JPH0786390A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase ground processes common to various types of product in number, to short a TAT, and to lessen photomasks required in a manufacturing process in number of pieces. CONSTITUTION:Arsenic ions are implanted into all the surface of a P-type semiconductor substrate 1 for the formation of an N<+> buried layer 2, and an N-type epitaxial layer 3 is made to grow thereon. Boron ions are introduced to form a P-type diffusion layer 4 which serves as a base region, and furthermore phosphorus ions or the like are introduced into all the surface to form an N-type diffusion layer 5 which serves as an emitter region. A trench-type isolation layer 6 which isolates devices from each other is formed, and an oxide film 7 is formed on the substrate 1. Contact holes 8a to 8c whose inner faces are coated with nitride film are provided so as to lead out the regions of a transistor, and. each of the contact, holes 8a to 8e is filled with a tungsten film 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a common process common to products such as a gate array bipolar type logic circuit manufacturing method and an individual process for each product. The present invention relates to a manufacturing method of a semiconductor integrated circuit provided.

[0002]

2. Description of the Related Art A conventional method for manufacturing a semiconductor integrated circuit is shown in FIG.
Will be described with reference to. First, the n ⁺ type buried layer 2b is selectively formed on one main surface of the p type semiconductor substrate 1, and silicon is grown on the entire surface to form the n type epitaxial layer 3 [(a) of FIG. 7]. . Next, the n-type epitaxial layer 3 and the buried layer 2 are penetrated from the upper part to the lower part, and the semiconductor substrate 1
A trench reaching the depth is formed, and the trench is filled with an insulator to form a trench type separation layer 6. As a result, the element formation regions are electrically separated from each other. Next, phosphorus is selectively diffused to a high concentration to form a collector extraction region 2c [(b) of FIG. 7].

Next, boron is selectively introduced into the epitaxial layer 3 surrounded by the trench type isolation layer 6 by an ion implantation method or a thermal diffusion method to form a p-type diffusion layer 4b.
Further, arsenic is selectively ion-implanted or thermally diffused into the p-type diffusion layer 4b to form the n-type diffusion layer 5b. Finally, an oxide film 7 is formed on the entire main surface of the semiconductor substrate, contact holes are opened, and collector electrodes 12a,
The base electrode 12b and the emitter electrode 12c are formed [(c) of FIG. 7]. This prior art is disclosed in, for example, Japanese Patent Laid-Open No. 59-59
-43565 gazette. A process flow of this manufacturing method is shown in FIG.

[0004]

In the conventional method for manufacturing a semiconductor integrated circuit described above, the n ⁺ -type buried layer 2a, the trench-type isolation layer 6, the collector lead-out region 2b, the p-type diffusion layer 4b and the n-type diffusion layer 5b are used. Etc. have been formed using their own photomasks. Therefore, when it is necessary to change the size or layout of transistors and other elements due to defects in the circuit configuration during the development of semiconductor integrated circuits, reconsider and correct all patterns including the element isolation pattern. After that, all the photomasks had to be manufactured again, and there was a problem that the development period was prolonged. In addition, the conventional manufacturing method has a problem that the manufacturing period is prolonged due to the large number of photolithography steps.

[0005]

According to a method of manufacturing a semiconductor device of the present invention, a buried layer of a second conductivity type (a second conductivity type buried layer forming a collector region over the entire main surface of a first conductivity type semiconductor substrate (1)) is provided. 2), a step of forming a second conductivity type epitaxial layer (3) forming a collector region on the entire surface thereof, and a step of forming the first conductivity in the entire surface area of the second conductivity type epitaxial layer. By introducing a type impurity or by growing an epitaxial layer containing an impurity of the first conductivity type on the entire surface of the second conductivity type epitaxial layer to form a base region of the first conductivity type impurity layer (4, Four
a), a step of forming a diffusion layer (5, 5a) of the second conductivity type which constitutes an emitter region in the surface region of the impurity layer of the first conductivity type, and electrically between the elements. Forming a separation region (6) for separation.

A second portion forming the emitter region
The conductivity type diffusion layer (5) can be formed in the entire surface region of the first conductivity type impurity layer (4). In addition, after the step of forming the isolation region (6),
An insulating film (7) is formed on the entire surface to expose the surfaces of the collector region (2), the base region (4) and the emitter region (5), and a contact hole (8a) whose side wall is covered with an insulating film (9). , 8b, 8c) and filling the inside of the contact hole with a conductor (10) can be added.

[0007]

Embodiments of the present invention will now be described with reference to the drawings. 1 (a) to (d) to FIG. 2 (a) to
FIG. 3C is a sectional view showing the state of the npn-type bipolar transistor in each process step of the first embodiment of the present invention in the order of processes. First, as shown in FIG.
Arsenic (As) is ion-implanted on the entire surface of the type semiconductor substrate 1 to form an n ⁺ type buried layer (impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ ) 2 which will be a part of the collector region, and then formed thereon. By growing silicon containing phosphorus (P) as an impurity,
The n-type epitaxial layer 3 is formed.

Next, as shown in FIG.
Boron (B) is added to the entire surface of the epitaxial layer 3 by 2
Ions are implanted so as to have an impurity concentration of about × 10 ¹⁸ cm ⁻³ to form a p-type diffusion layer 4 serving as a base region. Then, as shown in FIG. 1C, arsenic is ion-implanted into the entire surface of the p-type diffusion layer 4 so as to have an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ to form an emitter region n. The mold diffusion layer 5 is formed. This is the end of the first half of the manufacturing method of this embodiment. The steps up to this point complete the formation of all diffusion layers of the transistor.

Next, as shown in FIG. 1 (d), based on a pattern of a semiconductor integrated circuit designed to perform a desired function, a groove for partitioning each element is formed into an n ⁺ type buried layer 2
To a depth that completely penetrates the trench, and the trench is filled with an insulator to form a trench type isolation layer 6 for electrically isolating the elements. Here, as a material for filling the groove, BPSG, which has a high embedding property, is used.

Next, as shown in FIG. 2A, CVD
By a (Chemical Vapor Deposition) method, SiO ₂ is deposited to a film thickness of about 5000 Å to form an oxide film 7.
After that, contact holes 8a, 8b, 8c reaching the n ⁺ type buried layer 2, the p type diffusion layer 4, and the n type diffusion layer 5 are formed, respectively. Here, the contact holes 8a, 8b, 8
Although the order of opening c is arbitrary, it is better to open the contact holes 8c in order from the shallowest depth.

Next, as shown in FIG. 2B, CVD
Then, a nitride film 9 is grown to a thickness of about 1000 Å on the entire surface by the method, and the anisotropic dry etching is performed to etch back the nitride film 9 by an amount corresponding to the film thickness to leave it only on the inner wall of the contact hole. Next, in order to form the electrode lead-out portion, C
A tungsten film 10 is grown on the entire surface by the VD method and etched back to fill the contact holes 8a, 8b, 8c with the tungsten film 10 as shown in FIG.
To form.

FIG. 3A is a process flow chart showing the process sequence of the manufacturing method of this embodiment. According to this manufacturing method, if the transistor size or the like is changed after the completion of the trial manufacture, the steps after the element isolation step can be changed.
Compared with the conventional example [see (b) of FIG. 3], in which almost all the processes need to be reviewed when the design is changed, the TAT (Turn Around Time) for developing a semiconductor integrated circuit can be significantly shortened. it can. In this case, for example, if the wafer shown in FIG. 1C in which the emitter region has been formed is stored and used, more efficient development is possible and the number of manufacturing steps can be shortened. it can. In addition to this, according to the present embodiment, the photomask for forming the n ⁺ -type buried layer 2a, the collector lead-out region 2b, the p-type diffusion layer 4b and the n-type diffusion layer 5b, which is required in the conventional example, is unnecessary. Therefore, even if the number of photomasks for forming contact holes is increased, the semiconductor integrated circuit can be manufactured with a smaller number of photomasks, and from this point, the development period and the manufacturing period can be shortened.

Next, referring to FIGS. 4 and 5, the second embodiment of the present invention will be described.
An example will be described. 4A to 4C to 5A to 5C are cross-sectional views showing the state of the npn-type bipolar transistor in each process step of the second embodiment of the present invention. As shown in FIG. 4A, n is formed on the p-type semiconductor substrate 1 as in the case of the first embodiment.
^{The +} type buried layer 2, the n type epitaxial layer 3, and the p type diffusion layer 4 are sequentially formed, and subsequently, as shown in FIG. 4B, the n type diffusion layer 5 is formed to electrically connect the elements. A trench type separation layer 6 is formed to be separated into.

Next, as shown in FIG. 4C, the film thickness 5
After forming the oxide film 7 of about 000Å by the CVD method,
After the first nitride film 11a is grown on the entire surface, patterning is performed so as to cover the contact hole formation portion for drawing the base electrode and the contact hole formation portion for drawing the emitter electrode. Subsequently, as shown in FIG. 5A, a second nitride film 11b is deposited on the entire surface and patterned so as to cover the contact hole formation portion for drawing out the emitter electrode.

Next, as shown in FIG. 5B, a photolithography method and a dry etching method are applied,
Contact holes 8a, 8b and 8c for drawing out the collector, base and emitter regions are simultaneously formed.
Here, the film thicknesses of the nitride films 11a and 11b are determined so that each contact hole reaches the appropriate depth of each diffusion layer. Next, the first and second nitride films 11a and 11b are removed by wet etching.

Next, as shown in FIG. 5C, the nitride film 9 is formed only on the side wall of each contact hole as in the first embodiment, and then tungsten is grown on the entire surface. Then, by etching back, the tungsten film 10 is buried in the contact holes 8a, 8b, 8c. In the second embodiment, the contact hole 8
By forming a, 8b, and 8c at the same time, the distance between the contact holes, that is, the distance between the electrodes can always be kept constant, and stable transistor characteristics can be obtained.

6 (a) to 6 (c) are process sectional views showing in sequence the manufacturing process of the third embodiment of the present invention. First,
As shown in FIG. 6A, arsenic (As) is ion-implanted on the entire surface of the p-type semiconductor substrate 1 to form an n ⁺ -type buried layer 2 which becomes a part of the collector region, and phosphorus is formed thereon. 1 x 10
Silicon containing at a concentration of ¹⁸ cm ⁻³ is grown to form an n-type epitaxial layer 3, and then boron is added at 2 × 10 5.
Silicon having a concentration of ¹⁸ cm ⁻³ is grown to form a p-type epitaxial layer 4a to be a base region. In this embodiment, the steps up to this point are common processes, and the steps thereafter are individual processes according to the semiconductor integrated circuit.

Next, based on the pattern design of the semiconductor integrated circuit, arsenic is ion-implanted so as to have an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ , and as shown in FIG. A collector extraction region 2a and an n-type diffusion layer 5a to be an emitter region are formed. Next, as shown in (c) of FIG. 6, a trench type isolation layer 6 for isolating each element,
A trench type isolation layer 6a for separating the collector extraction region 2a from the base region is formed. The separation layer 6a can be omitted if there is no problem in transistor performance. After that, an oxide film is formed on the semiconductor substrate by a conventional method, a contact hole exposing the surface of each region is formed, and an electrode that contacts each region through the contact hole is formed.

In this embodiment, the collector lead-out region forming step and the emitter region forming step are individual processes for each integrated circuit, but since the base region is formed in common, the same process as the previous embodiment is performed. Therefore, TAT can be shortened. Further, according to the present embodiment, the photomask for forming the n ⁺ type buried layer 2a and the p type diffusion layer 4b, which is required in the conventional example, is not required, and the trench type for insulating the collector extraction region 2a is eliminated. Even if a photomask is used to form the separation layer 6a, the number of photomasks required can be reduced as compared with the case of the conventional example.

The preferred embodiment has been described above.
The present invention is not limited to these examples, and various modifications can be made within the scope of the present invention. For example, all the impurity conductivity types in the embodiments can be reversed, and the base regions (p) in the first and second embodiments can be reversed.
The method of forming the type diffusion layer 4) can be changed from the diffusion method to the epitaxial growth method, and the third embodiment shown in FIG. 6 is modified to form the collector extraction region 2a and the n-type diffusion layer 5a. Prior to this, the trench type isolation layers 6 and 6a may be formed.

[0021]

As described above, according to the method of manufacturing a semiconductor integrated circuit of the present invention, after the collector region, the base region, or even the emitter region is formed on the entire main surface of the semiconductor substrate, Since the elements are separated based on the specifications of individual semiconductor integrated circuits to form the individual transistors, the underlying process can be widely shared among products and the TAT can be shortened. Further, since the number of steps for the individual integrated circuit is reduced, the circuit configuration can be easily changed during the manufacturing process. Further, since the photolithography process is reduced, the process can be simplified and the manufacturing period can be shortened.

[Brief description of drawings]

FIG. 1 is a part of a process sectional view of a first embodiment of the present invention.

FIG. 2 is a part of the process sectional view of the first embodiment of the present invention.

FIG. 3 is a process flow chart of the first embodiment of the present invention and a conventional example.

FIG. 4 is a part of the process sectional view of the second embodiment of the present invention.

FIG. 5 is a part of the process sectional view of the second embodiment of the present invention.

FIG. 6 is a process sectional view of a third embodiment of the present invention.

FIG. 7 is a process sectional view of a conventional example.

[Explanation of symbols]

1 p-type semiconductor substrate 2, 2b n ⁺ -type buried layer 2a, 2c collector extraction region 3 n-type epitaxial layer 4, 4b p-type diffusion layer 4a p-type epitaxial layer 5, 5a, 5b n-type diffusion layer 6, 6a trench type Separation layer 7 Oxide film 8a, 8b, 8c Contact hole 9 Nitride film 10 Tungsten film 11a First nitride film 11b Second nitride film 12a Collector electrode 12b Base electrode 12c Emitter electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/73

Claims (6)

[Claims] 1. A step of forming a second conductive type buried layer forming a collector region over the entire one main surface of a first conductive type semiconductor substrate, and a second step of forming a collector region over the entire upper surface thereof.
Forming a conductive type epitaxial layer;
A first conductivity type impurity is introduced into the entire surface region of the conductivity type epitaxial layer, or an epitaxial layer containing the first conductivity type impurity is grown on the entire surface of the second conductivity type epitaxial layer to form a base region. A step of forming a first-conductivity-type impurity layer that constitutes the element, a step of forming a second-conductivity-type diffusion layer that constitutes an emitter region in the surface area of the first-conductivity-type impurity layer, and And a step of forming an isolation region that electrically isolates the semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the diffusion layer of the second conductivity type forming the emitter region is formed in the entire surface region of the impurity layer of the first conductivity type. Manufacturing method. 3. After the step of forming the isolation region, an insulating film is formed on the entire surface to expose the surfaces of the collector region, the base region and the emitter region to form a contact hole whose side wall is covered with the insulating film. 3. The method of manufacturing a semiconductor integrated circuit according to claim 1, further comprising a step of filling the inside of the contact hole with a conductor. 4. A step of forming a buried layer of a second conductivity type forming a collector region over the entire one main surface of a semiconductor substrate of the first conductivity type, and a second step of forming a collector region over the entire surface thereof.
Forming a conductive type epitaxial layer;
A first conductivity type impurity is introduced into the entire surface region of the conductivity type epitaxial layer, or an epitaxial layer containing the first conductivity type impurity is grown on the entire surface of the second conductivity type epitaxial layer to form a base region. A step of forming a first conductivity type impurity layer constituting the element, a step of forming an isolation region electrically separating the elements, and an emitter region formed in the surface area of the first conductivity type impurity layer. And a step of forming a diffusion layer of the second conductivity type. 5. The semiconductor integrated circuit according to claim 1, wherein the diffusion layer of the second conductivity type forming the emitter region is formed in the entire surface region of the impurity layer of the first conductivity type. Manufacturing method. 6. An insulating film is formed on the entire surface after the step of forming the diffusion layer of the second conductivity type to expose the surfaces of the collector region, the base region and the emitter region, and the side walls are covered with the insulating film. 6. The method for manufacturing a semiconductor integrated circuit according to claim 4, further comprising the step of forming a contact hole and filling the inside of the contact hole with a conductor.