JPH0785601A - Magnetic storage device - Google Patents

Abstract

PURPOSE:To make a magnetic storage device high in density and reliability by providing a timing control circuit for updating equalization coefficients in an adaptive equalizer and stopping and resuming equalization coefficient updation in accordance with the interruption and resumption of data reading. CONSTITUTION:After outputs delayed by delay circuits 101 and 102 are added by an adder 103, a reproduced signal Xn to be inputted to an equalizer 130 is multiplied by the coefficients for deciding an equalization amount by a multiplier 107. This output and the output delayed by the circuit 101 are added by an adder 108 and an equalization output Yn is obtained. Based on the gradient information of coefficients obtained at a gradient generating part 128 by outputs from the adders 103 and 108, equalization coefficients are supplied from an equalization coefficient renewing part 125. In this case, the stopping and resuming of equalization coefficient updation are controlled in accordance with the time of interruption and resumption of data reading by a timing control circuit 119 and an equalization coefficient after stop is held at the same value as before the stop. Thus, a training pattern is eliminated after the interruption of the data reading in the same sector.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic storage device capable of high speed operation and large capacity.

[0002]

2. Description of the Related Art In a magnetic storage device such as a magnetic disk device (for example, a hard disk device), one of signal processing techniques for achieving high density and high reliability is, for example, US Pat. No. 5,060,088. The importance of the adaptive equalizer as shown in (3) is increasing. FIG. 4 shows an example of the configuration of the adaptive equalizer.

The adaptive equalizer shown here delays an input waveform sample value through a two-stage delay circuit consisting of a first delay circuit 41 and a second delay circuit 42, and a waveform sample which does not give any delay. Value is added by the first adder 43, and the added value by the first adder 43 is multiplied by the multiplier 44.
A second adder that corrects the input waveform sample value by delaying it through a delay circuit of one stage including only the first delay circuit 41. And the equalizer waveform sample value output is obtained.

On the other hand, the output of the first adder 43 and the second output
And the output of the adder 45 of the above are given to the gradient calculating circuit 46, the gradient of the coefficient is obtained here, and given to the third adder 47. Third
The output from the third delay circuit 48 is given to the adder 47 of the above, and the third adder 47 adds both inputs and gives to the third delay circuit 48. The third delay circuit 48 delays this by a predetermined time, feeds it back to the third adder 47, and supplies it to the multiplier 44 as a multiplication coefficient.

To the second adder 45, the input waveform sample value is given as it is, and the added value obtained by delaying by two stages is given as one input, and the input waveform sample value is given one stage. Since a signal delayed by a minute is given as the other input, if the former of the two types of inputs is given with a polarity opposite to that of the latter, the waveform obtained by subtracting the former waveform from the latter waveform is the second one. Since it is obtained from the adder 45, the first
By setting the delay amounts of the second delay circuits 41 and 42 to appropriate values so that the peak areas of the waveforms do not overlap with each other, the sample values of the blunted input waveform can be equalized.

Then, from the value thus obtained and the value of the output of the first adder 43, the gradient calculation circuit 46
The gradient required for equalization is calculated, and this is calculated by the third delay circuit 48.
Is added together with the value obtained via the third adder 47 and is given to the multiplier 44 via the third delay circuit 48 as a coefficient, so that the optimum equalization processing is performed.
The level of the former signal is adjusted.

Since this adaptive equalizer can dynamically correct the fluctuation of the reproduced waveform, it is particularly effective when the waveform varies depending on the position of the cylinder, such as the reproduced signal of the magnetic disk device. However, in order to make the equalization amount follow this fluctuation amount with a minimum delay, when operating the adaptive equalizer, it is necessary to input a waveform of a specific data pattern called a training pattern in the initial operation thereof.

FIG. 5 shows one sector of the format on the data track which is provided with the training pattern. As shown in FIG. 5, the format on the data track of a recording device in which the waveform varies depending on the cylinder position such as a magnetic disk device has a gap 1108 in which several tens of sectors composed of fields 1101 to 1107 are formed. They are separated and lined up.

Here, 1101 is a sync field, 1102 is a training field, and 110
3 is an ID field, 1104 is a gap, 1105 is a sync field, 1106 is a training field, and 1107 is a data field. These constitute one sector, and a gap 1108 is provided behind it, and this gap 1108 serves as a sector delimiter.

When accessing the data of a certain sector, first, the frequency (phase) of the phase lock loop (PLL) for timing clock recovery is used by using the pattern written in the sync field 1101.
Perform retraction.

Next, the training field 1102
The equalization amount of the adaptive equalizer is adjusted to an appropriate value in the waveform pattern portion of. That is, the coefficient of the multiplier indicated by reference numeral 1001 in FIG. 4 is converged to an appropriate value using a recursive least squares (RLS) algorithm or the like.

After ensuring proper operation of the signal processing circuit by these calibrations, the ID field 1
The information of 103 is read and it is determined whether or not the sector is an access target. Gap field 1104
Is an area for absorbing the discontinuous portion of the waveform of the ID information (identification information) written when initializing (formatting) the data track and the information of the data field that is rewritten after that. Even if the access is to read, if this part is read as it is, the operation of the PLL is disturbed due to this discontinuity.

Therefore, even in the sector to be read-accessed, the read gate signal is disabled in this portion, and the read operation is completed. If it is the sector to be read, the series of operations performed from the field 1101 is repeatedly performed from the sync field 1105 to thereby obtain the data field 110.
Read the data written in 7. Therefore, in order to handle such a case, the sync field 1
105, the control information of the control fields such as the training field 1106 is required prior to reading the data field, and the user data area in the total track capacity is reduced accordingly, and the ratio of the user data capacity is reduced. , The format efficiency decreases.

In other words, because of the gap field 1104, even in the sector to be read-accessed, the read operation is once terminated in this portion, then the synchronization is regained, and the data written in the data field 1107 is read. put out. A control field for that purpose is needed after the gap, and the area that should be secured as the user data area is consumed by that much, and the capacity of the user data area is reduced.

Further, as a conventional technique for increasing the density of a magnetic storage device, there are a system called a sector servo system and a system called zone bit recording (ZBR), which are widely used especially in a device having a small disk diameter. Has been. Of these, the sector servo type is
Of the multiple magnetic recording disk surfaces, all surfaces are provided for data recording without having a servo surface on which only tracking servo information is written. Servo information is recorded at a specific position on the data track. It is a method of embedding. In a device other than the ZBR system, the gap 110 in FIG.
This information is embedded in the position corresponding to 8.

The ZBR system is a technique for increasing the device capacity by bringing the recording density on the disk surface to a nearly uniform state. Since the recording tracks formed concentrically on the disk surface have different lengths on the inner and outer circumferences,
If writing is performed at the same frequency on a disk having a constant rotation speed, the recording density on the inner circumference is high and the recording density on the outer circumference is low.

Therefore, if the recording frequency is made variable so that the recording density is constant in every recording track, the amount of information that can be recorded can be increased in the recording tracks on the outer peripheral side. However, even if the recording frequency is changed very finely, the cost performance is not improved. Therefore, the recording frequency is usually changed for each zone.

The position of the servo information when the sector servo system and the ZBR system are used together is schematically shown in FIG. 6 by taking the case of 4 zones as an example. A thick line area indicated by reference numeral 1200 indicates servo information, and a zone indicated by reference numeral 1201 in the recording track is 4 sectors, 12 zones.
It is assumed that the zone denoted with 02 is 5 sectors, the zone denoted with 1203 is 6 sectors, and the zone denoted with 1204 is 7 sectors.

FIG. 6A shows a case where the servo information embedding positions are between sectors, as in the case where the ZBR method is not used together, and FIG. 6B shows that the servo information is arranged radially. It is an example arranged in.

In this example, in the case of (a), the method of accessing the data in the sector is the same as the conventional method.
On the other hand, it is not necessary to perform special control, but when performing seek operation across zones, the number of servo information samples changes at the zone boundaries, so it is necessary to switch the control corresponding to that. , Seek performance deteriorates because a guard band is required at the zone boundary for this detection.

On the other hand, in the method (b), since the servo information interrupts the middle of the sector information, special control is required to jump over this portion when accessing the data in the sector. You don't have to sacrifice performance.

The disk device is required to have a large capacity and a high-speed access, but most of the access time is occupied by the operating time of the mechanical part. Therefore, sacrificing seek performance is equivalent to giving up on shortening access time.

FIG. 7 shows a format on the data track when the method of FIG. 6B is used, and shows an example of one sector among them.
The sync field 1101 to the training field 1106 are the same as the format shown in FIG. 5, and the control operation during this is as described above.

The difference here is the reference numerals 1301 and 130.
The data field indicated by reference numerals 5, 1309 is divided by the servo patterns indicated by reference numerals 1302, 1306.

Since the servo patterns 1302 and 1306 are patterns written with a clock having a frequency different from that of the data, this portion corresponds to the gap field 110.
As in the discontinuous area of 4, the read gate signal must be disabled to interrupt the data read operation. Therefore, in order to restart the reading of the data fields such as the data field 1305 and the data field 1309 after being divided by the servo pattern, the same sequence of operations as at the start of reading from the sync field 1101 is performed. A PLL synchronize field, shown as 1303 and 1307, and a training pattern field for the adaptive equalizer, shown as 1304 and 1308, are provided.

[0026]

As described above, in a large-capacity magnetic recording device such as a hard disk device, when reading data in a sector, it is not necessary to perform a write operation, but an ID field and a data field The read is interrupted to skip the discontinuities in the intervening waveform.

A PLL synchronize field and a training pattern field for the adaptive equalizer are provided prior to the data field as a field for the control data necessary for resuming the read operation. Is decreasing
It prevents the capacity of the user data area from increasing.

Further, in the disk device using the sector servo system and the ZBR system, when the seek performance is not deteriorated, the information of the sector is divided by the servo information in the middle. Also in this case, the PLL sync field and the adaptive equalizer training pattern field are added prior to the field immediately after the division in order to restart the reading interrupted by the servo information.

These fields are exhausting the storage capacity that can be used for user data storage.
There is a problem that a part of the increased track capacity due to the adoption of the ZBR system is offset.

The present invention has been made in view of the above points, and an object of the present invention is to provide a sector servo system and a ZBR system even if the data format is divided in a discontinuous area of the waveform. As is remarkable in the case of a device that also uses, the higher density and more reliable magnetic recording can be achieved without reducing the format efficiency due to the repeated provision of the training pattern field for the adaptive equalizer. It is to provide a magnetic recording device that can be used.

[0031]

In order to achieve the above object, the present invention is configured as follows. That is, in a magnetic storage device which performs a reproduction signal processing of an adaptive equalization system on a reproduction signal input read from a magnetic disk, a delay for giving at least two different delay amounts to the reproduction signal input and outputting it. Circuit, a reproduction signal input read from the magnetic disk and a reproduction signal given one of the two delay amounts obtained by the delay circuit are added to obtain an equalization amount. And a second synthesis unit that outputs a corrected synthesis reproduction signal by correcting the synthesis reproduction signal output of the first synthesis unit for the coefficient for determining the equalization amount. Section, and a third synthesizing section for synthesizing an output of the second synthesizing section with a reproduced signal given the other delay amount of the two types by the delay circuit to obtain an equalized output. And a first combining section and a third combining section A gradient generator for generating gradient information of the coefficient from the equalization output from the equalizer, and an equalization coefficient updater for receiving the gradient information of the coefficient output by the gradient generator and supplying the coefficient for determining the equalization amount. And an adaptive equalization circuit unit having a fourth synthesis unit for obtaining a coefficient for determining the equalization amount, and a timing control circuit for controlling the update timing of the equalization coefficient update unit, The timing control circuit has a control function of stopping the update of the equalization coefficient when the reading of the data area of the magnetic disk is interrupted and restarting the update when the data reading is restarted, and the equalization coefficient updating unit. Has a holding function to hold the equalization coefficient at the time of the stop during the update stop.

[0032]

The adaptive equalizer has an advantage that the equalization error can be suppressed to be smaller than that of the equalizer which only gives a constant equalization amount by dynamically correcting the fluctuation of the reproduced waveform. The control time constant is set to be relatively large because it should not be made to follow the rapid fluctuation of. That is, it can be considered that the equalization amount does not significantly change before and after the interruption of the reading in the same sector. Therefore, if the timing of read interruption in the same sector is detected and the equalization amount before the interruption is held until after the interruption, the training pattern after the interruption can be omitted. I'm done.

The present invention is based on this point of view.
Referring to FIG. 1, the delay circuit (101, 10
In 2), at least two different delay amounts are given to the reproduction signal input read from the magnetic disk. On the other hand, the first combining unit (first adder 103) is one of the two types of delay amounts obtained by the reproduction signal input read from the magnetic disk and the delay circuits 101 and 102. Is added to the given reproduction signal to output a combined reproduction signal that is the basis of the equalization amount.

The second synthesizer (first multiplier 107) is
The combined reproduction signal output of the first combining unit (first adder 103) is corrected by a coefficient for determining the equalization amount and output as a corrected combined reproduction signal. Further, the third synthesizing unit (second adder 108) reproduces the reproduction signal given the delay amount of the other of the two types by the delay circuit and the second synthesizing unit (first multiplier 107). And the output of are combined to obtain an equalized output.

The gradient generator (calculator 128) calculates the coefficient from the equalized outputs from the first synthesizer (first adder 103) and the third synthesizer (second adder 108). The gradient information is generated, and the equalization coefficient updating unit 125 receives the gradient information of the coefficient output from the gradient generating unit (calculating unit 128) and supplies the coefficient for determining the equalization amount. Then, the adaptive equalization circuit unit obtains the coefficient for determining the equalization amount.

Further, the timing control circuit 119 controls the timing of coefficient updating of the equalization coefficient updating section (equalization coefficient adjusting section 129), but the timing control circuit 119 reads the data area of the magnetic disk. There is a control function of stopping the update of the equalization coefficient at the time of the interruption and restarting the update at the time of restarting the reading of the data. The equalization coefficient updating unit 125 outputs the equalization coefficient at the time of the stop during the update stop. There is a holding function to hold.

According to the present invention, the timing of the read interruption in the same sector is detected, and the equalization coefficient before the interruption is held until after the interruption. The equalization process can be restarted. Therefore, even if a gap is formed in the same sector, the optimum equalization coefficient can be obtained without providing a training pattern for obtaining the equalization coefficient after the gap. Since the training pattern can be omitted, especially in a disk device that uses both the sector servo method and the ZBR method,
Even when the information of the same sector is frequently divided in the discontinuous area of the waveform, it is possible to provide a magnetic recording apparatus having higher density and higher reliability without lowering the format efficiency.

[0038]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of an adaptive equalizer according to the present invention, and FIG. 2 is an example of the configuration of a signal processing system of a magnetic recording apparatus equipped with the adaptive equalizer of FIG. It is a block diagram shown.

The structure of the signal processing system of the magnetic recording apparatus will be described. Reference numeral 201 denotes an electromagnetic conversion system, which is a magnetic disk (magnetic recording medium) and a magnetic recording / reproducing head, and these magnetic recording / reproducing heads are tracked on the magnetic disk. It consists of a head operation system that controls the movement of the position (seek).

Reference numeral 202 is a preamplifier, 203 is a variable gain amplifier (VGA), and 204 is an A / D converter. The reproduced waveform from the magnetic disk read by the head of the electromagnetic conversion system 201 is preamplified by the preamplifier 202. And the recording bit period T after being amplified by the VGA 203.
Is sampled and converted into a digital quantity Xn.
Reference numeral 205 denotes an adaptive equalizer according to the present invention. The adaptive equalizer 205 receives the sample value Xn, performs equalization processing on the sample value Xn, and outputs Yn as the equalization result.

The adaptive equalizer 205 has a function of sequentially updating the equalization coefficient used during the equalization process.
Further, it has a function of detecting a read interruption timing in the same sector, and when the read interruption timing in the same sector is detected, the equalization coefficient before the interruption of the adaptive equalization processing is retained even after the interruption. At the time of restarting the equalization process, it has a function of performing the equalization process using the held equalization coefficient. As a result, equalization at the time of restarting reading in the same sector can be performed without training.

Reference numeral 206 is a detector, and this detector 206 detects and outputs recording data from Yn which is the output of the adaptive equalizer 205.

Reference numeral 208 denotes a timing error detection unit that receives Yn as an input, detects the timing of read interruption, and adjusts the control voltage applied to the voltage controlled oscillator (VCO) 207 according to the waveform of the data in the sync field. And forms a timing / clock recovery circuit in cooperation with the voltage controlled oscillator 207. The timing / clock recovery circuit is a circuit that pulls in the frequency and phase of the voltage controlled oscillator 207 by using the waveform pattern of the sync field.

Reference numeral 209 is a gain error detection circuit for detecting an error of the signal level from Yn with respect to an appropriate level and outputting a gain control signal of a level capable of correcting the error. The gain of the VGA 203 is controlled by the gain control signal of the gain error detection circuit 209.

In such a configuration, the electromagnetic conversion system 20
1 for magnetic recording from a magnetic disk (magnetic recording medium)
The signal read by the reproducing head is supplied to the preamplifier 20.
Amplified by 2 and further variable gain amplifier (VGA) 20
After being amplified by 3, it is given to the A / D converter 204, where it is sampled at the recording bit period T and converted into a digital quantity Xn. This digital quantity Xn
Is given to the adaptive equalizer 205.

The adaptive equalizer 205 receives the sample value Xn as an input, performs equalization processing on the sampled value Xn, and outputs Yn as the equalization result.
Is output. The detector 206 detects and outputs recording data from Yn which is the output of the adaptive equalizer 205.

Further, the adaptive equalizer 205 successively updates the equalization coefficient used during the equalization process. When the timing of read interruption in the same sector is detected, the adaptive equalization processing is interrupted, but the equalization coefficient before this interruption is retained even after the interruption, and at the time of restarting the equalization processing, this retention is held. Equalization processing is performed using the equalized coefficient.

Therefore, it becomes possible to perform equalization at the time of resuming reading after interruption of reading in the same sector without training.

Further, the timing error detection unit 208 is set to Y
With n as an input, the timing of the read interruption is detected, and when the data of the sync field appearing after the gap is received, the voltage controlled oscillator (VC
O) Adjust the control voltage applied to 207. This allows
The frequency and phase of the voltage controlled oscillator 207 are pulled in, and the sampling timing of the A / D converter 204 is synchronized with the data. In addition, the gain error detection circuit 20
Reference numeral 9 outputs a gain control signal so that the signal level of Yn becomes an appropriate level. Therefore, the gain control signal from the gain error detection circuit 209 causes the VGA2
03 is controlled in gain, amplifies the input signal from the preamplifier 202 to an appropriate signal level, and A / D converter 2
Give to 04.

As described above, according to this apparatus, the timing of the read interruption in the same sector is detected, the equalization coefficient before the interruption of the adaptive equalization circuit is held after the interruption, and the held equalization is performed. By performing the equalization at the time of resuming reading in the same sector by using the coefficient, the training pattern after interruption can be omitted from the format. Therefore, in particular, a disk using both the sector servo method and the ZBR method Even if the information of the same sector is frequently divided in a discontinuous area of the waveform like a device, it is possible to realize a magnetic recording device with higher density and higher reliability without lowering the format efficiency. .

The above is the description of the operation of the signal processing system to which the adaptive equalizer 205 of the present invention is applied. The details of the adaptive equalizer 205 of the present invention will be described below. FIG. 1 is a block diagram showing a specific configuration example of the adaptive equalizer 205 of the present invention in the signal processing system having the configuration of FIG.

The adaptive equalizer 205 of the present invention delay circuits 101 and 1 which give at least two different delay amounts to the reproduction signal input read from the magnetic disk and output the same.
02, and the reproduction signal input read from the magnetic disk and the reproduction signal to which one of the two delay amounts obtained by the delay circuits 101 and 102 has been added. Equalization to a combined reproduction signal output of the first combining unit (first adder 103) and the first combining unit (first adder 103) that outputs a combined reproduction signal that is the basis of the conversion amount. A second synthesizing section (first multiplier 10) that corrects the coefficient for determining the amount and outputs a corrected synthetic reproduction signal.
7), and a second synthesis unit (first reproduction signal) given the delay amount of the other of the two types by the delay circuit.
Equalizer 1 having a third combiner (second adder 108) that combines the output of the multiplier 107 of
30 and a gradient generator (calculator) that generates coefficient gradient information from the equalized outputs from the first synthesizer (first adder 103) and the third synthesizer (second adder 108). 12
8) and an equalization coefficient updating unit 125 which receives the gradient information of the coefficient output from the gradient generation unit (calculation unit 128) and supplies the coefficient for determining the equalization amount,
An adaptive equalization circuit unit having a fourth synthesis unit (equalization coefficient adjustment unit 129) for obtaining a coefficient for determining the equalization amount; and updating of the equalization coefficient update unit (equalization coefficient adjustment unit 129). The timing control circuit 119 controls the timing, and the timing control circuit 119 stops the update of the equalization coefficient at the time when the data reading is interrupted, and at the time when the data reading is restarted. The control is also performed to restart the update of 1., and the equalization coefficient updating unit 125 is configured to have a function of holding the equalization coefficient at the time of the stop while the update is stopped.

A specific description will be given. The block 130 shown in FIG. 1 is a part constituting a basic cosine equalizer.

The cosine equalizer 130 is composed of first and second delay circuits 101 and 102, a first adder 103, a first multiplier 107, and a second adder 108.

Of these, the input 127 of the delay circuits 101 and 102 is the A / D converter (A
The output 104 of the / D converter) 204 is provided. Also,
The first adder 103 has A / A indicated by reference numeral 105.
A sample value Xn of the output 104 of the D converter 204,
The delayed output 126 of the second delay circuit 102, X _n−2, is given, and the first adder 103 adds them and sums U.
n is synthesized and output. The first multiplier 107 multiplies the value of the sum Un output from the first adder 103 by the value of the equalization coefficient Kn provided from the equalization coefficient adjusting unit 129, and the second adder 108. Is the sampled value X of the output 106 which is the delayed output of the first delay circuit 101
_n-1 is added to synthesize the equalized output value Yn which is the addition output 109.

The equalization coefficient adjusting section 129 is used for the second adder 10
It is the main part of the adaptive equalizer that outputs the equalization coefficient Kn with the equalization output value Yn that is the output of 8 and the sum Un that is the output of the first adder 103 as inputs.

The equalization coefficient adjusting unit 129 calculates the equalization coefficient based on the equalization output value Yn which is the output from the second adder 108 and the Un which is the output from the first adder 103. Calculating unit 128 for calculating the gradient ΔKn of
The equalization coefficient Kn is obtained based on the gradient ΔKn of the equalization coefficient obtained in step S8, and the equalization coefficient updating unit 125 for updating the equalization coefficient Kn is divided into two parts. In this embodiment, the operations of the calculation unit 128 and the equalization coefficient updating unit 125 are
It is based on a conventional algorithm for properly converging the equalization amount of the adaptive equalizer.

The timing control circuit 119 is a block for controlling the timing of changing the update characteristic of the equalization coefficient Kn in the equalization coefficient update section 125. Further, the loop formed by the third adder 115 and the delay element 116 constitutes an integral element, and 118 is an element which gives its initial value Ki.

Reference numeral 120 is a gate for passing a clock, and under the control of the timing control circuit 119, this gate 1
Reference numeral 20 controls the supply of the clock required to drive the delay element 116. The clock supplied to the gate 120 is a clock output from the voltage controlled oscillator (VCO) 207.

The delay element 116 takes in the quantized digital value of the input signal 132 supplied from the third adder 115 at the edge of the clock 131 supplied via the gate 120, and outputs the output signal 1 until the edge of the next clock.
This is a register held as 33. The clock required for the operation of the delay element 116 is configured to be supplied and controlled by the gate 120. Further, since the delay element 116 is composed of a register, the delay element 116 and the gate 120
The input signal 1 provided from the third adder 115
It is possible to obtain the sampling function of 32 and the function of holding this sampled data.

In the adaptive equalizer 205 composed of the discrete value-discrete time control system as shown in FIG.
01 and 102 are composed of registers synchronized with the sampling clock. If the head of the magnetic recording device seeks from a certain track on the magnetic disk surface to another certain track, then a read gate signal is issued from a system control block (not shown) and the signal processing circuit starts its operation. However, the timing control circuit 119 switches the switch 11 so that the value of the delay element (delay register) 116 at that time has an appropriate initial value Ki.
Switch 7

The adaptive equalizer, when reading the training pattern field on the format, rapidly adjusts the equalization coefficient according to the read waveform, and obtains stable operation in the other fields. It is necessary to increase the time constant of the response characteristic. CL of 113 and CH of 114 are elements that give a coefficient for obtaining such a response characteristic, and the timing control circuit 119 also controls the switching of the switch 112 according to the field.

Here, according to the data format and the time chart of FIG. 3, the adaptive equalization circuit 20 of the present invention will be described.
The operation of No. 5 will be described. In FIG. 3, reference numeral 301 indicates the on / off timing of the read gate signal. Also, 305 is a sector pulse, and this sector pulse 305 is a signal indicating the timing of the start of a sector in the format.

The system control circuit (not shown) is a sector
In synchronization with the pulse 305, the read gate 301 is turned on in the sync field 1101 portion. The timing clock recovery circuit composed of the voltage controlled oscillator (VCO) 207 and the timing error detection unit 208 in FIG. 2 uses the waveform pattern of the sync field to pull in the frequency and phase of the voltage controlled oscillator (VCO). To do. Here, the VCO is a circuit that generates a signal at a frequency corresponding to the input voltage.

The sampling clock of the A / D converter 204 in FIG. 2 is the voltage controlled oscillator (VC).
Since the clock output from (O) 207 is used, an accurate value cannot be obtained as the sample value Xn before the pull-in is completed. Therefore, the timing control circuit 119
The control line 123 of FIG. 1 is turned on in consideration of the timing sufficient for pulling in the timing recovery circuit.

When the control line 123 is turned on, the delay element 11 which is a delay register is passed through the gate 120 of FIG.
6 is supplied with a clock, and the equalization coefficient adjusting unit 129 of the adaptive equalizer 205 starts operating. Further, the timing control circuit 119 turns on the control signal 122 to supply the initial value to the delay element 116 and turns the switch 117 to the Ki side of 118 before turning on the signal line 123.
Further, immediately after the control line 123 is turned on and the clock is supplied to the delay element 116, the control signal 122 is turned off, and the switch 117 is switched to the output side of the third adder 115.

With a single frequency pattern in the sync field, the coefficient matching function of the adaptive equalizer does not work.
When the training field 1102 starts to be read out, the adjustment of the equalization coefficient starts to work, so that the timing control circuit 119 turns on the signal line 124 so that the switch 112 of FIG. Switch to the side.

As a result, the second multiplier 111 causes the coefficient C to increase the response speed with respect to the gradient ΔKn of the equalization coefficient output from the equalization coefficient calculator 110 in the calculation unit 128.
It is multiplied by H and given to the third adder 115. Delay element 1
Reference numeral 16 captures the output of the third adder 115 for each clock input and supplies it to the third adder 115 and the first multiplier 107. Then, this makes it possible to perform appropriate equalization processing.

Further, the training field 110
When the reading of 2 is completed, the timing control circuit 119 turns off the signal line 124 and switches the control signal 122 to the coefficient CL side for increasing the time constant of the response characteristic in order to stabilize the operation.

As a result, the second multiplier 111 multiplies the equalization coefficient Kn output from the equalization coefficient calculator 110 by the coefficient CL with which the time constant of the response characteristic becomes large, and then the third adder 115 outputs it. give. The delay element 116 takes in the output of the third adder 115 for each clock input and supplies it to the third adder 115 and the first multiplier 107. Then, as a result, stable equalization processing can be performed.

When the information in the subsequent ID field 1103 is read, the system control circuit 119 determines that the gap 110
At the beginning of 4, the read gate for opening and closing the read output of the read head in the hard disk is turned off.
The timing control circuit 119 turns off the output of the signal line 123 at the same time when the read gate turns off. When the output of the signal line 123 is turned off, the gate 120 is closed and the supply of the clock to the delay element 116 is stopped.

As a result, the delay element 116 formed of a register stops its operation, but the fetched data from the second multiplier 111 at the previous sampling time (the fetched data at the clock input last time (etc.) A value obtained by multiplying the gradient ΔKn of the conversion coefficient by the coefficient CL)) is held.

If the sector interrupted by the gap is the read access target sector, the system control circuit 119 causes the sync field 11 to read.
At 05, the read gate is turned on again. The timing clock recovery circuit composed of the voltage controlled oscillator (VCO) 207 and the timing error detection unit 208 of FIG. 2 uses the waveform pattern of the sync field to pull in the frequency and phase of the VCO.

The timing control circuit 119 turns on the control line 123 in FIG. 1 again in consideration of the timing sufficient for pulling in the timing recovery circuit. This causes the gate 120 to again supply the clock to the delay element 116, and the delay element 116 resumes operation. Delay element 116
Holds the data before interruption, so that the equalization coefficient Kn can be given to the first multiplier 107 immediately at the time of restarting the operation.

In the adaptive equalization circuit 205 of this embodiment, the delay element 116 outputs the quantized digital value of the input signal 132 supplied from the third adder 115 to the gate 120.
Is a register which takes in at the edge of the clock 131 given via the control signal and holds it as the output signal 133 until the edge of the next clock. Therefore, the equalization coefficient Kn at the time when the control line 123 is turned off is Will be held until.

At this time, the timing control circuit 119 is different from the case of the sync field 1101 in that the control signal 12
Since 2 is kept off, when the control line 123 is turned on and a clock is supplied to the delay element 116, which is a delay register, the adaptive equalizer uses the equalization coefficient when reading the ID field 1103. Starts to operate, and the information in the data field 1107 is continuously read.

Even after the interruption of the reading by the servo patterns 1302 and 1306, the same processing as in the case of the interruption by the gap field 1104 is performed and the reading is restarted.

As described above, according to the present device, the timing of the read interruption in the same sector is detected, the equalization coefficient before the interruption of the adaptive equalization circuit is held even after the interruption, and the held equalization coefficient is held. Since the equalization at the time of restarting reading in the same sector is performed by using
Even if the data area has a gap and the data area is divided, the optimum equalization coefficient can be secured without providing a training pattern for acquiring the equalization coefficient after the divided portion. The training pattern after interruption of data reading can be omitted from the format.

Therefore, even if the information of the same sector is frequently divided in the discontinuous area of the waveform, such as in a disk device using both the sector servo method and the ZBR method, the format efficiency is not deteriorated. In addition, a magnetic recording device with higher density and higher reliability can be realized.

The adaptive equalizer has an advantage that the equalization error can be suppressed to be smaller than that of the equalizer which only gives a constant equalization amount by dynamically correcting the fluctuation of the reproduced waveform. The control time constant is set to be relatively large because it should not be made to follow the rapid fluctuation of. on the other hand,
It can be considered that there is no large change in the equalization amount before and after the interruption of the reading in the same sector. Therefore, the timing of the interruption of the reading in the same sector is detected, the equalization amount before the interruption is held until after the interruption, and the equalization is performed using the equalization coefficient at the time of resuming the reading after the termination of the interruption. By doing so, the training pattern after the end of the interruption can be omitted, and accordingly, the format efficiency does not decrease. Therefore, according to the present invention, even if the data format is divided in the discontinuous area of the waveform, it is notable for the adaptive equalizer as is remarkable especially in the case where the sector servo system and the ZBR system are used together. It is possible to perform magnetic recording with higher density and higher reliability without lowering the format efficiency due to the repeated provision of the training pattern field of 1., and to increase the user data area capacity.

The present invention is not limited to the embodiments described above and shown in the drawings, but can be appropriately modified and implemented within the scope of the invention.

[0083]

As described in detail above, according to the present invention,
By detecting the timing of read interruption in the same sector and holding the equalization coefficient before interruption of the adaptive equalization circuit until after interruption, the training pattern after interruption can be omitted from the format. So, especially,
Even when the information of the same sector is frequently divided in a discontinuous area of the waveform, such as in a disk device that uses both the sector servo method and the ZBR method, the user data can be reproduced without lowering the format efficiency. The capacity of the area can be increased, and a magnetic recording device with higher density and higher reliability can be realized.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention,
FIG. 3 is a diagram showing a configuration of an adaptive equalization circuit according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram for explaining an embodiment of the present invention,
The block diagram which shows an example of a structure of the signal processing system of the magnetic memory device of this invention.

FIG. 3 is a diagram for explaining an embodiment of the present invention,
The figure which shows the data format and the timing of a signal which concern on the Example of this invention.

FIG. 4 is a diagram for explaining a conventional example and is a diagram showing a configuration of a conventional adaptive equalization circuit.

FIG. 5 is a diagram for explaining a conventional example, showing a conventional data format.

FIG. 6 is a diagram for explaining a conventional example and is a diagram for explaining positions of servo information.

FIG. 7 is a diagram for explaining a conventional example, showing a data format of a sector divided by servo information.

[Explanation of symbols]

 101 ... 1st delay circuit 102 ... 2nd delay circuit 103 ... 1st adder 108 ... 2nd adder 107 ... 1st multiplier 110 ... Block 111 which calculates the gradient of an equalization coefficient 111 ... 2nd Multiplier 115 ... third adder 116 ... delay element 119 ... timing control circuit 120 ... gate 125 ... equalization coefficient update unit 128 ... calculation unit 129 ... equalization coefficient adjustment unit 130 ... cosine equalizer 201 ... electromagnetic conversion System 202 ... Preamplifier 203 ... Variable gain amplifier (VGA) 204 ... A / D converter 205 ... Adaptive equalizer 206 ... Detector 207 ... Voltage controlled oscillator (VCO) 209 ... Gain error detection circuit

Claims (1)

[Claims] 1. A magnetic storage device for performing reproduction signal processing of an adaptive equalization system on a reproduction signal input read from a magnetic disk, wherein at least two different delay amounts are given to the reproduction signal input. An equalization amount by adding a delay circuit for outputting, a reproduction signal input read from the magnetic disk, and a reproduction signal given one of two types of delay amounts obtained by the delay circuit. A first synthesizing section for outputting a synthesized playback signal which is the basis of And a reproduction signal given a delay amount of the other one of the two types by the delay circuit and a second synthesis unit.
Equalizer having a third synthesizing unit for synthesizing the output of the synthesizing unit and an equalized output, and gradient information of coefficients from the equalized outputs from the first synthesizing unit and the third synthesizing unit. And a equalization coefficient updating unit 125 that receives the gradient information of the coefficient output from the gradient generation unit and supplies the coefficient for determining the equalization amount. An adaptive equalization circuit unit having a fourth synthesizing unit for obtaining a coefficient for controlling the timing, and a timing control circuit for controlling the update timing of the equalization coefficient updating unit. Is provided with a control function of stopping the update of the equalization coefficient at the time when the reading of the data area is interrupted and restarting the update at the time when the data reading is restarted, and the equalization coefficient updating unit 125 is stopped while the update is stopped. Equalizer at the time Magnetic memory device is characterized in that a configuration which gave a holding function of holding the.