JPH0785356B2 - Memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a capacitor for accumulating an information signal as a charge and a switching which is connected between the capacitor and a bit line and operates according to a selection signal of a word line. So-called DRAM having an element
The present invention relates to a memory device such as (dynamic RAM).

[Outline of Invention]

The present invention relates to a memory device having a capacitance for accumulating an information signal as electric charge and a switching element connected between the capacitance and a bit line and operating according to a selection signal of a word line. Is composed of at least two gate portions, the electric field concentration in the switching element is relaxed and the leak current is reduced.

[Conventional technology]

In general, research and development of a memory device such as a DRAM that stores and holds an information signal in the capacity of a memory cell in the form of electric charge is under way. First, the conventional 1-transistor / 1-cell type DRAM
An example will be described with reference to FIG.

FIG. 3 is an equivalent circuit of a part of the memory cells of the memory device. The gates of the switching transistors T _r of the memory cells are word lines WL _N-2 , WL to which selection signals are applied.
_N-1 , WL _N , WL _{N + 1} , etc., and _one of the drain and the source of the switching transistor T _r of each memory cell is connected to a capacitor C _M that stores and holds an information signal in the form of electric charge. The other ones are connected to the bit lines BL _M-2 , BL _M-1 , BL _M , BL _{M + 1} , etc. used for writing and reading, respectively.

Here, for example, when a certain word line WL _N is selected, the potential of only that word line WL _N is “1” (high level).
And the other word lines WL _N-2 , WL _N-1 , WL _{N + 1} , etc. have a potential of "0".
(Low level), the switching transistor _{Tr (N, M)} whose gate is connected to the word line WL _N is turned on. Then, the information signal “1” is input to the capacitor C _{M (N, M)} connected to this.
Is stored, the charge stored in the capacitor C _{M (N, M)} is selected in the switching transistor T
_When connected via _{r (N, M)} , the data is output to the bit line BL _M , and reading or refreshing using a predetermined sense amplifier or the like is performed.

[Problems to be solved by the invention]

In the memory device that operates as described above, the holding time can be lengthened by increasing the amount of accumulated charge, and power consumption and load on the sense amplifier can be reduced.

However, if the capacitance C _M is increased to increase the amount of accumulated charges, the occupied area of the cell is increased, and high integration cannot be achieved.

On the other hand, in order to increase the charge amount, for example, there is also a method of increasing the information signal “1”, that is, the voltage V _H for accumulating charges. However, when the write voltage V _H is increased, reliability due to hot carriers generated in the drain depletion layer at the time of rewriting the information signal is reduced.

In general the switching transistor T gate-source voltage of _r V _GS and the source-drain current I _SD (logarithmic value)
The relationship is as shown in FIG. Therefore,
As shown in FIG. 4, the source-drain current I _SD increases exponentially as V _H in the reverse direction increases. This means that when the voltage V _H when accumulating charges is increased, Indicates that the leak current I _SD increases exponentially. Therefore, even if the write voltage V _H is simply increased, the retention time cannot be extended and the problem cannot be solved. .

In view of the above problems, the present invention provides a memory device that reduces the leak current between the source and the drain, realizes a longer holding time, and further prevents the deterioration of reliability due to hot carriers. To aim.

[Means for solving problems]

The present invention includes a capacitor for storing an information signal as an electric charge and a switching element which operates in response to a selection signal of a word line connected between the capacitor and a bit line, and a gate of the switching element is provided. It is characterized in that it comprises at least two or more gate sections for relaxing electric field concentration in the switching element, and the same selection signal of the word line is supplied as a gate control input of the two or more gate sections. The above-mentioned problems are solved by the memory device.

[Action]

In the memory device of the present invention, the gates of the switching elements forming the memory device are composed of at least two gate portions for relaxing electric field concentration in the switching elements, and each gate portion has the same gate control input as a gate control input. When a selection signal for the word line is supplied and a certain capacitance is selected by the selection signal, each gate portion of the switching element corresponding to the selected capacitance is turned on to write or write to the selected capacitance. Reading is performed. Therefore, even if the voltage applied to the gate remains unchanged as a whole, the voltage applied to each gate portion is distributed, so that the leak current can be effectively prevented.

In other words, the write voltage V _H can be increased by forming the gate with at least two gate portions, and the holding time can be extended and the sense can be increased by increasing the amount of charge accumulated in the capacitor. The load on the amplifier can be reduced, and the area occupied by the cells can be reduced due to the increase in the amount of charge, and high integration can be easily realized.

At this time, the voltage applied to each gate section is distributed, and the gate-source voltage V _{GS at} each gate section is distributed.
However, when the gate-source voltage V _GS is reduced in this way, the leakage current I _DS decreases exponentially as shown in FIG. The current will be significantly smaller.

In addition, the voltage applied to each gate portion can be distributed and reduced, so that the electric field concentration applied to the depletion layer can be mitigated, and therefore the generation of hot carriers can be prevented.

〔Example〕

A preferred embodiment of a memory device of the present invention will be described with reference to the drawings.

Memory device of this embodiment, the capacitor C _M for storing information signals as shown in FIG. 1 as a charge, a selection signal of the word line WL connected between the capacitive C _M and the bit lines BL Two gate sections G ₁ and G as switching elements that operate according to
A switching transistor T _r having ₂ is provided in one memory cell.

The capacitance C _M is for accumulating an information signal in the form of electric charges, one of the opposing electrodes is grounded, and the other is connected to one of the source electrode / drain electrode of the switching transistor T _r . The word line WL corresponds to one word line WL for each of the arranged memory cells.
When the selection signal is applied to the switching transistor Tr having the gate connected to the word line WL, the switching transistor _Tr is turned on. Bit line BL is connected to the other of the source and drain electrodes of the switching transistor T _r, which is used in reading and writing information signal of the capacitance C _M, the switching transistor T _r is turned on At this time, it conducts with the capacitance C _M. A sense amplifier or the like for sensing is connected to the bit line BL.

The switching transistor _{Tr that} is turned on by such a selection signal of the word line WL has two gate portions G ₁ and G ₂ respectively connected to the word line WL. The gate portions G ₁ and G ₂ are equivalently the gates of the two transistors, respectively. Then, for example, the information signal "1"
When writing is performed, for example, the potential of the bit line BL is set to the potential V _H , and the capacitance C _M and the switching transistor
When the potential of the connection point of the T _r to the potential V _L is the the switching transistor _{T r, | V H -V L} | but voltage is applied, the switching transistor T _r is 2 as described above One of has a gate portion G _1, G _2, Thus the voltages of the gate portion G _1, G ₂ are each divided into M _1, M _2, voltage applied, respectively compared with the case of the single gate Can be made smaller.

Therefore, even when the write voltage V _H is increased, the problem of hot carriers can be effectively prevented without any adverse effect such as leakage. Therefore, by increasing the amount of charge stored in the capacitor C _M , the holding time can be extended and the load on the sense amplifier can be reduced, and further, the area occupied by the cell can be reduced. As a result, high integration can be easily realized.

Further, at this time, the voltage applied to each gate portion is the voltage M ₁ , M
₂ to be divided, respectively, the value of the leakage current exponentially decreases considerably as shown in Figure 4. Therefore, the holding time can be surely lengthened, and the load on the sense amplifier or the like can be easily reduced.

Here, the switching transistor _Tr is, for example,
It is used as a switching transistor for memory cells in DRAMs formed using SOI (silicon-on-insulator) technology, and can significantly reduce leak current, especially in the SOI structure.

Next, FIG. 2 is an equivalent circuit of a memory cell of another embodiment of the memory device of the present invention, which is an example of a so-called folded bit linear memory device.

Similar to that shown in FIG. 3, word lines WL _N-2 , WL _N-1 , WL _N , WL _{N + 1} , to which selection signals are applied, and bit lines BL used for writing and reading. _M-2 , BL _M-1 , BL _M , BL _{M + 1} , etc. are arranged one for each memory cell, and each memory cell has two gate portions G ₁ of the above-described embodiment. , G ₂ and a switching transistor T _r and a capacitance C _M , respectively.

The two gate parts G ₁ , G of the switching transistor T _r
2 are connected to the same word line, for example, switching transistor T connected to word line WL _N ,
_{In r1 (N, M)} , the voltage applied to each of the gate sections G ₁ and G ₂ is divided into the voltages M ₁ and M ₂ , respectively, as described above, and therefore the value of the leakage current is exponentially large. It is possible to easily realize reduction of the holding time, increase of the holding time, reduction of load on the sense amplifier, prevention of generation of hot carriers, and the like. Moreover, such a circuit configuration may be based on an SOI structure.

Next, as still another embodiment of the present invention, the number of gate portions described above may be three or more. In such a case, it becomes possible to further reduce the leak current and prevent the generation of hot carriers, and thus to prolong the holding time and the chip area.

〔The invention's effect〕

As is clear from the above description, the gate of the switching element is made up of at least two gate portions for alleviating the electric field concentration in the switching element, and the selection signal of the same word line is used as the gate control input of each gate portion. Is supplied, the write voltage V _H can be increased, and the holding time can be extended and the load on the sense amplifier can be reduced by increasing the amount of charge accumulated in the capacitor. Since the amount of charge is increased, the area occupied by the cells can be reduced, and high integration can be easily realized.

Further, the leak current can be reduced from such a structure, and further, the leak current can be exponentially reduced, and the present invention can be particularly applied to the SOI structure to achieve a good result.

Further, it becomes possible to reduce the concentration of the electric field applied to the depletion layer, so that the generation of hot carriers can be effectively prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of the structure of a memory device of the present invention, FIG. 2 is a circuit diagram showing an example of applying the memory device of the present invention to a folded bit linear memory device, and FIG. 3 is a conventional memory. FIG. 4 is a circuit diagram showing an example of the device, and FIG. 4 is a characteristic diagram showing characteristics of the switching transistor. G ₁ , G ₂ …… Gate section T _r …… Switching transistor C _M …… Capacity WL …… Word line BL …… Bit line

Claims (1)

[Claims] 1. A capacitor for storing an information signal as a charge, and a switching element connected between the capacitor and a bit line and operating according to a selection signal of a word line, the gate of the switching element being The switching element is composed of at least two or more gate sections for relaxing electric field concentration, and the same word line selection signal is supplied as a gate control input of the two or more gate sections. Memory device.