JPH0784865A - Memory management device for electron beam exposure system - Google Patents

Abstract

PURPOSE:To provide the memory management device for the electron beam exposure which facilitates memory management and can stably transfer bit map data fast as to a memory management device for an electron beam exposure device which handles a large amount of bit map data of, for example, a blanking aperture array system. CONSTITUTION:The device has a transmission side equipped with (n) FIFO memories 3-1-3-n, a data transfer master 1, a bit map expansion part 7, an FIFO driving part 5 which divides the bit map data bdata into (n) blocks and stores them in the FIFO memories 3-1-3-n, an address signal generation part 13, and a wait time generation part 15 which specifies transfer intervals, and a reception part equipped with a data channel selection part which selects one of (n) data buses and receives data, a memory, and an address selection part which determines addresses in the memory space.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory management apparatus for an electron beam exposure apparatus, and more particularly to a memory management apparatus for an electron beam exposure apparatus which handles a large amount of bitmap data such as a blanking aperture array system. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory management device for an electron beam exposure apparatus that can easily manage memory and can transfer bitmap data at high speed and stably.

An electron beam exposure apparatus is an LSI or an ASIC.
In the manufacturing process of (Application Specific IC), L & S with a line width of 0.3 [μm] or less is drawn with high accuracy,
Although it is used as a lithography apparatus that can be realized with a positioning accuracy of 0.02 [μm] or less, it has been thought that it cannot be used for mass production of LSI until now because of its low throughput.

However, in recent years, the invention of the block exposure and blanking aperture array system has made it possible to use 1 [sec.
], A throughput of about 1 [cm ² ] can be expected. In particular, in the blanking aperture array method, it is necessary to decompose the conventional exposure data into a pattern by increasing the number of beams, store a large amount of bit data on the bitmap memory, and read the data, which enables high-speed data transfer, Further, there is a demand for a memory management device for an electron beam exposure apparatus having high reliability of data.

[0004]

2. Description of the Related Art In a conventional memory management device for an electron beam exposure apparatus, a storage area for large deflection data (main differential data) and small deflection data (sub differential data) in the case of a variable rectangular beam or block exposure system. Is defined as a "page" as a fixed amount of space, and the total amount of 1.7 [Gbit] memory is managed to manage exposure data equivalent to 256M-DRAM.

However, in the blanking aperture array system, data is held in units of grating apertures, and if the exposure unit is 0.08 [μm], the above 256
-DRAM chip size 20 × 20 [mm], 6
A memory of 2.5 to 125 [G bits] is required, and it is desired to develop a new method for managing and controlling the memory.

[0006]

As described above, when the conventional memory management device for an electron beam exposure apparatus is applied to a blanking aperture array type electron beam exposure apparatus, a large amount of exposure data is bit map expanded. However, there is a problem in that it takes a very long time to transfer the data.

The present invention solves the above problems,
For example, in a memory management device for an electron beam exposure apparatus that handles a large amount of bitmap data, such as a blanking aperture array method, an electron beam exposure apparatus that enables easy memory management and high-speed and stable data transfer of bitmap data. It is an object of the present invention to provide a memory management device for a computer.

[0008]

In order to solve the above problems, the memory management device for an electron beam exposure apparatus of the first feature of the present invention has n outputs (n is arbitrary) as shown in FIG. Positive integers) of the data buses D1BUS to DnBUS, and n FIFO (first-in first-out) memories 3-1 to 3-n, and the FIFO memory 3
Controls the input / output of -1 to 3-n, and selects the channel selection signal CS
A data transfer master 1 for outputting 1 to CSp (p is a minimum integer exceeding log ₂ n), and a bit map expansion unit 7 for expanding the exposure data DATA into bit map data bdata adapted to the aperture of the electron beam exposure apparatus. , The bitmap data bdata is divided into n blocks,
A FIFO drive unit 5 for storing in each of the n FIFO memories 3-1 to 3-n, and the FIFO memory 3-1.
Address signal generator 13 for generating transfer destination addresses A0-Ar of 3 to 3-n outputs and outputting them to address bus ABUS
And a waiting time generation unit 15 that specifies a transfer interval of the outputs of the FIFO memories 3-1 to 3-n.
And a data channel selection unit 21 for selecting one of the n data buses D1BUS to DnBUS to fetch data on the data bus based on the channel selection signals CS1 to CSp, and the data channel selection unit 21. The memory 25 for holding the data fetched by the memory 25 and the memory 25 based on the address on the address bus ABUS.
Address selection unit 2 that determines an address in the memory space of
3 and a receiving side 200 including the receiving side 200.

According to a second aspect of the present invention, there is provided a memory management apparatus for an electron beam exposure apparatus according to claim 1, wherein the number of the memory 25 is s (s). Is an arbitrary positive integer) bank memory 25
-1 to 25-s, and the address signal generator 13
Are memory bank selection signals BS1 to BSq designating transfer destination banks of the FIFO memories 3-1 to 3-n output.
(Q is a minimum integer exceeding log ₂ s), and the address selection unit 23 outputs the memory bank selection signals BS1 to BS1 based on the address on the address bus ABUS.
Determine the address of the bank memory specified by BSq.

According to a third aspect of the present invention, there is provided a memory management device for an electron beam exposure apparatus, wherein the memory management device for an electron beam exposure apparatus is the memory management device for an electron beam exposure apparatus. The memory management device uses the FI
In data transfer of FO memory 3-1 to 3-n output,
The addresses A0 to Ar and the FIFO memories 3-1 to 3-3-
The n output and the channel selection signals CS1 to CSp are synchronized with the data strobe signal DS that is output from the data transfer master 1 and that specifies the break of one data, and the latency signal specified by the latency generation unit 15 is used. wait
Based on the above, a waiting time is added in units of at least one of the outputs of the FIFO memories 3-1 to 3-n by an integer multiple of the system clock SYSCLK output from the data transfer master 1.

According to a fourth aspect of the present invention, there is provided a memory management apparatus for an electron beam exposure apparatus according to claim 2 or 3, wherein the memory management apparatus for an electron beam exposure apparatus is as described above. The receiving side 200 includes s receiving side boards 200-j including the data channel selecting section 21, the address selecting section 23, and one of the bank memories 25-j (j = 1 to s). Then, the waiting time generation unit 15 specifies the delay of the rising and falling time of the signal due to the drive load which differs depending on the number (s) of the receiving side boards 200-j, which the waiting time generation unit 15 specifies. Change the setting with wait.

Further, a memory management device for an electron beam exposure apparatus according to a fifth feature of the present invention is the memory management device for an electron beam exposure apparatus according to claim 1, 2, 3 or 4. Book data bus D1BUS to DnBUS
And the number of n FIFO memories 3-1 to 3-n (n)
Is the memory 25 or one bank memory 25-j
(J = 1 to s) corresponds to the number of pages in the page memory space.

[0013]

In the memory management device for the electron beam exposure apparatus having the first, second, third and fifth characteristics of the present invention, the bit map data output from the bit map developing section 7 as shown in FIG. After bdata is temporarily stored in the register 11, it is divided into n blocks and stored in the FIFO memories 3-1 to 3-n under the control of the FIFO drive unit 5. The data transfer master 1 stores a series of bitmap data in the FIFO.
When the data is held in the memories 3-1 to 3-n, the data transfer to the receiving side is started. The data transfer is performed in synchronization with the system clock SYSCLK, and the address signal generator 13 outputs the address signals A0 to Ar and the memory bank selection signals BS1 to BSq, and the data transfer master 1
Is the data bus D from each FIFO memory 3-1 to 3-n.
Data strobe signal DS # from 1BUS to DnBUS
Data is sent sequentially at data intervals separated by. At this time, the waiting time generation unit 15 requests the data transfer master 1 to add an arbitrary waiting time (waiting time signal wa
it), a value that is a multiple of the system clock SYSCLK is added to each data interval.

On the other hand, on the receiving side, the data channel selection unit 21 synchronizes with the system clock SYSCLK and, when the data strobe signal DS # is active, based on the channel selection signals CS1 to CSp, the data bus DiB.
US (i = 1 to n) is selected, the data signals Di0 to Dim are received from the data bus, and the address selection unit 23 selects a bank memory based on the memory bank selection signals BS1 to BSq. , Memory access is performed.

As a result, for example, even when the electron beam apparatus has a large amount of bit map data as in the blanking aperture array method, the memory 25 having a bank structure having a very large memory space is constructed on the receiving side. Of the FIFO memories 3-1 to 3-n corresponding to the number of pages in the page memory space and the data bus D.
1BUS to DnBUS and a memory bank selection signal BS1
.About.BSq and the address bus ABUS manage the memory space, and the bitmap data is divided into n blocks to transfer n blocks, thereby enabling high-speed transfer of bitmap data. .

Further, in the memory management device for the electron beam exposure apparatus of the fourth and fifth features of the present invention, for example, the electron beam apparatus is configured as a block by the configuration (n = 4, m = 63) shown in FIG. Even when a large amount of bitmap data is stored as in the ranking aperture array method, the memory 25 having a bank configuration having a very large memory space is prepared by the number of banks (s) of the receiving side substrate 200-j. And the number of FIFO memories 3-1 to 3-4 corresponding to the number of pages in the page memory space and the data bus D.
1BUS to D4BUS and memory bank selection signal BS1
.About.BSq and the address bus ABUS manage the memory space, and high-speed data transfer is made possible by four block transfers (64-bit data transfer).

Further, in the waiting time generating section 15, the delay of the rising and falling times of the signal due to the drive load, which varies depending on the number (s) of the receiving side boards 200-j,
The waiting time signal wait specified by the waiting time generation unit 15 adjusts the waiting time by adding a waiting time in the minimum unit of transfer of the bitmap data in increments of the system clock SYSCLK. Transfer is possible.

[0018]

Embodiments of the present invention will now be described with reference to the drawings. First Embodiment FIGS. 1 and 2 are block diagrams of a memory management device for an electron beam exposure apparatus according to a first embodiment of the present invention. The memory management device for an electron beam exposure apparatus of this embodiment is roughly divided into a transmission side and a reception side. FIG. 1 shows the configuration of the transmission side, and FIG. 2 shows the configuration of the reception side. Further, it is assumed that the data obtained by expanding the exposure data into a bitmap is divided into n blocks (1 block is m + 1 bit block data). Note that n and m are arbitrary positive integers. In particular, n may be the number corresponding to the number of pages in the page memory space of the memory 25, and m
+1 is the number obtained by dividing the bit length of the bitmap data by n.

The signal connecting the transmitting side and the receiving side includes
System clock SYSCLK, memory bank selection signals BS1 to BSq designating the bank number of the memory on the receiving side
(Q is the smallest integer exceeding log ₂ s; s is the number of banks), channel selection signal C that specifies a valid data bus
S1 to CSp (p is the smallest integer exceeding log ₂ n),
Address bus ABU for transferring address signals A0-Ar
S, data signals Di0 to Dim (i = 1 to n), respectively
Data buses D1BUS to DnBUS for transferring data
An address strobe signal AS # indicating that the address signals A0 to Ar on the address bus ABUS are valid, and a data strobe signal DS # indicating that the data signals Di0 to Dim on the data buses D1BUS to DnBUS are valid. There is. Here, in the signal name,
A signal with the symbol # added to the end of the signal name indicates that the signal is a negative logic signal.

In FIG. 1, the transmitting side includes a data transfer master 1, FIFO memories 3-1 to 3-n, a FIFO driving section 5, a bit map expanding section 7, a register 11, an address signal generating section 13, and a waiting time generation. It is configured to include the section 15.

The FIFO memories 3-1 to 3-n have m + 1
It is configured by including n (3-1 to 3-n) bit-width memories, and the input / output control of the memories is performed by a FIFO (First-In F
irst-Out) control. Further, the outputs of the FIFO memories 3-1, ..., 3-n are respectively connected to the data signal D1.
0 to D1m, ..., Dn0 to Dnm are formed.

The data transfer master 1 generates a system clock SYSCLK, channel selection signals CS1 to CSp, an address strobe signal AS #, and a data strobe signal DS #. In addition, the FIFO memory 3-1 to 3-
n and the control signals c31 to c3 for the FIFO driver 5.
n and c5 are issued to prompt reading of data from the FIFO memories 3-1 to 3-n.

The bit map developing section 7 matches the exposure data DATA (for example, the data such as the starting point and the size in the exposure in the opcode format) from the host with the aperture of the blanking aperture array type electron beam exposure apparatus. It is expanded to bitmap data bdata.

The FIFO drive unit 5 stores the bitmap data bdata generated by the bitmap expansion unit 7 in the register 11, and under the control of the control signals f31 to f3n,
Register 11 output to FIFO memory 3-1 to 3-n,
Write data by dividing it into n blocks.

The address signal generator 13 defines a memory space, and memory bank selection signals BS1 to BSq.
And issue address signals A0-Ar. The waiting time generation unit 15 defines the data transfer interval and sets the waiting time signal w
The data transfer master 1 is notified by ait.

In FIG. 2, the receiving side has a data channel selecting section 21, an address selecting section 23, and a memory 25.
It is configured with. The memory 25 has a bank configuration and is composed of s bank memories (first bank 25-1 to s-th bank 25-s).

The data channel selection unit 21 includes a system clock SYSCLK and channel selection signals CS1 to CS.
p, the data signal groups Di0 to Dim (i = 1 to n), and the data strobe signal DS # are received and the corresponding data is read. That is, the channel selection signals CS1 to CS
The data bus DiBUS designated by p is selected to read the data signals Di0 to Dim on the data bus DiBUS.

The address selection unit 23 includes a system clock SYSCLK, memory bank selection signals BS1 to BSq,
The memory bank selection signals BS1 to BS are received by receiving the address signals A0 to Ar and the address strobe signal AS #.
A bank designated by q is selected and the bank memory 25
The internal address (iab) is supplied to -1 to 25-s.

Next, the operation of this embodiment will be described with reference to the timing chart shown in FIG. FIG. 3 is a timing chart for explaining the operation of the memory management device for the electron beam exposure apparatus of this embodiment.

In this embodiment, the bit map data bdata output from the bit map expansion unit 7 is stored in the register 1
1 is temporarily stored, and under the control of the FIFO drive unit 5, it is divided into n blocks and stored in the FIFO memories 3-1 to 3-n. When this is completed, new bitmap data b
It requests the bitmap expansion unit 7 to issue data, and repeats the same operation as described above until the data in the bitmap expansion unit 7 becomes empty.

The outputs of the FIFO memories 3-1, ..., 3-n are data signals D10-D1m ,.
It supports Dnm, and the data transfer master 1 has FI
The state of the FO drive unit 5 is monitored, and when a series of bitmap data is held in the FIFO memories 3-1 to 3-n,
Start data transfer to the receiver.

All data transfer is performed by the system clock SY.
It is performed in synchronization with SCLK. The data transfer master 1
The address signal generation unit 13 is requested to issue an address (control signal c13), and the address signal generation unit 13 receives this and outputs valid address signals A0 to Ar and memory bank selection signals BS1 to BSq.

In synchronization with this, the data transfer master 1 activates the address strobe signal AS #,
Further, from each FIFO memory 3-1 to 3-n to the data bus D
Data strobe signal DS # from 1BUS to DnBUS
Data is sent sequentially at data intervals separated by.

At this time, the waiting time generation section 15 requests the data transfer master 1 to add an arbitrary waiting time (waiting time signal wait), and the system clock SYSC
A value that is a multiple of LK is added to each data interval.

On the receiving side, the data channel selection unit 21
Is a single data bus DiB based on the channel selection signals CS1 to CSp when the data strobe signal DS # is active in synchronization with the system clock SYSCLK.
US (i = 1 to n) is selected, the data signals Di0 to Dim are received from the data bus and are supplied to the memory 25. In addition, the address selection unit 23 selects a bank based on the memory bank selection signals BS1 to BSq and stores the internal address (iab) in the bank memory 25-1 to 25-s.
To supply.

As described above, in the memory management device for the electron beam exposure apparatus according to the present embodiment, even when the electron beam apparatus has a large amount of data as the bitmap data as in the blanking aperture array system. , A memory 25 having a bank structure having a very wide memory space is constructed on the reception side, and, for example, FIFO memories 3-1 to 3-n corresponding to the number of pages in the page memory space and data buses D1BUS to DnBUS are provided. , The memory bank selection signals BS1 to BSq and the address bus ABUS manage the memory space, and n block transfers (m + 1 bit data transfer) enable high-speed data transfer of bitmap data. Second Embodiment FIG. 4 shows a block diagram of a memory management device for an electron beam exposure apparatus according to a second embodiment of the present invention. The memory management device for the electron beam exposure apparatus of this embodiment divides data into four blocks and transfers the data. In the first embodiment, n is used.
= 4 and m = 63.

In FIG. 4, the memory management device for the electron beam exposure apparatus of this embodiment is composed of a transmitting side substrate 100 and a receiving side substrate 200-j (j = 1 to s; s is the number of banks). .

Transmitting side substrate 100 and receiving side substrate 200-
The signal connecting between j is (for example, 50 [MHz]
System clock SYSCLK, memory bank selection signals BS1 to BSq (q is a minimum integer exceeding log ₂ s; s is the number of banks, and in this embodiment, the number of receiving side boards 200-j prepared), channels Selection signal CS1,
CS2, address bus ABUS for transferring address signals A0 to A22, error correction code (ECC; Error)
Data signals Di0 to Di63 with Correcting Code)
Four data buses D1BUS for transferring (i = 1 to 4)
To D4BUS, address strobe signal AS # indicating that the address signals A0 to A22 on the address bus ABUS are valid, and data buses D1BUS to D4B
There is a data strobe signal DS # which indicates that the data signals Di0 to Dim + ECC on the US are valid.

These signal groups are arranged on the back panel using, for example, connectors. In FIG. 4, on the transmitting side substrate 100, the data transfer master 1, the FIFO memories 3-1 to 3-4, the FIFO driving unit 5, the bit map expanding unit 7, the register 11, the address signal generating unit 13, and the waiting time. The generating unit 15 is provided.

The FIFO memories 3-1 to 3-4 are 64+.
The FIFO memory 3 includes four (3-1 to 3-4) memories each having an (ECC bit; eg, 4) bit width.
Outputs of -1, ..., 3-4 are data signals D10, respectively.
-D163 + ECC, ..., Dn0-D463 + ECC are formed.

The data transfer master 1 generates a system clock SYSCLK, channel selection signals CS1 and CS2, an address strobe signal AS #, and a data strobe signal DS #. In addition, the FIFO memory 3-1 to 3-
4 and the FIFO driver 5 to the control signals c31 to c3.
4 and c5 to prompt reading of data from the FIFO memories 3-1 to 3-4.

The bit map expansion section 7 expands the exposure data DATA from the host into bit map data bdata that matches the aperture of the blanking aperture array type electron beam exposure apparatus, and at the same time outputs an error correction code ECC for each byte. Add.

The FIFO drive unit 5 stores the bitmap data bdata generated by the bitmap expansion unit 7 in the register 11, and under the control of the control signals f31 to f34,
Register 11 output to FIFO memory 3-1 to 3-4,
The data is distributed to the block data of 64 + ECC bits and written.

The address signal generator 13 defines a memory space, and memory bank selection signals BS1 to BS4.
And issue address signals A0 to A22. The waiting time generation unit 15 defines the data transfer interval and notifies the data transfer master 1 by a waiting time signal wait.

The data transfer master 1, the FIFO driving unit 5, the bit map expanding unit 7, the register 11, the address signal generating unit 13, and the waiting time generating unit 15 are highly integrated by using an ASIC, an FPGA or the like. It can be easily configured.

On the receiving side substrate 200-j, a data channel selecting unit 21, an address selecting unit 23, and a memory 25-j are provided. The data channel selection unit 21 includes a system clock SYSCLK, channel selection signals CS1 and CS2, and data signal groups Di0 to Di63.
(I = 1 to 4) and the data strobe signal DS # are received and the corresponding data is read.

The address selection unit 23 includes a system clock SYSCLK, memory bank selection signals BS1 to BS4,
Upon receiving the address signals A0 to A22 and the address strobe signal AS #, the corresponding address is selected.

The receiving side substrate 200 having such a structure
A required memory space can be constructed by preparing j in an arbitrary number. With the above configuration, in the memory management device for the electron beam exposure apparatus of the present embodiment, even if the electron beam apparatus has a large amount of data as bitmap data as in the blanking aperture array system, The memory 25 having a bank configuration having a wide memory space is constructed by preparing the receiving side substrates 200-j by the number of banks (s), and the number of FIFO memories 3-1 corresponding to the number of pages in the page memory space. To 3-4, the data buses D1BUS to D4BUS, the memory bank selection signals BS1 to BSq, and the address bus ABUS to manage the memory space, and four block transfers (64-bit data transfer) to achieve high speed. Data transfer is possible.

Further, the receiving side substrate 20 constructed on the receiving side
It is possible to adjust the delay of the rise and fall time of the signal due to the drive load that varies depending on the number of boards of 0 by adding a waiting time in the minimum unit of the bit map data transfer by an integer multiple of the system clock SYSCLK. It enables stable data transfer of bitmap data.

[0050]

As described above, according to the present invention,
Even if the electron beam device has a large amount of bit map data as in the blanking aperture array method, a bank structure memory with a very large memory space is built on the receiving side to reduce the number of pages in the page memory space. The memory space is managed by a corresponding number (n) of FIFO memories, a data bus, a memory bank selection signal, and an address bus, and bitmap data is divided into n blocks to transfer n blocks. Therefore, it is possible to provide a memory management device for an electron beam exposure apparatus capable of high-speed data transfer of bitmap data.

Further, according to the present invention, a memory having a bank structure having an extremely wide memory space is constructed by preparing the number of the receiving side substrates by the number of banks (s), and corresponding to the number of pages in the page memory space. Since the memory space is managed by the number (n) of FIFO memories, the data bus, the memory bank selection signal, and the address bus, and n blocks are transferred, high-speed data transfer is possible. In addition, the waiting time generation unit delays the rise and fall time of the signal due to the drive load, which varies depending on the number (s) of the receiving side boards, by the waiting time specified by the waiting time generation unit. It can be adjusted by adding a waiting time at the minimum unit of bitmap data transfer in increments of an integer, and a stable bitmap data It is possible to provide a memory management apparatus for electron beam exposure apparatus capable of data transfer.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a transmission side of a memory management device for an electron beam exposure apparatus according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a configuration on a receiving side of a memory management device for an electron beam exposure apparatus according to a first embodiment of the present invention.

FIG. 3 is a timing chart illustrating an operation of the memory management device for the electron beam exposure apparatus according to the first embodiment.

FIG. 4 is a configuration diagram of a memory management device for an electron beam exposure apparatus according to a second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Data transfer master 3-1 to 3-n ... FIFO memory 5 ... FIFO drive section 7 ... Bit map expansion section 11 ... Register 13 ... Address signal generation section 15 ... Wait time generation section 21 ... Data channel selection section 23 ... Address Selector 25-1 to 25-s ... Bank memory (first bank to s-th)
Bank) 100 ... Transmitting side substrate 200-j (j = 1 to s) ... Receiving side substrate SYSCLK ... System clock BS1 to BSq ... Memory bank selection signal CS1 to CSp ... Channel selection signal A0 to Ar ... Address signal ABUS ... Address bus Di0 to Dim (i = 1 to n) ... Data signal D1BUS to DnBUS ... Data bus AS # ... Address strobe signal DS # ... Data strobe signal DATA ... Exposure data bdata ... Bitmap data b5 ... Control signals c31 to c3n, c5. c13 ... Control signal f1, f31 to f3n, f7, f11 ... Control signal a1 ... Control signal wait ... Wait time (signal) idb ... Internal data (bus) iab ... Internal address (bus)

Claims (5)

[Claims] 1. An n number of FIFO memories (3-1 to 3-n) connected to data buses (D1BUS to DnBUS) of which n outputs (n is an arbitrary positive integer), said FIFO memory (3). -1 to 3-n) is controlled, and channel selection signals (CS1 to CSp; p is log ₂
A data transfer master (1) that outputs a minimum integer exceeding n), and a bitmap expansion unit (7) that expands the exposure data (DATA) into bitmap data (bdata) that matches the aperture of the electron beam exposure apparatus. , The bitmap data (bdata) is divided into n blocks, and each of the n FIFO memories (3-1) is divided into n blocks.
To 3-n), and a transfer destination address (A0-Ar) of the output of the FIFO memory (3-1 to 3-n) and an address bus (ABU).
A transmission side (100) including an address signal generating section (13) for outputting to S) and a waiting time generating section (15) for designating a transfer interval of the outputs of the FIFO memories (3-1 to 3-n); One of the n data buses (D1BUS to DnBUS) based on the channel selection signals (CS1 to CSp)
A data channel selection unit (21) for selecting a book and loading the data on the data bus, a memory (25) for holding the data loaded by the data channel selection unit (21), and the address bus (ABUS) Based on the address above
Receiving side (200) provided with an address selecting section (23) for determining an address in the memory space of the memory (25)
And a memory management apparatus for an electron beam exposure apparatus. 2. The memory (25) includes s (s is an arbitrary positive integer) bank memories (25-1 to 25-s), and the address signal generator (13) includes the FIFO memory. Memory bank selection signals (BS1 to BSq; q is log ₂ s) designating a transfer destination bank of (3-1 to 3-n) output.
Is output to the address selection unit (23), and the address selection unit (23) outputs the address bus (A
2. The memory management device for an electron beam exposure apparatus according to claim 1, wherein the address of the bank memory designated by the memory bank selection signals (BS1 to BSq) is determined based on the address on the BUS). 3. The memory management device for the electron beam exposure apparatus, in the data transfer of the output of the FIFO memory (3-1 to 3-n), the address (A0 to Ar) and the FIFO memory (3-1).
~ 3-n) output and channel selection signals (CS1 to CS
p) is output from the data transfer master (1),
The waiting time (wa) specified by the waiting time generation unit (15) is synchronized with the data strobe signal (DS) that specifies one data break.
It), a waiting time is added in increments of at least one of the output of the FIFO memory (3-1 to 3-n) by an integer multiple of the system clock (SYSCLK) output by the data transfer master (1). The memory management device for an electron beam exposure apparatus according to claim 1 or 2. 4. The receiving side (200) includes the data channel selection unit (21) and the address selection unit (23).
And s number of receiving side boards (200-j) provided with one of the bank memories (25-j; j = 1 to s), and the waiting time generation section (15) includes the receiving side board (20).
0-j) The waiting time (wai) specified by the waiting time generation unit (15) for the delay in the rise and fall times of the signal due to the drive load, which varies depending on the number of drives (s).
4. The memory management device for an electron beam exposure apparatus according to claim 2, wherein the setting is changed according to t). 5. The n data buses (D1BUS to D).
nBUS) and n FIFO memories (3-1 to 3−)
The number (n) of n) corresponds to the number of pages in the page memory space of the memory (25) or one bank memory (25-j; j = 1 to s). 2. The memory management device for the electron beam exposure apparatus according to 2, 3, or 4.