JPH0783584B2 - Phase detector - Google Patents
Phase detectorInfo
- Publication number
- JPH0783584B2 JPH0783584B2 JP63300309A JP30030988A JPH0783584B2 JP H0783584 B2 JPH0783584 B2 JP H0783584B2 JP 63300309 A JP63300309 A JP 63300309A JP 30030988 A JP30030988 A JP 30030988A JP H0783584 B2 JPH0783584 B2 JP H0783584B2
- Authority
- JP
- Japan
- Prior art keywords
- phase
- signal
- phase difference
- alternating current
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Measuring Phase Differences (AREA)
- Power Conversion In General (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、多相交流信号の周波数変化や位相変化に対
して速い応答で追従する位相検出器に関するものであ
る。Description: TECHNICAL FIELD The present invention relates to a phase detector that follows a frequency change or a phase change of a polyphase AC signal with a quick response.
第３図は例えば特公昭60−37711号公報に示された従来
の位相検出器の原理図を示すものであり、具体的にはサ
イリスタ位相制御電力変換器装置等に適用されるもので
ある。図において、１は位相差Δθ（位相差信号）に比
例した信号E0Δθが出力される位相比較器、２は位相比
較器１が出力する位相差信号Δθに比例した信号E0Δθ
を増幅し、信号V1を出力する制御増幅器、３は前記制御
増幅器２の出力により、出力パルス周波数が制御される
電圧−周波数変換器、４は前記周波数変換器の出力パル
スを計数するカウンタ、５は90゜位相の異なった２相正
弦波データが書き込まれたリードオンリメモリ（ROM）
で、カウンタ４の計数値θ１に応じた直交２相正弦波e1
d,e1qがリードオンリメモリ５とディジタル−アナログ
変換器6,7より得られる。11は、一般に良く使用される
３相信号eR,eS,eTより直交した２相正弦波e0d,e0qを演
算する３相−２相変換器である。FIG. 3 shows a principle diagram of a conventional phase detector disclosed in, for example, Japanese Patent Publication No. Sho 60-37711, and specifically, it is applied to a thyristor phase control power converter device and the like. In the figure, 1 is a phase comparator that outputs a signal E 0 Δθ proportional to the phase difference Δθ (phase difference signal), and 2 is a signal E 0 Δθ that is proportional to the phase difference signal Δθ output from the phase comparator 1.
Amplifying the control amplifier that outputs a signal V 1, 3 is the output of the control amplifier 2, the voltage output pulse frequency is controlled - the frequency converter, the 4 counts the output pulse of the frequency converter counter, 5 is a read-only memory (ROM) in which two-phase sine wave data with different 90 ° phases are written.
Then, the quadrature two-phase sine wave e 1 according to the count value θ 1 of the counter 4
d, e 1 q are obtained from the read-only memory 5 and the digital-analog converters 6,7. Reference numeral 11 is a three-phase to two-phase converter that calculates orthogonal two-phase sine waves e 0 d and e 0 q from commonly used three-phase signals e R , e S , and e T.
次に動作について説明する。まず、３相−２相変換器11
に供給される３相信号eR,eS,eTを とする。Next, the operation will be described. First, 3 phase-2 phase converter 11
The three-phase signals e R , e S , e T supplied to And
この３相信号に対して、該、３相−２相変換器11におい
て次の相変換を行い、直交した２相信号を得る。The three-phase signal is subjected to the following phase conversion in the three-phase to two-phase converter 11 to obtain orthogonal two-phase signals.
また、リードオンリメモリ５には、予め次の単位振幅の
直交した２相正弦波データが書き込まれている。 In the read-only memory 5, the following two-phase sine wave data having orthogonal unit amplitudes are written in advance.
これら２組の２相信号e0d,e0q及びe1d,e1qの位相差Δθ
＝（θ０−θ１）を求める。 The phase difference Δθ between these two sets of two-phase signals e 0 d, e 0 q and e 1 d, e 1 q
= (Θ 0 −θ 1 ).
E0sin（θ０−θ１）＝E0sinθ０・cosθ１−E0cosθ０
・sinθ１……（４） （４）式より、 ここで、（５）式は、次の如く近似することができる。
すなわち、 （Ａ）.sinΔθ≒Δθ （Ｂ）．入力交流信号の振幅は、ほぼ一定であり、E0は
定数として見なせる。E 0 sin (θ 0 −θ 1 ) = E 0 sin θ 0 · cos θ 1 −E 0 cos θ 0
・ Sin θ 1 (4) From the equation (4), Here, the equation (5) can be approximated as follows.
That is, (A) .sin Δθ≈Δθ (B). The amplitude of the input AC signal is almost constant, and E 0 can be regarded as a constant.
従って、位相差Δθは となる。そこで、位相比較器１が（６）式のカッコ内を
演算することにより、位相差信号Δθに比例した信号E0
Δθを求めたのち、制御増幅器２が位相差信号Δθに比
例した信号E0Δθを増幅することにより、信号V1を演算
し出力する。この制御増幅器２の出力により、電圧−周
波数変換器３の出力パルス周波数が制御され、この出力
パルスがカウンタ４にて計数される。たとえば、位相差
信号が大きな時は、制御増幅器２が電圧−周波数変換器
３の出力パルス周波数を上昇するよう動作し、位相差Δ
θは減少する。Therefore, the phase difference Δθ is Becomes Therefore, the phase comparator 1 calculates the inside of the parentheses in the equation (6) to obtain a signal E 0 proportional to the phase difference signal Δθ.
After obtaining Δθ, the control amplifier 2 amplifies the signal E 0 Δθ proportional to the phase difference signal Δθ to calculate and output the signal V 1 . The output pulse frequency of the voltage-frequency converter 3 is controlled by the output of the control amplifier 2, and the output pulse is counted by the counter 4. For example, when the phase difference signal is large, the control amplifier 2 operates so as to increase the output pulse frequency of the voltage-frequency converter 3, and the phase difference Δ
θ decreases.
このように、位相差Δθが小さくなるように単位振幅の
２相正弦波e1dとe1qの位相差θ１を制御して、入力信号
の位相θ０に追従したディジタルの位相信号θ１が得ら
れる。In this way, the phase difference θ 1 between the two-phase sine waves e 1 d and e 1 q of unit amplitude is controlled so that the phase difference Δθ becomes smaller, and the digital phase signal θ that follows the phase θ 0 of the input signal 1 is obtained.
従来の位相検出器は以上のように構成されているので、
通常、多相交流としてよく使用される、90゜の位相差が
ない３相あるいは６相の交流に対しては、これら多相交
流信号から90゜位相の異なった２相正弦波信号を生成し
なければならず、多相−２相変換器が不可欠であるとい
う課題があった。Since the conventional phase detector is configured as described above,
Normally, for three-phase or six-phase alternating current, which is often used as multi-phase alternating current and has no 90 ° phase difference, two-phase sinusoidal signals with different 90 ° phases are generated from these multi-phase alternating current signals. There is a problem that a polyphase-to-two-phase converter is indispensable.
この発明は上記のような課題を解消するためになされた
もので、入力の多相交流信号より90゜位相の異なった２
相正弦波信号に変換せずに、多相交流信号をそのまま入
力信号として、この入力信号の周波数変化と位相変化と
に対して速やかに追従可能な位相検出器をハードウェア
量の増加を抑えて得ることを目的とする。The present invention has been made in order to solve the above problems, and has a phase difference of 90 ° from the input polyphase AC signal.
A phase detector that can quickly follow a frequency change and a phase change of this input signal without converting it to a phase sine wave signal, using the polyphase AC signal as the input signal without increasing the amount of hardware. The purpose is to get.
この発明に係る位相検出器は、多相交流信号における任
意の２相交流信号間の位相差を設定する位相設定器を設
けることにより、その設定された位相差だけ位相が異な
る２つの交流信号を発生させ、その２つの交流信号と前
記任意の２相交流信号に基づいて位相差信号を演算する
ようにしたものである。The phase detector according to the present invention is provided with a phase setting device for setting a phase difference between arbitrary two-phase alternating current signals in a multi-phase alternating current signal, so that two alternating current signals different in phase by the set phase difference can be detected. The phase difference signal is generated based on the two generated AC signals and the arbitrary two-phase AC signal.
この発明における位相検出器は多相交流信号のうち任意
の２相信号を変換せずに第１の２相交流入力信号として
第１の２相交流入力信号の位相と検出器出力位相との位
相差を、第１及び第２の交流信号発生器が発生する第２
の２相交流入力信号を用いて、小さくするように制御す
る。The phase detector according to the present invention does not convert any two-phase signal of the multi-phase alternating current signal and converts the phase of the first two-phase alternating current input signal and the detector output phase as the first two-phase alternating current input signal. The phase difference is generated by the second AC signal generator generated by the second AC signal generator.
The two-phase AC input signal of is used to control so as to make it smaller.
以下、この発明の一実施例を図について説明する。図中
第３図と同一の部分は同一の符号をもつて図示した第１
図及び第２図において、12は多相交流信号における任意
の２相交流信号間の位相差αがディジタル値で設定され
たα設定器（位相設定器）、13はカウンタ４の計数値θ
１からα設定器12に設定された位相差αを減算する減算
器、5aはカウンタ４の計数値θ１に応じた交流信号e1R
を発生するリードオンリメモリ（第１の交流信号発生
器）、5bは減算器13の減算結果θ１−αに応じた交流信
号e1Sを発生するリードオンリメモリ（第２の交流信号
発生器）、８は任意の２相交流信号のうち位相の進んだ
交流信号eRとリードオンリメモリ5bが発生する交流信号
e1Sとを乗算してディジタル・アナログ変換するディジ
タル−アナログ変換器（第１の乗算器）、８は任意の２
相交流信号のうち位相の遅れた交流信号eSとリードオン
リメモリ９が発生する交流信号e1Rとを乗算してディジ
タル・アナログ変換するディジタル−アナログ変換器
（第２の乗算器）、10はディジタル−アナログ変換器９
の出力からディジタル−アナログ変換器10の出力を減算
し、位相差信号Δθに比例した信号sinα・E0・Δθを
出力する減算器である。An embodiment of the present invention will be described below with reference to the drawings. In the figure, the same parts as those in FIG.
In FIG. 2 and FIG. 2, 12 is an α setter (phase setter) in which the phase difference α between arbitrary two-phase AC signals in the polyphase AC signal is set by a digital value, and 13 is the count value θ of the counter 4.
1 is a subtracter for subtracting the phase difference α set in the α setter 12, 5a is an AC signal e 1R corresponding to the count value θ 1 of the counter 4
Is a read-only memory (first AC signal generator), 5b is a read-only memory (second AC signal generator) that generates an AC signal e 1S according to the subtraction result θ 1 -α of the subtractor 13. , 8 are AC signals e R with advanced phase among arbitrary two-phase AC signals and AC signals generated by the read-only memory 5b
A digital-analog converter (first multiplier) that multiplies e 1S and performs digital-analog conversion, and 8 is an arbitrary 2
A digital-analog converter (second multiplier) for performing digital-analog conversion by multiplying an AC signal e S delayed in phase among the phase AC signals and an AC signal e 1R generated by the read-only memory 9, Digital-analog converter 9
Is a subtracter that subtracts the output of the digital-analog converter 10 from the output of and outputs a signal sin α · E 0 · Δθ proportional to the phase difference signal Δθ.
次に第１図及び第２図を参照しながら動作について説明
する。まず、第１図に示す原理図にもとづいて概略説明
をする。多相信号のなかの、例えばeR,eS（第１の２相
交流入力信号）を用いて互いの位相を検出している。そ
こで、前記、第１の２相交流入力信号eR,esは（７）式
で表わすことができる。Next, the operation will be described with reference to FIGS. 1 and 2. First, a schematic description will be given based on the principle diagram shown in FIG. Mutual phases are detected using, for example, e R and e S (first two-phase AC input signals) among the multi-phase signals. Therefore, the first two-phase AC input signals e R , e s can be expressed by equation (7).
但し、αはeRとeSの位相差である。 However, α is the phase difference between e R and e S.
また、リードオンリメモリ５には、交流入力信号の２相
に対応した、次の単位振幅の正弦波データが予め書き込
まれている。e1R,e1Sを第２の２相交流入力信号とする
とe1R,e1Sは そこで、これら２組の第１、第２の２相交流入力信号の
位相差Δθ＝（θ０−θ１）を求める。Further, in the read-only memory 5, sine wave data of the following unit amplitude corresponding to the two phases of the AC input signal is written in advance. If e 1R , e 1S is the second two-phase AC input signal, e 1R , e 1S becomes Therefore, the phase difference Δθ = (θ 0 −θ 1 ) between these two sets of first and second two-phase AC input signals is obtained.
eR・e1S−eS・e1R＝E0cosθ０・cos（θ１−α） −E0cos（θ０−α）・cosθ１ ＝−sinα・E0｛sinθ０・cosθ１ −sinθ１・cosθ０｝ ＝−sinα・E0・sin（θ０−θ１） ……（９） （９）式より、 （10）式において、従来例と同様に次の近似を用いる。e R · e 1S −e S · e 1R = E 0 cos θ 0 · cos (θ 1 −α) −E 0 cos (θ 0 −α) · cos θ 1 = −sin α · E 0 {sin θ 0 · cos θ 1 − sin θ 1 · cos θ 0 } = − sin α · E 0 · sin (θ 0 −θ 1 ) (9) From the equation (9), In equation (10), the following approximation is used as in the conventional example.
（Ａ）.sinΔθ≒Δθと見なせる。(A) .sin Δθ can be regarded as Δθ.
（Ｂ）．入力交流信号の振幅は、ほぼ一定であり、E0は
定数と見なせる。また、選択された２相の相間位相差は
一定とする。(B). The amplitude of the input AC signal is almost constant, and E 0 can be regarded as a constant. In addition, the phase difference between the two selected phases is constant.
よって、sinαも一定値である。Therefore, sin α is also a constant value.
従って、位相差Δθは となり、信号eR・eS・e1R・e1Sより位相差Δθが連続的
に得られる。Therefore, the phase difference Δθ is Therefore, the phase difference Δθ is continuously obtained from the signals e R , e S , e 1R , e 1S .
但し、sinα≠０でなければならないのでα≠180゜とす
る。However, since sin α ≠ 0, α ≠ 180 °.
位相差Δθを検出してからの動作は、従来例と同様なの
で、説明を省略する。Since the operation after detecting the phase difference Δθ is the same as that of the conventional example, the description is omitted.
次に、第２図のブロック図にもとづいて動作について説
明する。Next, the operation will be described based on the block diagram of FIG.
eRとe1S、eSとe1Rを入力として乗算機能を持つディジタ
ル−アナログ変換器8,9と減算器10により、前記（11）
式のカッコ内の演算が行われ、位相差信号Δθに比例し
た信号sinα・E0・Δθが演算される。そして、位相差
信号Δθに比例した信号sinα・E0・Δθは、制御増幅
器２により増幅され、信号V1が演算される。そして、信
号V1は電圧−周波数変換器３により入力され、その信号
V1に対応する周波数が発生される。この出力パルス周波
数はカウンタ４によって計数され、その計数値θ１に応
じて前記第２の２相交流入力信号e1S・e1Rを発生するリ
ードオンリメモリ5a,5bが作動する。すなわち、リード
オンメモリ5aはe1R＝cosθ１を出力する。また、α設定
器12は第１の２相交流入力信号eR・esの相間位相差αを
設定し、減算器13にて計数値θ１をθ１−αとして、リ
ードオンリメモリ5bに与える。このリードオンリメモリ
5bは、前記リードオンリメモリ5aと同一のデータが書き
込まれており、e1S＝cos（θ１−α）を出力する。Using the digital-analog converters 8 and 9 and the subtracter 10 which have e R and e 1S and e S and e 1R as inputs, and have the multiplication function, (11)
The operation in the parentheses of the equation is performed, and the signal sin α · E 0 · Δθ proportional to the phase difference signal Δθ is calculated. Then, the signal sin α · E 0 · Δθ proportional to the phase difference signal Δθ is amplified by the control amplifier 2 and the signal V 1 is calculated. Then, the signal V 1 is input by the voltage-frequency converter 3, and the signal
A frequency corresponding to V 1 is generated. The output pulse frequency is counted by the counter 4, and the read-only memories 5a and 5b for generating the second two-phase AC input signals e 1S · e 1R are operated according to the count value θ 1 . That is, the read-on memory 5a outputs e 1R = cos θ 1 . Further, the α setter 12 sets the phase difference α between the phases of the first two-phase AC input signal e R · e s , and the subtracter 13 sets the count value θ 1 to θ 1 −α and sets it in the read-only memory 5b. give. This read only memory
The same data as that in the read-only memory 5a is written in 5b and outputs e 1S = cos (θ 1 −α).
このように第２の２相交流入力信号e1R・e1Sとの相間位
相差αを、α設定器12にて設定するだけで、他の部分は
回路変更なしに第１の２相交流入力信号eR・esを、多相
交流のうち相間位相差が180゜を除くものから任意に選
択して使用することができる。In this way, the phase difference α between the second two-phase AC input signals e 1R and e 1S is set by the α setter 12, and the other parts are the first two-phase AC input without changing the circuit. The signals e R and e s can be arbitrarily selected and used from the polyphase alternating currents except for those having a phase difference between phases of 180 °.
以上のように、この発明によれば、多相交流信号におけ
る任意の２相交流信号間の位相差を設定する位相設定器
を設けることにより、その設定された位相差だけ位相が
異なる２つの交流信号を発生させ、その２つの交流信号
と前記任意の２相交流信号に基づいて位相差信号を演算
するように構成したので、入力される２相交流信号間の
位相差が90゜でなくとも、位相差信号を演算することが
できるようになり、その結果、入力される２相交流信号
間の位相差は90゜に限定されず（ただし、位相差が180
゜の２相交流信号は除く）、例えば、位相差が90゜でな
い３相あるいは６相の交流信号であっても、多相−２相
変換器を設けることなく位相差を検出することができる
効果がある。As described above, according to the present invention, by providing the phase setting device that sets the phase difference between arbitrary two-phase alternating current signals in the multi-phase alternating current signal, the two alternating currents whose phases differ by the set phase difference. Since the signal is generated and the phase difference signal is calculated based on the two AC signals and the arbitrary two-phase AC signal, the phase difference between the input two-phase AC signals is not 90 °. , It becomes possible to calculate the phase difference signal, and as a result, the phase difference between the input two-phase AC signals is not limited to 90 ° (however, the phase difference is 180
2 phase AC signal is excluded), for example, even if it is a 3-phase or 6-phase AC signal having a phase difference of not 90 °, the phase difference can be detected without providing a multi-phase to 2-phase converter. effective.
第１図はこの発明の一実施例を示す位相検出器の原理
図、第２図は第１図の細部構成を示すブロック図、第３
図は従来の位相検出器を示す原理図である。 図において、１は位相比較器、２は制御増幅器、３は電
圧−周波数変換器、４はカウンタ、5aはリードオンリメ
モリ（第１の交流信号発生器）、5bはリードオンリメモ
リ（第２の交流信号発生器）、８はディジタル−アナロ
グ変換器（第１の乗算器）、９はディジタル−アナログ
変換器（第２の乗算器）、10,13は減算器、12はα設定
器（位相設定器）である。 なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a principle diagram of a phase detector showing an embodiment of the present invention, FIG. 2 is a block diagram showing a detailed configuration of FIG. 1, and FIG.
The figure is a principle diagram showing a conventional phase detector. In the figure, 1 is a phase comparator, 2 is a control amplifier, 3 is a voltage-frequency converter, 4 is a counter, 5a is a read-only memory (first AC signal generator), and 5b is a read-only memory (second AC signal generator). AC signal generator), 8 is a digital-analog converter (first multiplier), 9 is a digital-analog converter (second multiplier), 10 and 13 are subtractors, 12 is an α setter (phase) Setting device). In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (1)
圧−周波数変換器と、前記電圧−周波数変換器により発
生された周波数を計数するカウンタと、多相交流信号に
おける任意の２相交流信号間の位相差が設定された位相
設定器と、前記カウンタの計数値から前記位相設定器に
設定された位相差を減算する減算器と、前記カウンタの
計数値に応じた交流信号を発生する第１の交流信号発生
器と、前記減算器の減算結果に応じた交流信号を発生す
る第２の交流信号発生器と、前記任意の２相交流信号の
うち位相の進んだ交流信号と前記第２の交流信号発生器
が発生する交流信号とを乗算する第１の乗算器と、前記
任意の２相交流信号のうち位相の遅れた交流信号と前記
第１の交流信号発生器が発生する交流信号とを乗算する
第２の乗算器と、前記第２の乗算器の乗算結果から前記
第１の乗算器の乗算結果を減算し、前記位相差信号に比
例した信号を出力する減算器と、前記減算器が出力する
位相差信号に比例した信号を増幅し、信号を前記電圧−
周波数変換器に出力する制御増幅器とを備えた位相検出
器。1. A voltage-frequency converter that generates a frequency corresponding to a phase difference signal, a counter that counts the frequency generated by the voltage-frequency converter, and an arbitrary two-phase AC signal in a multi-phase AC signal. A phase setter in which a phase difference between them is set, a subtracter that subtracts the phase difference set in the phase setter from the count value of the counter, and an AC signal corresponding to the count value of the counter No. 1 AC signal generator, a second AC signal generator that generates an AC signal according to the subtraction result of the subtractor, and an AC signal with an advanced phase among the arbitrary two-phase AC signals and the second AC signal generator. First multiplier for multiplying the alternating current signal generated by the alternating current signal generator, an alternating current signal with a phase delay among the arbitrary two-phase alternating current signals, and an alternating current signal generated by the first alternating current signal generator A second multiplier for multiplying and The subtractor that subtracts the multiplication result of the first multiplier from the multiplication result of the second multiplier to output a signal proportional to the phase difference signal, and the phase difference signal output from the subtractor The signal is amplified and the signal is
A phase detector having a control amplifier for outputting to a frequency converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63300309A JPH0783584B2 (en) | 1988-11-28 | 1988-11-28 | Phase detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63300309A JPH0783584B2 (en) | 1988-11-28 | 1988-11-28 | Phase detector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02145978A JPH02145978A (en) | 1990-06-05 |
| JPH0783584B2 true JPH0783584B2 (en) | 1995-09-06 |
Family
ID=17883227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63300309A Expired - Lifetime JPH0783584B2 (en) | 1988-11-28 | 1988-11-28 | Phase detector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0783584B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10132846B2 (en) * | 2016-06-14 | 2018-11-20 | Analog Devices Global | Method of and apparatus for learning the phase error or timing delays within a current transducer and power measurement apparatus including current transducer error correction |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6037711A (en) * | 1983-08-10 | 1985-02-27 | 三洋電機株式会社 | Method of producing film capacitor |
-
1988
- 1988-11-28 JP JP63300309A patent/JPH0783584B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02145978A (en) | 1990-06-05 |
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