JPH0783367B2 - Data transmission control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Use of the Invention] The present invention relates to loop-type data in which a plurality of computer systems each having an I / O device for data transmission are connected in a loop by a transmission / reception line of the I / O device. The present invention relates to a transmission system, and more particularly to a loop type data transmission control system suitable for high-speed data transmission.

[Background of the Invention]

In the conventional loop data transmission system, a transmission I / O device connected to a common bus of a transmission control processor receives line data and reads the data word by word. An example of this is shown in FIG.

The transmission control processor 1 is used for data transmission of the received data received by the data transmission I / O device 2 for each word length.
An interrupt program activated by an interrupt signal 7 output from the I / O device 2 fetches received data for each word length through the data bus 6. The computer checks the content of the data following the synchronization word at the head of the received frame and switches the transmission mode from the computer.

The transmission mode is a through mode in which received data is transferred to a computer while allowing data to pass downstream, and a store-and-forward mode in which data is transferred to the computer once without being passed to the downstream, once taken into the computer, judged by the computer. There is a forward mode, and these two modes are selected by writing from the computer to the control register of the I / O device. Therefore, if the line speed of the loop becomes faster than the processing speed of the computer, even if the I / O device receives data, even if it is not the data that should be passed downstream, the mode switching command is output. Since the processing for doing so is slow, there is a drawback that it passes downstream.

In order to solve this, it is necessary to increase the processing speed of the computer, but in order to realize this, a large-scale circuit is required, which is difficult in terms of downsizing and weight reduction of the device and cost performance.

[Object of the Invention]

An object of the present invention is to provide a loop transmission system in which a computer system having an I / O device for data transmission is connected in a loop form by n (n ≧ 2) by transmission / reception lines of the transmission I / O device. When one frame of data is received through the transmission I / O device, when the pattern indicating the registered reception content matches the content of the received data, the data is suppressed by suppressing the passage of the data to the downstream side. It is to provide a loop-type data transmission control system that enables simple and reliable transmission.

[Outline of Invention]

In the loop type transmission control device described for the above purpose, the DMA
When data is received through the transmission I / O device by transfer, the data is passed to the data reception mode in each transmission I / O in the downstream, and the data is taken into the computer, the through reception mode, and the downstream. Has a store-and-forward reception mode in which transmission is stopped once, and once received, the reception data is transmitted again from the transmission port.

When the DMA transfer is performed in the through reception mode, if the processing speed of the computer is slower than the transfer speed of the line and the data length of one frame is short, the data passing through the store or store and Even if the data should be forwarded, the computer recognizes the reception of the data,
There is not enough time to switch to store-and-forward reception mode, and data passes downstream.

Therefore, the downstream computer system is supposed to receive the two data, the data that has passed through the I / O device of the upstream computer system in the through mode and the data that is output from the upstream computer system by store and forward. Therefore, double reception of the same data occurs.

That is, in such a case, it is necessary to give up the through mode reception.

In order to solve this, the present invention provides a storage device for storing a content code for identifying the content of a data body in one frame, and broadcasts from this computer system to another computer system in advance in this storage device. Stores the content code of data that should not be sent to the downstream side in through mode, such as data that was once output for communication and then transmitted once again through the loop to the local system. When data is received, synchronization is performed. A means for detecting that the content code and the storage pattern of the storage device match the flag is data to be trapped, and further, in order to prevent passage of data by the trap detection signal, With the gate provided downstream of the transmission I / O,
To suppress the output of transmission data,
Keep high. By doing so, the data to be trapped is transferred to the gate before the transmission control processor checks the received data stored in the DMA memory and switches the I / O device from the through mode to the store-and-forward mode. This prevents passage to the downstream.

Further, the transmission mode switch is reset by the transmission request signal for transmitting the data from the transmission I / O, and enables the transmission of the data downstream.

Example of Invention

 An embodiment of the present invention will be described below with reference to FIG.

The transmission control device (NCP) is a computer 1 that controls transmission.
It is composed of a transmission I / O device 2, a DMA transfer storage device 3, a DMA controller 9, a transmission mode switching signal generator 10, and a transmission mode switching device 11, which are connected via the bus 6.

The computer 1 sets the transmission data in the DMA transfer storage device 3, activates the DMA controller, and transmits the I / O device 2 for transmission.
Send data from.

This transmission I / O device is an LSI that supports the HDLC procedure.

The transmission data 5 (TD) from the transmission I / O device 2 is transmitted via the transmission mode switch 11 to the transmission data output signal 15 (TD).
out) is sent on the loop.

When the transmission I / O device is set for transmission, the transmission request signal 16 output from the transmission I / O resets the transmission mode switching signal generator 10 and resets the transmission mode switching signal 14. When reset, the transmission mode switching signal 14 outputs the transmission data TD as it is as a transmission data output signal.

Next, when receiving the data, the computer 1 uses the DMA for reception.
Reserve the transfer buffer and set the DMA controller channel to receive mode.

Received data 4 (RD) has a data format of 1 frame
As shown in the figure, the sync flag is followed by a code indicating the contents of data, and then the contents of Data and the contents of the frame are checked. Frame check sequence (FCS)
It serves as a synchronization flag indicating the end of the signal data.

The transmission I / O device is set to the DMA transfer mode and receives the above frame data word by word.

The transfer request signal 12 from the transmission I / O is D at each word length reception.
The data is output to the MA controller, and the DMA controller transfers the received data from the transmission I / O device to the DMA transfer storage device 3. By repeating the above-described operation, reception and accumulation are performed when there is received data, and the operation mode of the transmission I / O device 2 includes a through mode and a store-and-forward mode. In the case of the through mode, the received signal is transferred to the DMA transfer storage device 3 by the above-mentioned receiving and accumulating operation and also passed through the signal line 5. In store-and-forward mode, the received signal is
Transferred to a predetermined address in the DMA transfer storage device 3, while
The data stored in the DMA transfer storage device 3 in the past is output to the signal line 5. The operation mode switching of the transmission I / O device 2 is executed by rewriting the control register (not shown) in the transmission I / O device 2 by the computer 1. The switching between the through mode and the store-and-forward mode as described above is described in JP-A-57-24144. In the present embodiment, in order to eliminate the drawback due to the time delay of the operation mode switching of the transmission I / O device by the computer, the transmission mode switch 14 is provided on the output signal line 5 of the transmission I / O device. A transmission mode switching control signal generator 10 for controlling this is provided. When the content code of the frame data is received, the transmission mode switching signal detection timing signal 13 is output from the DMA controller to the transmission mode switching signal generator 10.

The transmission mode switching signal generator 10 outputs the received data when the content of the content code storage device in which the pattern of the content code to be trapped from the computer 1 is registered in advance and the content of the received data read by the DMA match. The transmission mode switching signal 14 is set and output to the transmission mode switching device 14 so as not to pass downstream.

The transmission mode switching device 14 sets the transmission data output signal 15 to, for example, High because the transmission mode switching signal 14 is set.
Fixed to block the passage of subsequent received data. For content codes other than those registered, the transmission mode switching signal is not set.

After that, the computer 1 checks the content of the received data and selects whether the mode of the transmission I / O device is the through mode or the store and forward mode.

Next, referring to FIG. 4, a method of generating the transmission mode switching timing signals 13 and 13 'output by DMA will be described. DMA
Is composed of, for example, an address count register 9a, a data count register 9b, a control register 9c, and a status register 9d, where 9a is the transfer address of the DMA transfer storage device, 9b is the transfer word count, and 9c is the DMA transfer address. DMA the address code of the I / O device to be used and the R / S signal indicating the receive / transmit mode to the status register 9d.
Control status indicating the transfer status of the controller, for example, in the case of reception, reception ready RD
Set Y, receiving BSY, receiving completion CMPL, idle state IDLE.

Each register 9a, 9b, 9c, 9d is installed for each channel.

The operation of only one channel will be described below.

When the transmission I / O device receives the data, the transfer request signal 12 is output from the transmission I / O device. On the other hand, each register outputs a signal corresponding to the channel.

The data count is output from the data count register, the reception timing of the content code of the reception data following the synchronization flag is detected by decoding the reception data count value by the decoder 9e, and is input to the AND gate 9g.
Receive / transmit mode signal from control register 9c
The R / S signal is output and input to the AND gate 9g, and the device select signal is output, decoded by the decoder 9f, and input to the AND gate 9g.

From the status register 9d, RDY indicating the ready to receive
The signal is output and input to the AND gate 9g.

This RDY signal indicates that the DMA is ready and is output even during the DMA transfer. From the completion of the DMA transfer to the completion of the DMA preparation,
No output.

The transfer request signal 12 from the transmission I / O device 2 is further input to the AND gate 9g, and the result obtained by ANDing the inputs is sent to the transmission mode switching signal generator 10 as the transmission mode switching timing signal 13. Output.

In addition, even if the transfer request signal 12 is input to the DMA controller, even if the status of DMA is not ready RDY
Since the I / O device cannot receive the data, it has to interrupt the passage of the data. Therefore, the RDY signal is inverted by the inverter 9h, the transfer request signal 12, the device select signal, and the reception mode signal R / S are
It is input to the ND gate 9i, and the ANDed result is used as the transmission mode switching timing signal 13 ', and the transmission mode switching signal generator 10
Output to. As a result, the passage of data to the downstream is interrupted, but the reception data is discarded because the preparation for reception is not completed even in the own computer system.

FIG. 5 shows an embodiment of the transmission mode switching signal generator.

The computer 1 stores the storage devices 10a ₁ to 10a via the data bus.
The content code of the received data is registered in a _i (i is the number of bits of the word) in a bit pattern.

If you want to register the corresponding bit, set it to Low.
To set. The registered bit pattern is the inverter 10
Inverted at b, input to AND gate 10c, and received data input from the transmission I / O device via the data bus.
The AND gate is used and the output of the AND gate 10c is NOR gate.
Enter in 10d. In this way, the output of the NOR gate 10d becomes High when all the received data bits corresponding to the registered bits are Low.

NOR gate 10d output and transmission mode switching timing signal 13
Is used as the input of the AND gate 10e, AND is taken, and the OR gate 10f
And input. The output of 10f is connected to the set input of the storage device 10g, and when the output of the NOR gate 10d is High and the transmission mode switching timing signal is High output, the transmission mode switching signal 14 that is the output of 10g is set to High. Set.

Therefore, among the bit patterns set in the memory devices 10a _{1 to} 10a _i in advance, the set bit of Low is
The transmission mode switching signal 14 is output only when the received data are all low.

Similarly, the transmission mode switching timing signal 13 'is High.
Also in this case, the transmission mode switching signal 14 is output High.
That is, when RDY is ready for reception, the transmission mode switching signal is output. Next, send data to the transmission I / O
When the device 2 is changed to the store-and-forward mode, or when the data generated in the own computer system is received, that is, when the internal data of the DMA transfer storage device 3 is to be output as the transmission data, the transmission I / O device is The output transmission request signal 16 (RTS) is output and the transmission mode switching signal is reset.

FIG. 6 shows the configuration of the transmission mode switch 11.

When the transmission mode switching signal 14 is set to High,
Regardless of the state of the output TD5 of the transmission I / O device, the transmission data output TDout15 is fixed to High, the output TD5 of the transmission I / O device is cut off, and the reception data received in the through mode is sent to the downstream. Block passage. Transmission mode switching signal 14
Is reset by the transmission request RTS, the transmission I / O
Device output TD5 is unchanged, transmit data output TDout15
Is transmitted downstream.

〔The invention's effect〕

According to the present invention, in a loop transmission system in which n (n ≧ 2) transmission control computers are connected through a transmission I / O device, the computer receives one frame of data from a loop transmission line. Regarding the data which should be blocked by the first means, the first means for detecting the data which should be blocked from passing downstream when the pattern showing the preset data content and the received data are coincident with each other are provided. , By providing the second means for interrupting the output to the downstream, the loop line speed is high, and the computer can switch the transmission mode of the transmission I / O device from the through mode to the store and forward mode. When it is not possible, there is an effect that the transmission control can be performed easily and surely.

Further, even when the preparation for receiving the data is not completed, the third means for detecting that the preparation for receiving the data is not completed operates the second means to prevent the data from passing downstream. Can be stopped.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional loop type transmission control device, FIG. 2 is a block diagram showing an embodiment of the loop type transmission control device according to the present invention, and FIG. 3 is a transmission of the loop type transmission control device. Data format diagram, FIG. 4 is a block diagram showing a configuration example of a DMA controller, FIG. 5 is a block diagram showing a configuration of a transmission mode switching signal generator, and FIG. 6 is a block diagram showing a configuration of a transmission mode switching device. Is. 1 ... Processor, 2 ... I / O device for information transmission, 3
...... Recording device, 4 ... Received data (RD), 5 ... Transmitted data (TD), 6 ... Data bus, 7 ... Interrupt signal, 8 ...
… Transmission mode switching signal, 9 …… DMA control device, 10 …… Transmission mode switching signal generator, 11 …… Transmission mode switching device, 12
...... Transfer request signal, 13 …… Transmission mode switching signal detection timing signal, 14 …… Transmission mode switching signal, 15 …… Sending data output signal (TDout), 16 …… Sending request signal.

Claims (1)

[Claims] 1. A plurality of computer systems in which a processor, a storage device, and a transmission I / O device are connected on a common bus are connected in a loop through signal lines connected to the transmission I / O device. I / O for transmitting and receiving data between the computer systems.
The device has a through mode in which data from the upstream side is taken in while allowing the data from the upstream side to pass through to the computer system on the downstream side by the mode selection of each processor, and an operation to transmit the data of the own system to the computer system on the downstream side. In a loop type data transmission control method having a function of switching to a store-and-forward mode in which the operation of fetching data from the upstream side into its own system is performed in parallel, transmission to the other system is suppressed based on an instruction from the processor. Means for preregistering the content code of the received data to be detected, generating a trap detection signal by detecting a match between the registered content code and the content code of the received data read from the I / O device, and the trap detection The transmission I / O during the period when the signal is emitted.
A gate means for prohibiting data output to the signal line is provided at the output part of the transmission data from the device to the computer system on the downstream side, and the processor checks the data taken in via the transmission I / O device. I / for transmission
Loop type data, characterized in that before switching the O device from the through mode to the store and forward mode, the reception data to be output to the downstream side by the gate means to be suppressed from being transmitted to the other system is stopped. Transmission control method.