JPH0782478B2 - Multi-processor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is capable of processing a large amount of data in parallel at high speed by connecting a large number of processors each having a local memory by a processor combination device having a high-speed data transfer switching function. It relates to a multiprocessor system.

[Conventional technology]

Conventionally, various coupling forms have been proposed for a multiprocessor system in which a large number of processors each having a local memory are coupled, but mainly, a bus coupling type and a crossbar switch coupling type are known. ing.

The bus coupling type is a mode in which a plurality of processors each having a local memory are coupled by a bus composed of a plurality of data and control lines. Usually, the plurality of processors are coupled via a parallel input / output link or a communication link. Communication between processors is realized by input / output instructions. However,
Such a bus-coupled type requires input / output operations for information transfer, and is economical, but has a problem that the information transfer rate decreases as the number of processors increases. Used only for large multiprocessor systems.

On the other hand, as a conventional example of the crossbar switch coupling type, as shown in FIG. 5, an ADENA computer (T ・ Nogi, “THE ADENA COMPUTER”, International
Symposium on Applied Mathematics and Information
Science, Kyoto University, 1982) is known. In FIG. 5, 51 and 52 are processors P having local memories M arranged in the X and Y directions, respectively, so that data can be exchanged between arbitrary processors N.
A buffer memory 53 is provided in a matrix of × M. However, in such a combined mode, for example, when a plurality of processors 51 in the X direction try to transfer data to the same processor 52 in the Y direction, a so-called route selection control circuit that selects one of the processors is selected. Also, the buffer memory 53 is required, the control circuit becomes complicated as the number of processors increases, and a large capacity of the buffer memory 53 is required, resulting in a problem in economic efficiency.

[Problems to be solved by the invention]

In the bus-coupled and crossbar switch-coupled multiprocessor systems that combine multiple conventional processors with local memory as described above, the transfer rate of each information decreases as the number of processors increases, and route selection However, it is not suitable for constructing a large-scale multiprocessor system because of the problems such as the complicated control circuit and the increase of buffer memory capacity.

The present invention has been made in order to solve the above problems in a multiprocessor system that processes a large amount of data having a complicated structure in parallel at a high speed. Directly coupled through a processor bus (CPU bus) by using a processor coupling device having a CPU, prevents a decrease in information transfer rate, has a simple circuit configuration, is large-scale, highly reliable, and is relatively inexpensive The purpose is to provide a system.

[Means for solving problems]

The multiprocessor system according to the present invention is a multiprocessor system in which a plurality of processors 11 each having a local memory M are connected to each other to perform data transfer between the processors, and n input ports 21, 22 are provided.
... and n output ports 22, 22, ..., Processor bus interface 23, path selection means (path selection control circuit 24), and each of the input ports and output ports, A processor coupling device 12 having a register (state register 25) holding operation state control information (state 0 to 2, output state) for controlling the operation state of each port is provided for each processor, and each input is provided. The port takes in the data, and when the corresponding register indicates the first operation state control information (state 0), the port selects the route selection means based on the transfer destination processor number information included in the data. When activated, the first process of selecting the output port to which the data is to be transferred and the corresponding register indicating the second operation state control information (state 1) are displayed. The second process for determining the use state of the output port selected by the first process at the time of the above, and the corresponding one of the registers when the corresponding register indicates the third operation state control information (state 2). Executes the third process of transferring the data to the output port selected by the process of 1 and determined to be usable by the process of 2, and the output port of each output port can output the data of the corresponding register. If the data is already transferred from each of the input ports when the operation state control information (output state) indicating that the data is already transferred, the process of transferring the data to the transfer destination processor is executed, and each of the registers The processing of each port based on the operating status control information of 1. divides the data transferred to each port into a certain byte unit (element byte unit), ·· n
The second input port, the 1,2, ..., The nth output port are executed in this order, and are executed by the repeated time division processing.

[Operation] Based on the operation state control information of the corresponding register, each input port performs route selection processing (first processing), output port usage state check (second processing), and data transfer to output port ( The third process) is performed. In addition, each output port shows the operation state control information (output state) indicating that the corresponding register can output data, and if the data has already been transferred from each input port, the data is transferred. Transfer to the destination processor. The processing of each of these input ports and each of the output ports is performed by time division processing. This first divides the data being transferred to each port into certain bytes. That is, specifically, the variable-length packet arriving at each port is divided into each element byte such as the first byte, the second byte, the third byte ... (Normal data byte), the end byte,
Each port processes once per element byte. Then, the port processing is performed in the order of the 1,2, ... nth input port and the 1,2, ... nth output port, and the processing of each port is repeated in this order. As a result, high-speed time-division processing is performed, and the processing as a whole is processed in parallel.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
The figure is a block diagram showing the configuration of the multiprocessor system of this embodiment. 11 is a processor P having a local memory M, 12 is 4 input ports, 4 output ports and a processor bus interface. The processor is a coupling device, and the processor coupling device 12 is used as a node to couple and configure the processor.

FIG. 2 is a block diagram of the processor coupling device 12 in this embodiment. The processor coupling device 12 includes a plurality of (four in this case) input ports 21, output ports 22, a processor bus interface 23, a route selection control circuit 24,
A status register 25 described later is provided. Input port
The output port 22 and the output port 22 are independent of each other, and when the processor bus interface 23 is included, the connection form is 5 to 5, and a maximum of 5 routes can be opened simultaneously.
That is, in the case of a processor coupling device having n input ports, n output ports and a processor bus interface, a maximum of n + 1 paths will be opened at the same time.

FIG. 3 is a diagram showing a packet format. The route selection (routing) control of the route selection control circuit 24 shown in FIG. 2 is performed, for example, by sending from the destination processor number written in the first byte 31 of the packet. This is done by selecting the previous output port 22. At this time, the packets are retransmitted to the output ports 22 of different destinations, and the destination output port
When 22 do not compete, data transfer is executed in parallel at the same time, and the data transfer function is maximized. In addition, each output port 22 is provided with a FIFO (first in first out) type buffer memory that sequentially processes and outputs data that has been input first in order to eliminate stagnation of transferred data and improve transfer efficiency. ing. Further, for the purpose of enhancing the data exchange transfer function within the node, in order to enable the simultaneous parallel opening of routes and the data parallel transfer, the processor coupling device 12 shown in FIG. A status register 25 that manages status information is provided for each port 2.
The element bytes of the variable-length packet arriving at 1,22 are the first byte 31, the second byte, the normal data byte 32, ...
Different processing depending on the end byte 33
It will be done in a time-sharing manner while watching the contents of 25.

FIG. 4 (a) is a flowchart for explaining the state number held by the state register in each input port and the processing of the element byte of the packet in each state. In the state 0 (41), for example, so-called route selection processing for selecting the output port 22 of the data transmission destination by the destination processor number written in the first byte 31 of FIG. 3 is performed. In the state 1 (42), it is checked whether or not the selected output port 22 is in operation and is Busy (busy), and when it is not Busy, the right to use the output port 22 is obtained and the head is obtained. Transfer the byte 31 and set its output port 22 to Busy. In the state 2 (43), it is determined whether it is the normal data byte 32 or the end byte 33, and when it is the normal data byte 32, the state of the state 2 remains the same.
32, while on the other hand, if it is the end byte 33, the end byte 33 is transferred and the output port 22 in use
Release Busy and return to state 0.

Since each input port 21 processes the element bytes of the packet in a time division manner by the state management of the state register 25 as described above, a plurality of paths are simultaneously opened in parallel in the processor coupling device 12 and high speed data transfer is performed. .

Although the state management of the state register 25 in the input port 21 is described in the operation explanation based on the flowchart shown in FIG. Element bytes of are processed. Compared to the processing at the input port 21, the processing at the output port 22
Since there is no route selection process or element byte discrimination process, and only the process corresponding to the transfer process, it is simple and has only one state. That is, as shown in FIG. 4B, in the output state 44, first, it is determined whether or not the output buffer is not empty and ready for output, and the element bytes have been transferred to the output buffer and output is ready. If there is, output processing is performed, and similarly to the input port 21, each output port 22 is repeatedly processed in order in element byte units in time division.

〔The invention's effect〕

As described above, according to the present invention, a large number of processors having a local memory are combined and configured by using a processor combination device having n input ports, n output ports and a processor bus interface as a node. However, in order to open a maximum of n + 1 paths simultaneously in parallel and enable parallel data transfer, the processor coupling device is provided with a status register for managing status information for each port, and the contents of this status register are While observing, by configuring the element bytes of the packet arriving at each port to be processed in a time-sharing manner, a large number of processors with local memory
Since they can be easily combined by using a processor combination device, it is possible to prevent a decrease in information transfer rate, and to provide a large-scale, highly reliable, and relatively inexpensive multiprocessor system with a simple circuit configuration. The effect is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a multiprocessor system according to an embodiment of the present invention, FIG. 2 is a block diagram of a processor coupling device according to this embodiment, FIG. 3 is a diagram showing a packet format, and FIG. ) Is a flowchart for explaining the state number held by the state register in each input port and the processing of the element byte of the packet in each state according to this embodiment, and FIG. 4B shows the processing of each output port similarly. The flowchart shown in FIG. 5 is a block diagram of a conventional multiprocessor system. 11 …… Processor with local memory, 12 …… Processor coupling device, 21 …… Input port, 22 …… Output port,
23 ... Processor bus interface, 25 ... Status register, 31 ... First byte, 32 ... Normal data byte, 33 ... End byte, M ... Local memory, P ...
Processor.

Claims (1)

[Claims] 1. A multiprocessor system in which a plurality of processors each having a local memory are connected to each other to transfer data between the processors, wherein n input ports and n output ports and a processor bus are provided. A processor coupling device having an interface, a route selection means, a register provided for each of the input ports and output ports, and holding operating state control information for controlling the operating state of each port Each of the input ports fetches data, and when the corresponding register indicates the first operation state control information, the route is based on the transfer destination processor number information included in the data. Corresponding to the first process of selecting the output port to which the data is to be transferred by operating the selection means. Second register for determining the usage status of the output port selected by the first processing when the register indicating the second operation status control information and the corresponding register for the third operation status. When the control information is indicated, a third process of transferring the data to the output port selected by the process of 1 above and determined to be usable by the process of 2 above is executed, and each output port corresponds to When the register indicates the operation state control information indicating that data can be output, if the data has already been transferred from each of the input ports, the process of transferring the data to the transfer destination processor is executed. In addition, the processing of each port based on the operation status control information of each register divides the data transferred to each port into certain bytes. 1,2, · · · n-th input port, 1,2 multiprocessor system characterized in that it is executed by a division process when repeated taking place in the order of · · · n-th output port.