JPH0779457B2 - Television motion detection device - Google Patents

Description

The present invention relates to a television image applied to a field number conversion process in a system conversion for converting a high-definition television signal into a PAL system television signal, for example. Motion detector.

[Outline of Invention]

According to the present invention, the first field and the second field of the normal television signal are formed from the signal of one field of the high definition television signal, and the first field and the second field are formed.
In a device for detecting an image movement from a signal in one of the fields, a difference between a representative point of a detection area formed by a plurality of pixel data in one field and each pixel data in the detection area The value is calculated, the minimum value is detected in the data obtained by summing up the absolute values of the difference values, the minimum value and pixel data in the vicinity of the minimum value are calculated, and the vertical component of the image motion detection signal is detected. Therefore, highly accurate motion detection is possible.

[Conventional technology]

In a format conversion device that converts a high-definition television system (HD system) into a PAL system, motion compensation is performed when converting the number of fields, that is, when converting from 60 fields to 50 fields. FIG. 6 shows an example of the system conversion device proposed previously.

In FIG. 6, the luminance signal in the high-definition television signal is supplied to the input terminal indicated by 1, and this luminance signal is supplied to the A / D converter 2 via a low-pass filter (not shown). The digital luminance signal from the A / D converter 2 is supplied to the line number conversion circuits 3 and 4. The line number conversion circuits 3 and 4 perform line number conversion and deinterlacing processing.

The number of lines is converted from 1125 to 625 using, for example, the technique of digital frequency conversion. In addition, the number of lines is 62 from the video of one field of the high definition television signal.
Five first field images and second field images are simultaneously formed. The video of the first field and the video of the second field are offset by 0.5 line. However, the line number conversion circuit 3 always outputs the PAL system first field image signal, and the line number conversion circuit 4 outputs the second field image signal. Therefore, from the line number conversion circuit 3, A digital video signal consisting of only the first field of is obtained, and from the line number conversion circuit 4, A digital video signal consisting of only the second field of is obtained.

FIG. 7A partially shows a non-interlaced scanning line structure in which the number of lines has been converted. In FIG. 7A, the white circles indicate the first field line (solid line) and the second field.
Pixels included in each field line (broken line) are shown. Each of the line number conversion circuits 3 and 4 simultaneously outputs the first field data shown in FIG. 7B and the second field data shown in FIG. 7C. That is,
A pair of the 23rd line of the first field and the 336th line of the second field are simultaneously output, and similarly, a pair of (24,337) th line, a pair of (25,338) th line, (26,339). ) The second line pair is output at the same time.

The motion vector is detected by the first conversion from the line number conversion circuit 3.
The conversion process of the number of fields is performed using the video signal of the field, and is performed for each of the first field and the second field. Reference numeral 7 denotes a motion detection circuit for detecting a motion vector, and the motion detection circuit 7 is supplied with the digital video signal of the first field. Further, the output signal of the line number conversion circuit 3 is supplied to the frame memory 5 and the image shift circuit 9, and is supplied to the output signal frame memory 6 and the image shift circuit 11 of the line number conversion circuit 4. The signal one field before read from the frame memories 5 and 6 is supplied to the image shift circuits 8 and 10.
The output signals of the image shift circuits 8 and 9 are supplied to the adder circuit 16, and the output signals of the image shift circuits 10 and 11 are added.
Is supplied to. The output signal of the adder circuit 16 is the frame memory
18 and the output signal of the adder circuit 17 is supplied to the frame memory.
Supplied to 19. The frame memories 18 and 19 are provided for time axis expansion.

The motion detection circuit 7 calculates the difference between the representative point of the previous field and the pixel data of the current field (field difference data) for each detection area, totals the absolute values of this field difference data, and generates the field difference totalized data. However, the minimum value of the field difference aggregation data is detected. The motion detection circuit 7 obtains a motion vector corresponding to the motion of the image. This motion vector is a signal composed of a horizontal (x) direction component and a vertical (y) direction component.

The motion detection area is a rectangular area having a center as an origin and having a predetermined spread in each of the x direction and the y direction. Further, as shown in FIG. 8A, the motion detection areas and the x-direction overlap each other, and one detection area R1 is overlapped with the detection areas R2, R3, and R4. Therefore, in the x direction, the detection areas overlap four-fold. In addition, the detection regions overlap in the y direction as well, and as shown in FIG. 8B, the detection region R6 overlaps with one detection region R5. In this way, the detection areas overlap in both the x-direction and the y-direction, so that the detection areas overlap eight times in total.

Due to the overlapping of the detection areas as described above, the motion detection circuit 7 is configured to be capable of processing eight sets as shown in FIG. In FIG. 9, a digital video signal from the line number conversion circuit 3 is supplied to an input terminal indicated by 30, and this digital video signal is converted into eight subtraction circuits 31,3.
2, 33, 34, 35, 36, 37, 38 and the representative point frame 39 are supplied. From the representative point frame memory 39, representative point data of the previous field located at the origin of each of the eight detection areas overlapping each other is output, and the eight representative point data are supplied to the subtraction circuits 31 to 38. The subtraction output signals (field difference data) of the subtraction circuits 31 to 38 are summed up circuits 41, 42, 43, 44, 4
It is supplied to 5,46,47,48 and the absolute value of the field difference data is totaled over one field. The data of the summed results of the summation circuits 41 to 48 are supplied to the addition circuit 49,
The output signal of the adder circuit 49 is supplied to the minimum value detection circuit 50. The minimum value (x,
y) The position on the coordinate is the motion vector.

The image shift circuits 8, 9, 10, 11 to which the motion vector from the motion detection circuit 7 is supplied shifts the position of the image in the x direction and the y direction according to the motion vector. It is configured. An example of motion correction performed by these image shift circuits 8, 9, 10, 11 will be described with reference to FIG.

In FIG. 10, F1, F2, F3, F4, F5, and F6 represent images of six consecutive first fields. This image includes a moving object that moves from left to right every v (1/60) seconds by a constant velocity motion of v. This v is nothing but the motion vector detected by the motion detection circuit 7. In the case of this constant velocity motion, the total amount of movement from image F1 to image F6 is
It will be 5v. The six images F1 to F6 are converted into five images f1 to f5.
When converting to, it is necessary to increase the moving distance by (1/5) v.

As shown in FIG. 10, the image in which the image F1 in the previous field is not shifted at all and the image in which the image F2 in the current field is (−v) shifted are added, and the addition output is halved, The image f1 is formed. An image f2 is formed from the image F2 shifted by (1/5) v and the image F3 shifted by (-4/5) v. An image f3 is formed from the image F3 shifted by (2/5) v and the image F4 shifted by (−3/5) v. An image f4 is formed from the image F4 shifted by (3/5) v and the image F5 shifted by (−2/5) v. Image F5 shifted by (4/5) v and image F
An image f5 is formed from 6 shifted by (−1/5) v.

The image f6 formed from the next image F6 that has been v-shifted and the image F11 that has not been shifted at all includes the image F11 that has not been shifted at all and the image F12 (not shown) that has been shifted by -v. Since it has the same pattern as the image f11 to be formed, the overlapping image f6 is removed. After that, the correction operation shown in FIG. 10 is repeated again.

From frame memory 18 (625 lines / 50 fields)
The non-interlaced first field digital video signal is output, and the frame memory 19 outputs the (625 lines / 50 frames) second field digital video signal. The output signals of the frame memories 18 and 19 are supplied to the switch circuit 20. Switch circuit
A control signal that is inverted every (1/50) seconds is supplied to the terminal 20 from the terminal 21, and the output of the switch circuit 20 is (625 lines / 50
Field), that is, a PAL digital luminance signal is extracted. The D / A converter 22 converts the digital luminance signal into an analog luminance signal.

The motion detection in the system conversion device described above can obtain a motion vector with an accuracy of one sample in the x direction. However, the first field image (Fig. 7B
In order to perform the motion detection from
The motion vector can be obtained only with the accuracy of 2 lines in the 625-line interlaced image.

In order to solve this problem, it is conceivable to perform motion detection using both the first field image and the second field image. FIG. 11 shows a configuration for performing motion detection using both the first field image and the second field image.

That is, as shown in FIG. 11, the first field signal from the line number conversion circuit 3 and the second field signal from the line number conversion circuit 4 are supplied to the motion detection circuit 7. The motion detection circuit 7 detects a motion vector using a signal of one frame including a signal of the first field and a signal of the second field. The image shift circuits 8 and 9 shift the image of the first field based on the detected motion vector, and the image shift circuits 10 and 11 shift the image of the second field based on the detected motion vector.

The output signal of the image shift circuit 8 is supplied to the input terminals a of the switch circuits 12 and 14, and the output signal of the image shift circuit 9 is supplied to the input terminals a of the switch circuits 13 and 15. The output signal of the image shift circuit 10 is supplied to the input terminals b of the switch circuits 12 and 14, and the output signal of the image shift circuit 11 is supplied to the input terminals b of the switch circuits 13 and 15. The output signals of the switch circuits 12 and 13 are supplied to the adding circuit 16, and the output signals of the switch circuits 14 and 15 are supplied to the adding circuit 17. The switch circuits 12, 13, 14, and 15 are controlled by the line shift control signal generated by the motion detection circuit 7, respectively.
That is, when it is determined that the shift down of one line in the interlaced image is necessary, the switch circuits 12 and 13
Each input terminal b of is connected to the output terminal c
The output signal of the first field subjected to the shift processing is obtained at 16. When it is determined that one line in the interlaced image needs to be shifted to the upper side, each input terminal b of the switch circuits 14 and 15 is connected to the output terminal c, and the addition circuit 17 performs the shift process. The output signal of the second field is obtained.

The motion detection circuit 7 in FIG. 11 detects a motion vector from an image of one frame composed of the first field and the second field. FIG. 12 shows an example of the motion detecting circuit 7. Subtraction circuits 31 to 38 and summing circuit 4 in FIG.
1 to 48 and the adder circuit 49 are provided to calculate difference data for the image of the first field. Further, the subtraction circuits 61 to 68, the aggregation circuits 71 to 78, and the addition circuit 79 are connected to the input terminal 60.
It is provided to calculate the difference data for the image of the second field from the. The output signals of the adder circuits 49 and 79 are supplied to the adder circuit 80, the output signal of the adder circuit 80 is supplied to the minimum value detection circuit 50, and a motion vector is obtained at the output terminal 52. A component smaller than 2 lines in the interlaced image in the y-direction component of this motion vector is converted into a value of 1 line or 2 lines by rounding or the like, and the switch circuits 12, 13, 14, 15 are controlled according to this value. A line shift control signal for performing the operation is formed.

[Problems to be solved by the invention]

The smaller the unit amount of motion correction, the higher the accuracy of motion correction. As shown in FIG. 11, if the image of the first field and the image of the second field that are present at the same time are used, the It is possible to detect the motion in the direction with an accuracy of one line. However, since it is necessary to detect a motion vector for each image of the first field and the second field, there is a problem that the scale of hardware becomes large.

Therefore, an object of the present invention is to provide a motion detection device for a television image capable of performing motion detection with one line accuracy in the vertical direction by a small-scale hardware.

[Means for solving problems]

The present invention forms a first field and a second field of a normal television signal from a signal of one field of a high-definition television signal, and outputs an image from a signal of one of the first field and the second field. In a device for detecting motion, a difference value between a representative point of a detection area formed by a plurality of pixel data in one field and each pixel data in the detection area is calculated, and the absolute value of the difference value is aggregated. The minimum value of the quadratic curve formed by the circuit that detects the minimum value in the calculated difference data, the minimum value, and the data of at least two neighbors in the vertical direction of the minimum value in the distribution of the calculated difference data. A circuit for calculating and forming a vertical component of the image motion detection signal.

[Action]

The difference between the representative point of the previous field and the pixel data of the current field is calculated using the signal of one field of the high-definition (HD system) television signal, and the minimum value is calculated from the sum of the absolute values of this difference value. Is calculated, the scale of hardware for calculating the minimum value can be reduced. The vertical accuracy of the minimum value calculated in this way is the accuracy of two lines in an interless image of 625 lines. The minimum point is obtained by calculating the detected minimum value and pixel data in the vicinity of the minimum value.

The vertical accuracy of the minimum point can be set to 1 line or less.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. One example of this is (1125 lines / 60 fields)
High-definition television system (HD system) of (625 lines / 50
This is a format conversion device when converting to the field) PAL format. FIG. 1 shows the overall configuration of this (HD → PAL) system converter.

In FIG. 1, the luminance signal in the high-definition television signal is supplied to the input terminal indicated by 1, and this luminance signal is supplied to the A / D converter 2 via a low-pass filter (not shown). The digital luminance signal from the A / D converter 2 is supplied to the line number conversion circuits 3 and 4. The line number conversion circuits 3 and 4 respectively form a first field image and a second field image from a 1 field HD system image. The first field image and the second field image have an offset of 0.5 line. From the line number conversion circuit 3, A digital video signal consisting of only the first field of is obtained, and from the line number conversion circuit 4, A digital video signal consisting of only the second field of is obtained.

The output signal of the line number conversion circuit 3 is supplied to the frame memory 5 and the image shift circuit 9, and the output signal of the line number conversion circuit 4 is supplied to the frame memory 6 and the image shift circuit 11. The output signals of the frame memories 5 and 6 are supplied to the image shift circuits 8 and 10. Image shift circuit 8
Reference numerals 9 and 9 perform motion correction on the digital video signals of the previous field and the current field of the first field, and image shift circuits 10 and 11 perform motion correction of the digital video signals on the previous field and the current field of the second field.

That is, when converting from the HD system to the PAL system, the number of fields is converted from 60 fields to 50 fields. In this case, a motion vector (x sample, y line) composed of components in the x direction (sample direction) and y direction (line direction) is detected and motion correction is performed. Further, the image shift circuits 9 and 11 add (−1, −) to the detected motion vector.
4/5, −3/5, −2/5, −1/5) is used to shift the image of the current field by a shift command obtained by multiplying by
The image shift circuits 8 and 10 shift the image of the previous field by a shift command obtained by multiplying the detected motion vector by each coefficient (1/5, 2/5, 3/5, 4/5, 1). I do. This image shift is done in both the x and y directions.

The shift command for the image shift circuits 8, 9, 10, 11 is formed by the motion detection circuit 107. The motion detection circuit 107 is supplied with the digital video signal of the first field from the line number conversion circuit 3. Since the motion vector is detected from the signal of the first field, the image shift circuit 8
11 to 11, a motion vector is detected with an accuracy of 1 sample in the x direction, and a motion vector is detected with an accuracy of 2 lines in an interless image of 625 lines in the y direction. The output signals of the image shift circuits 8 to 11 are switched by the switch circuit 1 in order to perform motion correction with an accuracy of one line in the y direction.
It is supplied to 2,13,14,15 respectively.

The switch circuits 12 to 15 have input terminals a and b and an output terminal c, respectively, and the output signals of the image shift circuits 8 and 10 are supplied to the input terminal a and the input terminal b of the switch circuit 12, respectively. The output signal from the output terminal c of the circuit 12 is supplied to the adding circuit 16. By the switch circuit 12, the first
The signal of the field and the signal of the second field are switched so that one line can be shifted. Similarly, by the switch circuits 13, 14, 15 the first field and the second field
The fields are switched and one line shift is performed.

The motion detection circuit 107 forms a line shift control signal for controlling the switch circuits 12, 13, 14, and 15. 1
When line shifting is required, the input terminals b and output terminals c are connected in the switch circuits 12 to 15, and when one line shifting is unnecessary, the input terminal a and output terminals c are connected. The output signals of the switch circuits 12 and 13 are supplied to the adding circuit 16, and the output signals of the switch circuits 14 and 15 are supplied to the adding circuit 17.

The output signal of the adder circuit 16 is supplied to the frame memory 18,
The output signal of the adder circuit 17 is supplied to the frame memory 19. The time expansion operation is performed by the frame memories 18 and 19, and from the frame memory 18, Non-interlaced signal of the frame memory 19
From The non-interlaced signal of is obtained. The output signals of the frame memories 18 and 19 are supplied to the switch circuit 20. The switch circuit 20 is switched by a control signal from the terminal 21, and alternately selects the first field signal and the second field signal. This switch circuit 20
(625 lines / 50 fields) from the interlace signal is supplied to the D / A converter 22. Output terminal 23 of D / A converter 22
A PAL analog video signal can be obtained.

Similar to the above-mentioned luminance and signal components, the red color difference signal and the blue color difference signal are subjected to line number conversion and field number conversion processing. Then, although not shown, the PAL system color encoder is supplied with the luminance signal and the two color difference signals to obtain a PAL system composite color television signal.

FIG. 2 shows an example of the motion detection circuit 107. The digital video signal of the first field from the line number conversion circuit 3 is supplied to the input terminal 130. This digital video signal is the subtraction circuit 131, 132, 133, 134, 135, 136, 137, 13
8 and the representative point frame memory 139.

Motion detection is performed in a predetermined size (for example, x = −19 to +20, y = −4) in each of the x (sample) direction and the y (line) direction.
~ +4) as the unit of detection area, (x, y)
The origin of the coordinates is used as the representative point. Further, in order to improve the accuracy of motion detection, the detection areas are made to overlap each other, and are overlapped eightfold. Therefore, motion detection is performed in eight phases.

In the subtraction circuits 131 to 138, the difference value between the representative point data of the previous field and the pixel data of the current field is calculated, and the output signals of the subtraction circuits 131 to 138 are supplied to the summing circuits 141 to 148. The aggregating circuits 141 to 148 aggregate the absolute values of the difference values for one field, and the output signals of the aggregating circuits 141 to 148 are supplied to the adding circuit 149. The output signal of the adder circuit 149 is supplied to the minimum value detection circuit 150. In the minimum value detection circuit 150,
The minimum value (x ₀ , y ₀ ) is detected in the aggregated data of absolute values of field differences. This minimum value is supplied to the vector calculation circuit 151. Output terminal 15 of vector operation circuit 151
The motion vector is obtained in 2. The motion detection circuit 107 of FIG.
Detects the minimum value as in the motion detection circuit shown in FIG. The operation of the motion detection circuit 107 will be described with reference to FIG. As shown in FIG. 3A, one of the motion detection targets
The image of the field is equally divided into m in the horizontal direction and n in the vertical direction, so that (m × n) detection regions B0
0-Bnm is formed. One detection area has a size of (40 samples × 9 lines) as shown in FIG. 3B,
As described above, the position of each pixel in the detection area is defined by the x and y coordinates.

The digital video signal from the input terminal 130 is shown in FIG.
As shown in FIG. Starting from the pixel data of (x = -19, y = -4) in the detection area B00, the pixel data at the position of y = -4 in the detection areas B00 to B0m are sequentially supplied to the subtraction circuit 131. Next, y = −3 of the detection areas B00 to B0m, y = −2, y = −1, ...
The pixel data at the position of y = 4 are sequentially supplied to the subtraction circuit 131.

Then, the detection areas B10 to B arranged in the second row from the top in the horizontal direction
Similarly for 1 m, the pixel data is input to the subtraction circuit 131. Thereafter, pixel data are sequentially supplied to the subtraction circuit 131 in the same order, and finally (y = 4, x = 2 in the detection region Bnm.
The pixel data at the position 0) is supplied to the subtraction circuit 131.

On the other hand, the representative point data of the previous field from the representative point frame memory 139 is also supplied to the subtraction circuit 131 in the same order. In the case of representative point data, (40 × 9) samples included in the same detection area are the same data. Subtraction circuit 13
In 1, the absolute value of the difference between the pixel data of the detection area and the representative point data is obtained. The summing circuit 141 connected to the subtraction circuit 131 accumulates the absolute value of the difference for each position (x, y) in the detection area. The summing circuit 141 has a memory that is addressed corresponding to the position of the pixel in the detection area as shown in FIG. 3D.

By reading the contents of the corresponding address of this memory, adding it to the subtraction output, and writing the addition result to the same address again, the totaling is performed for each address. Regarding the pixel data of one field, the totaling circuit 141 has a detection area B00.
~ Aggregate difference data for Bnm is obtained. Further, as described above, since the detection areas are configured to overlap each other, eight sets of circuit configurations for calculating the one-field total difference data as in the above (subtraction circuits 131 to 138 and total circuits 141 to 148).
Used. Then, the adding circuit 149 further totalizes the total difference data obtained by the eight sets of circuit configurations.

The adder circuit 149 also has a memory that is addressed corresponding to each pixel in the detection area, similarly to the above-described add-on circuit 141,
Eight sets of aggregated difference data are aggregated. The total difference data obtained by the adder circuit 149 is one for each field. The minimum value detection circuit 150 detects the minimum value in the aggregated difference data obtained by the addition circuit 149. If the representative point moves by the vector amount of (x, y) within the time of one field, the aggregate value of (x, y) in the distribution of aggregate difference data becomes the minimum value. In FIG. 3E, regarding the aggregated difference data obtained by the adder circuit 149, y
It is shown for each value of.

The calculation of the motion vector performed by the vector calculation circuit 151 from the minimum value detected by the minimum value detection circuit 150 will be described with reference to FIGS. 4 and 5.

FIG. 3E shows an example of the difference data obtained from the adder circuit 149 as described above. FIG. 3E shows (x = −19 to +
20 shows the aggregate value f (x, y) of the difference data for the coordinates of 20, y = −4 to +4). As an example, as shown in FIG. 4, the minimum value detection circuit 150 [(x ₀ , y ₀ ) = (−
5,2)] minimum value is obtained. This minimum is the first
Since it is obtained only from the field signal, it has an accuracy of two lines. This minimum value is point A.

Next, a point (x ₀ , y ₀ −1) near the minimum value is set as a point B,
The point (x ₀ , y ₀ +1) is set as the point C. When the (y ± 1) plane (three surfaces in total) of the y plane including the minimum value is viewed from the x-axis direction, the three points A, B, and C are 2 as shown in FIG. It is assumed to be on the next curve [f (−5, y) = ay ² + by + c]. The minimum point (yc = -b / 2a) of this curve is obtained by solving simultaneous equations. The minimum point yc is obtained by the following formula.

However, A = (x ₀ , y _A ), B = (x ₀ , y _B ), C = (x ₀ , y _C ).

Since the accuracy in the y direction is 1 line or less in principle, the final motion vector (x ₀ , yc) from the vector calculation circuit 151.
The accuracy of is 1 sample in the x direction and a value determined by the accuracy of the vector operation circuit 151 in the y direction. Actually, the image shift circuits 8 to 11 are multiplied by the coefficient corresponding to the frame position.
In the stage of being supplied to, the line precision is set to 2 lines, and fractions less than 2 lines are rounded off to 1 line or 2 lines and used as line shift control signals for the switch circuits 12, 13, 14, 15.

The vector calculation circuit 151 is not limited to hardware having a discrete configuration, and may be realized by a microcomputer.

〔The invention's effect〕

According to the present invention, when the motion correction is performed in the conversion of the number of fields when converting the HD system to the PAL system, the accuracy of the motion detection in the vertical direction can be set to one line accuracy. According to the present invention, the first field signal and the second field signal are simultaneously formed from the HD system digital video signal, and the motion detection is performed using the signal of one field. Therefore, both the first field and the second field are detected. There is an advantage that the configuration of the motion detection circuit is not complicated as compared with the case where the motion detection is performed using the signal of.

[Brief description of drawings]

FIG. 1 is a block diagram of a system converter using a motion detection circuit according to the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIGS. 3, 4, and 5 show differential data. FIG. 6 is a block diagram of an example of a conventional system conversion device, and FIG. 7 is formed of a part of the scanning line structure and the HD system. FIG. 8 is a schematic diagram showing a part of the scanning line structure of each of the first field and the second field, FIG. 8 is a schematic diagram used for explaining the motion detection region, and FIG. 9 is an example of a conventional motion detection circuit. Block diagram, Fig. 10 is a schematic diagram used to explain motion compensation operation,
FIG. 11 is a block diagram of another example of a conventional method conversion device,
FIG. 12 is a block diagram of another example of the conventional motion detection circuit. Description of main symbols in the drawing 1: HD format video signal input terminal, 3, 4: Line number conversion circuit, 8, 9, 10, 11: Image shift circuit, 12, 13, 14, 15: Switch circuit, 23: PAL system video signal output terminal, 107: motion detection circuit, 131 to 138: subtraction circuit, 141 to 148: aggregation circuit, 150:
Minimum value detection circuit, 151: Vector operation circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yutaka Tanaka, 1-10-11 Kinuta, Setagaya-ku, Tokyo, Japan Broadcasting Technology Laboratory (72) Inventor Toshiro Omura 1-1-10 Kinuta, Setagaya-ku, Tokyo No. 72 Broadcasting Technology Institute of Japan Broadcasting Corporation (72) Inventor Taiichirou Kurita 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Broadcasting Technology Laboratory of Japan Broadcasting Association (72) Taiji Nishizawa Kinuta 1 Setagaya-ku, Tokyo Broadcasting Technical Research Institute, Japan Broadcasting Corporation (72) Inventor Yuichi Ninomiya 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Broadcasting Technical Research Institute, Japan Broadcasting Association

Claims (1)

[Claims] 1. A first field and a second field of a normal television signal are formed from a signal of one field of a high definition television signal, and the first field and the second field are formed.
In a device for detecting a motion of an image from a signal of one of the fields, a representative point of a detection area formed by a plurality of pixel data in the one field and each pixel data in the detection area A circuit that calculates the difference value of, and detects the minimum value in the aggregated difference data in which the absolute values of the difference values are aggregated, the minimum value, and the distribution of the aggregated difference data, in the vertical direction of the minimum value. And a circuit for calculating a local minimum value of a quadratic curve formed from at least two neighboring data and forming a vertical component of the image motion detection signal. apparatus.