JPH0779422B2 - Image scaling device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a grayscale halftone image such as black and white or color photograph read by a scanner or the like.
The present invention relates to an image enlarging / reducing device for accurately adjusting a desired size and enlarging / reducing an image with less distortion.

2. Description of the Related Art Conventionally, as a method of obtaining an image of a desired output size, there are a method of reading only an output size from the beginning by a scanner and a method of adjusting the size of an already read image to a desired size by enlarging / reducing processing. .

The former method is possible when the output size is fixed in advance, and the latter method must be used when the output size is not fixed or when an image already prepared for another purpose is edited.

The method of reading an image of the desired output size with a scanner limits the reading pitch, so in some cases the reading range may be exceeded or the specified reading range may not be reached, resulting in a finer reading pitch. Need to be designed. On the other hand, the process of editing the image to adjust the size basically has the same drawback, but by partially using the image data before and after the image, the pixel and the pixel It is relatively easy to compensate for new pixels in the meantime or to thin out pixels to match the desired output size.

FIG. 10 is an explanatory diagram of a conventional technique. In FIG.
(A) shows a state in which the pixel data to be processed are arranged, and the vertical axis shows the gray level of each pixel. The figure (b) shows the conventional example when the data of the figure (a) is enlarged 5/3 times, and the figure (c) is the case where the data of the figure (a) is reduced 3/5 times. The conventional example of is shown. As can be seen from this example, at first glance, the result of the enlargement / reduction is discontinuous, and a partial image distortion occurs. In the same figure (b), new pavement data is generated between pixels by the enlargement processing, but as described above, it is a partially discontinuous image. On the other hand, FIG. 7C shows that pixel data is thinned out at a rate of 2/5 by the 3/5 reduction processing. In this case, only the thinning is performed and the influence of the surrounding pixels is not given, but the correction is given by the influence of the surrounding pixels for the sake of accuracy (sometimes called interpolation like the case of enlargement). There is also an example.

FIG. 11 is an explanatory diagram of a conventional example in which a weighted average is taken in order to accurately interpolate in the case of 5/3 magnification processing. In the figure, (a) shows a state in which image data to be processed are arranged, (b) is a timing pulse showing a pixel corresponding position at 5/3 times magnification, and (c) is image data after enlargement. Shows how to arrange. The weighted average in this conventional example will be described by taking the pixels g ₁ and g ₂ in FIG. Timing pulse position signal O in FIG.
Are at positions separated from the image data g ₁ and g ₂ by m ₁ and n _1, respectively, and the timing pulse position number 1 is
It is at a position separated from the image data g ₁ and g ₂ by m ₂ and n ₂ , respectively. As a result, the interpolation data h ₀ and h _{1 at} each timing pulse position are h ₀ = (g ₁ × n ₁ + g ₂ × m ₁ ) / (m ₁ + n ₁ ) h ₁ = (g ₁ × n ₂ + g _{It is} calculated by ₂ × m ₂ ) / (m ₂ + n ₂ ). FIG. 7C shows the result of linear interpolation, magnifying 5/3 times. According to this method, it is possible to calculate with high accuracy, but it is necessary to carry out multiplication twice and division once, and when using hardware, the cost is high and the circuit is complicated.

Problems to be Solved by the Invention As described above with reference to the conventional example, when pixels are interpolated and scaled by a method such as a weighted average, the accuracy is good, but the cost is increased due to hardware implementation. Also, it has a drawback that the circuit becomes complicated.

As described above, most of the interpolation methods are generally linear interpolation. For example, when it is desired to interpolate between pixels with an arbitrary function, the hardware becomes more complicated, and it is difficult to realize an inexpensive circuit.

The present invention eliminates these drawbacks and provides an image enlarging / reducing device which has a simple circuit structure and can perform pixel interpolation by an arbitrary function.

Means for Solving the Problems The present invention relates to each of the input pixels g _n and the sequentially input neighboring pixels g _{n + 1} with respect to the grayscale image data continuously input at a constant scanning pitch. A subtraction circuit that obtains a difference Δg by subtracting the other pixel from one of the pixels by using the pixel of, and divides the input pixel g _n and the neighboring pixel g _{n + 1} by a constant integer γ. Each position (i) (where i is 0- (γ-
Interpolation value in (1) integer value) is calculated by linear interpolation formula (Δg) · (i /
First storage means for pre-calculating and storing difference interpolation grayscale data calculated by γ), and enlargement / reduction of an image determined by an enlargement ratio β / α times (where α and β are integers) The corresponding image position by the difference Δg
Which γ-divided position (j) (where j = 0 to (γ-
1) It is the closest to the integer value) j = INT {k · (α · γ) / β} MDD γ (where INT is an operation that outputs an integer value, MDD is an operation that calculates the remainder of division, k Is the pixel value from the reference point of the enlarged / reduced image) and stores the address value (j) in advance, and the difference Δg and the output value (j ) As an address of the first storage means, the differential interpolation grayscale data is read from the first storage means, and the input pixel
g _n and an addition means for adding to _one of the neighboring pixels g _{n + 1} .

Operation As is apparent from the above-described configuration, the present invention is configured to first perform the interpolation calculation by the table reference with the difference value of the input data and add the reference value to the interpolation output to obtain the final interpolation value. According to such a configuration, if the input image data is used as it is for the address of the interpolation value memory, a bit width twice as large as the input image data (for example, 16 bits when the input bits are 8 bits) is required. , In the present invention, 1
It only increases the bit (eg 8 + 1 = 9 bits). Therefore, the size of the interpolation value memory is significantly reduced. Further, by rewriting the contents of the interpolated value address memory according to the enlargement / reduction ratio, enlargement / reduction of arbitrary magnification can be performed. Further, by calculating the interpolation values in advance and forming a table, it is possible to realize the enlargement / reduction of the image at a high speed with a simple circuit configuration using a table reference and an adder.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an image enlarging / reducing device according to an embodiment of the present invention, and is a specific explanatory diagram of FIG.

First, FIG. 2 (a) is input image data (here, g ₁ = 95, g ₂ = 5, g ₃ = 17, g ₄ = 68), and FIG. 2 (b) is divided. Incremental data δ for interpolation at each division position i = 0 to 3 in the case of the number γ = 4, and FIG. 2 (c) shows output data subjected to enlargement interpolation.

Next, referring to FIG. 1, when a series of image data is input, linear interpolation will be taken as an example for description. Input line in the figure
Enter the pixel g ₁ → g ₂ → g ₃ that indicates yourself in 101 and input line 1
Pixels g ₂ → g ₃ → g ₄ in the vicinity of 02 are synchronously input respectively, and the output line
The pixel data h subjected to the expansion interpolation as shown in the equation (1) is output to 103.

h = g _n + δ (1) δ = INT {((g _{n + 1} −g _n ) / γ) × i} (2) (where INT {} is an integer obtained by rounding Note that when the image scaling ratio β / α is set to 5/3 and the number of divisions γ (integer) between pixels is 4, the integer i indicating the read address of the interpolation data is 0 ≦ i. <Γ, that is, i
= 0 indicates a value in the range of 0 to 3.

Therefore, the interpolation increment data corresponding to i = 0 to 3 in g _{1 to} g ₄ are the values [0, -23, -45, -68, 0, 3, 6, 9, 0, 13, 2
6, 38, 0 ...].

First, in advance, in random access memory (RAM) 104,
The reading address j of the interpolation data described above is set from the microcomputer or the like via the data input line 105. Here, the read address is j =
It is in the range of 0 to 3, and is, for example, an integer determined by the following formula (3).

j = INT {k × (α × γ) / β} MDD γ (3) (where INT {} indicates a rounded integer, INT {} MD
Dγ indicates the remainder of INT {} / γ, and k indicates the pixel position from the reference point of the enlarged / reduced image. ) In this case, j = 0, 2, 1, 3, 2 is repeated.

Next, the pixel data g _n input to the input lines 101 and 102,
g _{n + 1} enters the subtractor 106 and calculates Δg = g _{n + 1} −g _n (−255
(Range of up to +255), and output to the output line 107. on the other hand,
According to the value of the counter 108 that counts in synchronization with the timing at which the interpolation pixel is output, the value of j from the RAM 104 (that is, j
= 0,2,1,3,2) are read out one after another, connected to the above-mentioned Δg, and inputted as the read-out address of the RAM 109.
As a result, the read pixel interpolation data is j = 0,
Incremental data for interpolation [0, -45, 3, 6, 13] are sequentially read out corresponding to each of 2, 1, 3, 2 and input to the adder 110. On the other hand, in synchronization with this interpolation increment data, the pixel data of itself (g ₁ = 95, g ₂ = 5, g ₃ = 17, g ₄ = 68) input from the input line 101 is also added by the adder 11
When it is input to 0, the addition operation is performed and the result is output to the output line 103.

Therefore, the expanded interpolation output data to the output line 103 is as shown in the equation (4).

[95,95,5,5,17] + [0, -45,3,9,13] = [95,50,8,14,30] (4) The input line 111 is for each circuit. It is a line for inputting a timing control signal.

In the above, the case where the division number γ between pixels is 4 in the enlargement by linear interpolation of 5/3 has been specifically described, but it goes without saying that the larger the division number γ, the higher the accuracy. The RAM 104 in FIG. 1 may be a ROM, and the ROM 109 may be a RAM.

Next, another embodiment which is not linear interpolation will be described.

FIG. 3 shows a case in which a grayscale distribution function f (g) that is uniquely determined by an arbitrary pixel grayscale level is used, and an interpolation function that combines two distribution functions of its own pixel and neighboring pixels is used. Showing things. In the same figure (a), each of the density distribution functions f (g ₁ ), f (g ₂ ), f (g ₃ ) ... Determining according to the pixel density level (g ₁ , g ₂ , g ₃ ) is shown by a dotted line. Also, FIG. 6B shows the synthesized grayscale distribution functions f (g ₁ ) + f (g ₂ ), f (g ₂ ) + f (g ₃ ), ... The data that is enlarged and interpolated under the same condition used in the linear interpolation of is shown by a thick solid line. In this way, by setting the interpolation increment data by the arbitrary interpolation function, the expansion interpolation (or the reduction interpolation) by the arbitrary function can be realized.

Next, an embodiment in the case of reduction interpolation will be described with reference to FIG. In FIG. 4, (a) shows the input pixel data sequence, and the vertical axis shows the gray level of each pixel. FIG. 11B shows the result when reduction interpolation is performed by 3/5 times. The reduction interpolation can be performed in the same manner as the enlargement interpolation described above, but as can be seen from FIG. 4 (b),
For example, in the input pixel data g _{2 to} g _3, etc., a portion in which no pixel data is generated by interpolation is generated. This is peculiar to reduction, and considering the case where the reduced interpolation value is output at the same clock as the input pixel clock, it can be achieved by selecting only the input pixel data used for reduction interpolation as the input, or the output result. It can also be achieved by discarding unnecessary output from the interpolation data memory. For example, in the embodiment of FIG. 1, in addition to the interpolation data read address, selection data (0, 1) written at the same position is newly provided to select input or output. In FIG. 4, the process of performing 3/5 reduction will be described below. The interpolation incremental data set in advance is obtained by the equations (1) and (2) as in the case of the expanded interpolation. Further, from the equation (3), the read address i of the interpolation data becomes [0, 3, 1] when the division number γ = 4, and this is repeated. However, as already mentioned, there is a part that is not interpolated between pixels, and if there is no new pixel generated between the pixel of its own and the next neighboring pixel, it is set to “0”. Asks for selection data such as "1". Therefore, for example, the selection data ε is set to ₁ , ₁ , ₀ , ₁ , ₀ corresponding to the input data g ₀ , g ₁ , g ₂ , g ₃ , g ₄ ...
Set as follows. Accordingly, the correspondence between the read address j of the interpolation data, the input data g _n , and the selection data ε is as follows.

Input data g _n : g ₀ , g ₁ , g ₂ , g ₃ , g ₄ selection data ε: 1, 1, 0, 1, 0 interpolation value address memory value j: 0, 3, × 1, × ( If the selection data is 0, the output interpolation data is not required at the input pixel timing and therefore the output data is not output or is discarded. It is shown that even such values do not affect the operation result.) In this way, reduction interpolation of an image can be realized.

Next, in the case of a two-dimensional image, another embodiment of the present invention will be described with reference to FIGS.

FIG. 5 shows a combination of the two embodiments of FIG. In the figure, two dotted lines (501 and 50)
2) corresponds to the embodiment of FIG. 1, and latches 503, 504505, 506) for temporarily holding data are provided in front of each of the enlargement interpolation (or reduction interpolation) units. In FIG.
Enlargement interpolation in the sub-scanning direction in the two-dimensional image is performed in the former stage, and enlargement interpolation in the main scanning direction is performed in the latter stage in response to the result of the former stage. In the figure, input line 507 is input with its own line data, and input line 508 is input with adjacent line data. The data of these two lines are held in the latches 503 and 504 while synchronizing with the timing signal from the interpolation control circuit 509, and are sequentially input to the expansion interpolator 501 at the preceding stage. The output data from the expansion interpolator 501 at the previous stage is
The image data is sent to the subsequent stage as a series of image data that has been enlarged and interpolated for one line. The interpolation data for one line is first held in the latch 505 and then transferred to the latch 506 at the next timing. These timing signals are generated from the interpolation control circuit 509. These two latches 505 and 506
Is input to the expansion interpolator 502 in the subsequent stage. In the expansion interpolator 502 in the subsequent stage, g _n is input from the latch 506 and g _{n + 1} is input from the latch 505 to perform the expansion interpolation represented by the equations (1) and (2).

FIG. 6 is an example in which the embodiment of FIG. 5 is applied more specifically. When a series of image data is sequentially input to the input line 601, the line data is sequentially written in the line buffers 602 to 604. First, data for two lines is sequentially written in the line buffers 602 and 603, and thereafter, each time the processing is completed one after another, the data is written in the remaining line buffers. Then, read the data from the line buffer for two lines of them,
Select your own line data with the selector 605,
The line data in the vicinity is selected by the selector 606. Next, the selected line data is input to the sub-scanning line data interpolating unit 607, and subsequently, in each of the main scanning pixel data interpolating unit 608, the enlarged (reduced) interpolation is performed to obtain the final interpolated line data. , Line buffers 610 and 6
Alternately written to 11.

Finally, the final interpolation data is read from the line buffer opposite to the line buffer written in the line buffers 610 and 611, and is output to the output line 613 via the selector 612. The input line buffer control circuit 614 includes line buffers 602 to 604 and a selector 605.
Generates 606 control signals. The output line buffer control circuit 615 also generates control signals for the line buffers 610 to 611 and the selector 612. Then, the interpolation control circuit 616 receives the interpolation data from the microcomputer or the like via the input line 616, and sets and controls each interpolation unit.

By the way, in the configuration of FIG. 6, sub-scanning interpolation is performed in the preceding stage and main-scanning interpolation is performed in the subsequent stage, but in FIG. 7, conversely, main-scanning is performed in the preceding stage and sub-scanning interpolation is performed in the succeeding stage. A configuration is shown in which the order is changed so as to be carried out. Therefore, the description of FIG. 7 is the same as the description of FIG. 6 and will be omitted.

Next, FIG. 8 shows an example in which the image data arranged two-dimensionally in FIGS. 6 and 7 is scaled up and down. In FIG. 8, (a) shows a state in which the image data are arranged two-dimensionally, and (b) shows the data in the pixels surrounded by circles in (a). The numbers in parentheses in FIG. 7B indicate the gray level of the pixel. For the data in the portion shown in FIG. 8, main scanning,
That is, FIG. 9 shows the result when the number of divisions is 8 in the X direction and 3/5 times reduction interpolation is performed, and the sub-scanning is performed, that is, the number of divisions is 4 and 5/3 times enlargement interpolation is performed in the Y direction. Shown in.

The case where the number of divisions is 4 has already been described above with an example of 5/3 times expansion and contraction. 8 and 9 show an example in which the vertical and horizontal magnifications and the number of divisions are set independently. As a result, an image which is vertically (Y) enlarged and horizontally (X) reduced is obtained as shown in FIG.

EFFECTS OF THE INVENTION As described in the above embodiments, according to the present invention, when a new pixel is generated by interpolation between existing pixels, a high-speed and high-accuracy interpolation function can be performed without complicated calculation. In addition to the feature that it can be set, the circuit is simplified, and as a result, it is possible to inexpensively realize hardware.

[Brief description of drawings]

FIG. 1 is a block connection diagram of an image enlarging / reducing apparatus according to an embodiment of the present invention, FIG. 2 is a conceptual diagram in the case of concrete linear interpolation in the embodiment of FIG. 1, and FIG. FIG. 4 is a conceptual diagram in which pixels are interpolated by an arbitrary function in another embodiment, FIG. 4 is a conceptual diagram in the case of the same reduced interpolation, and FIG. 5 is a block showing an embodiment in which two embodiments of FIG. 1 are combined. Wiring diagrams, FIGS. 6 and 7 are block wiring diagrams of the same device for performing enlargement (reduction) interpolation of two-dimensionally arranged image data in another embodiment of the present invention, and FIG. 8 is FIG. 6 or FIG. 7 is a concrete conceptual diagram in FIG. 7, FIG. 9 is a conceptual diagram showing the result of input / output of FIG. 8 and scaling processing, FIG. 10, FIG.
FIG. 11 is a conceptual diagram showing a conventional image scaling method. 104 ... RAM, 106 ... Subtractor, 108 ... Counter, 109 ...
… ROM, 110… Adder.

Claims (1)

[Claims] 1. For grayscale image data continuously input at a constant scanning pitch, each pixel of each input pixel g _n and a neighboring pixel g _{n + 1} sequentially input is used, and one of A subtraction circuit that subtracts the other of the pixels from the pixel to obtain a difference Δg, and each position (i) (provided that the input pixel g _n and the neighboring pixel g _{n + 1} are divided by a fixed integer γ. , I is 0- (γ-
Interpolation value in (1) integer value) is calculated by linear interpolation formula (Δg) · (i /
First storage means for pre-calculating and storing difference interpolation grayscale data calculated by γ), and enlargement / reduction of an image determined by an enlargement ratio β / α times (where α and β are integers) The corresponding image position by the difference Δg
Which γ-divided position (j) (where j = 0 to (γ-
1) It is the closest to the integer value) j = INT {k · (α · γ) / β} MDD γ (where INT is an operation that outputs an integer value, MDD is an operation that calculates the remainder of division, k Is the pixel value from the reference point of the enlarged / reduced image) and stores the address value (j) in advance, and the difference Δg and the output value (j ) As an address of the first storage means, the differential interpolation grayscale data is read from the first storage means, and the input pixel
An image enlarging / reducing device, comprising g _n and an adding means for adding to _one of the neighboring pixels g _{n + 1} .