JPH0779235B2 - Signal generator and output signal setting method thereof - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention is capable of operating in the GHz range in signal generators, particularly in either continuous wave (CW) mode or swept frequency mode, and is typically a transmission / reflection analyzer. Relates to a stabilized signal generator used in.

[Prior art]

A variety of source oscillators are available to generate ultra-high frequency electrical signals, all with more or less drift induced by ambient changes such as temperature, power supply variations and changes in electrical components associated with sources of vibration. receive. Typical source oscillators utilized in ultra high frequency applications utilize YIG oscillators or varactor tuned oscillators.

Techniques for improving frequency stabilization can be divided into the following two types. (A) Techniques for non-fixed sources (b) Techniques for fixed (normally phase-locked) sources In the case of non-fixed systems, open-loop type correction is usually incorporated into some form of linearization circuit. Techniques of this type range from simple diode shaping circuits common in varactor tuning circuits to more complex RPOM data corrections incorporated into microprocessor control signal generators. Since the circuit is open loop, no correction is possible for frequency shifts or mismatch errors over time.

A correction signal may be generated by using a temperature sensitive thermistor to help correct the source frequency for temperature drift. However, in all other respects, the device is essentially open loop.

In the case of a fixed system, the signal is derived from a high frequency source using the reduced conversion principle so that a signal with a lower frequency than the source is obtained, and this reduced conversion signal is then fed to a reference signal, usually derived from a crystal controlled oscillator. Be compared. The comparison is performed by a phase detector, the output of which is a voltage proportional to the phase error of the two signals. The correction voltage is provided to the tuning portion of the high frequency source oscillator to correct the frequency shift and to achieve a significantly higher level of accuracy due to this property of the system.

An open loop system normally sends the generated signal to 2000MH
Closed-loop phase-locking systems have a precision of allowing signals in the vicinity of z to be within +/- 5 MHz.
Better accuracy than 1KHz can be achieved at 00MHz.

As expected, closed loop phase locked systems are more complex and more costly than the relatively simpler open loop unlocked systems.

Both types of sources can be configured to produce a CW output or a swept output.

In the case of an open loop source, frequency sweep is achieved by adjusting the frequency determining component to the start frequency and then supplying an increasing (or decreasing) tuning signal (usually a variable voltage) to the tuning port of the vibrator. . This may be accomplished by generating a ramp voltage, which may be derived using analog circuitry or from a digital signal using a digital-to-analog converter (DAC). When the latter approach is used, a microprocessor is conventionally employed to control the ramp voltage generation. Whatever form of ramp signal is used (analogically or digitally induced), the oscillator has a frequency variation due mostly to the nonlinearity of the tuning portion of the oscillator and temperature variations. Inaccurate to the extent that

For phase locked systems, two approaches are possible.

In one arrangement, the start frequency at the beginning of each sweep is phase locked using a phase detector to correlate the required output frequency with the reference frequency.
The source is tilted in an open loop manner, and the sweep range is achieved as in a normal open loop.
However, the accuracy is greater because the frequency at the start of each sweep is phase locked.

Instead, not only the start frequency is phase locked, but the frequency is digitally increased (or decreased) by a series of steps, phase locked to each frequency step,
After phase lock is achieved, simply move on to the next frequency step for a fully synthesized sweep.

The first of these two schemes provides a fast sweep update time, but relatively poor frequency accuracy over the swept band, while the second one has a fairly high level during each sweep. Provides frequency accuracy but has a slower sweep update time.

With any of the phase-locked ones, the frequency drift due to time, temperature or output mismatch will be corrected instantaneously, or at least before each sweep. No such correction is possible in an open loop swept frequency generator.

Various attempts have been made to improve the accuracy of open loop systems, since those of phase locked systems are quite expensive. One approach has been to generate so-called "BIRDI markers". This provided a visual display associated with the signal generator, on which the electrically generated marker signal could be displayed.

This type of system operates by generating from the crystal control signal a comb train (harmonic train) of so-called frequencies, each of which is a multiple of the frequency of the original crystal control signal. The frequency generator output signal is sampled and the sampled signal is mixed with the "comb-row" signal. A beat or "BIRDI" is generated between the components of the "comb-row" signal at frequencies that are close to and closer to the frequency of the output signal. Using a low pass filter, the beat (or "BIRDI") signal can be separated from the high frequency signal and amplified for display on a CRT or similar display device. Frequency correction is accomplished by manually adjusting the master oscillator to correct any frequency drift. Frequency drift can be seen as a shift in the "BIRDI" display on the screen.

Systems utilizing such displays have the form of a closed loop (when the user is considered), but the accuracy achieved is much lower than that of a phase locked loop system, and this type of system Apart from the time delay inherent in V., there are other disadvantages with conventional open loop systems. That is, (a) As the amplitude of the output signal decreases, the amplitude of the beat signal also decreases, and eventually the beat signal may be lost in the electrical noise in the system. Visual correction at this stage becomes very difficult.

(B) If a very frequency-selective component with a very steep response curve is tested, the beat signal may be lost with a steep component characteristic, and the frequency correction is still very difficult.

On the other hand, the generation of the beat signal from the crystal control source represents a simple way to generate the feedback signal, and therefore the object of the present invention is simpler and cheaper than the conventional phase locked loop system. The purpose of the present invention is to provide a closed loop system which derives feedback information from a beat signal for frequency control.

[Outline of Invention]

According to the broadest aspect of the present invention, hundreds to thousands
Provides an output frequency of F MHz in the range extending to MHz, with coarse and fine frequency control elements, fine control, N MHz
In a method of setting a signal generator capable of producing a linear change in output frequency for a corresponding change in a parameter of an electrical signal supplied to said element over only a small range of L MH within N MHz of MHz
Combining with a multi-component reference signal containing at least a component having a frequency of z, the frequency control signal supplied to the device is
Adjusting to produce an output signal having a frequency in Hz, the fine frequency control element until a corresponding signal is detected which indicates a one-to-one relationship between the output signal and said reference signal (or a component thereof). Adjusting Memorizing the value of the frequency control signal from which the corresponding signal is detected, and using an algorithm or lookup table, required by the fine frequency control element to shift the frequency of the device by (F-L) MHz. The frequency control signal obtained by determining the value of the correction signal and adding the correction signal to the stored signal, i.e. adding the correction signal to the stored frequency control signal associated with said corresponding signal. F MHz by using as a control signal to the device
A method for setting a signal generator is provided, which comprises:

Typically, the calibration procedure and frequency shifting, zero point detection, signal storage and addition are done under the control of the microprocessor.

According to another aspect of the invention, the output frequency is frequency F
A signal generator set to 1. having an output that produces a radio frequency signal when operating,
In addition to the large band frequency control element, it has a small band control element, by which the oscillation frequency can be changed over a small frequency band by linearly changing the parameters of the electrical signal supplied thereto. A master oscillator capable of: 2. a controller configured to generate an electrical signal for controlling the frequency of the master oscillator from the input information; 3. a means for deriving a sample signal from the output of the master oscillator; A stabilized fixed frequency oscillation signal source for generating a reference signal F (ref), and 5. a harmonic spectrum of a signal having at least one component in the small frequency band from the reference signal F (ref), that is, a comb shape Row F (ref); 2F (ref); 3F (ref) ... nF (ref)
A circuit for generating (referred to as a harmonic spectrum signal), 6. combining the sampled signal with the harmonic spectrum signal, between the beat signal, ie especially the frequency of the sample signal and a component of said harmonic spectrum signal. A mixing or sampling circuit that produces a signal having a frequency that is an arithmetic difference; and 7. a beat signal detection circuit that responds to the output of the mixing circuit to identify that a beat signal pulse is being generated. For the purpose of frequency calibration, upon detection of the selected beat signal (caused by the interaction of the main oscillator output signal and one component NF (ref) of the harmonic spectrum signal) of the frequency supplied to the main oscillator The value of the decision signal is calculated in the calculation of the new value of the control signal for the master oscillator in order to obtain an oscillation frequency equal to (NF (ref) + X) Until it is adopted (where X is N.
F (ref) and the required frequency shift between the desired frequency F), said controller being programmed to change the frequency control signal supplied to the master oscillator. Will be provided.

The associated beat signal can be selected from a number of sum and difference signals by frequency selective separation using a low pass filter.

Normally, a crystal controlled oscillator is set to operate at a frequency of about 25MHz if the master oscillator operates at frequencies in the range up to 1MHz.

According to another aspect of the present invention, there is provided a method of controlling an oscillation frequency of a master oscillator in a signal generator having a linear frequency control element having a limited frequency sweep capability, which comprises: 1. Generating a frequency control signal that is generated in a random manner, 2. combining a sample of the master oscillator output signal with a reference signal having one component within said limited sweep frequency of the master oscillator, and 3. Adjust the value of the frequency control signal until the beat signal between the reference signal components is detected, and then change the value of the frequency control signal from the value corresponding to the calibration to the frequency of the main oscillator with respect to the value of the frequency control signal. Oscillation frequency control with steps to adjust to a new value calculated using an algorithm or look-up table describing the response, thus shifting the master oscillator output to the desired frequency A method is provided.

After the calibration procedure has been performed, the frequency of the master oscillator is correct and thereafter remains in that state depending on the quality of the open loop correction incorporated into the signal generator to compensate for thermal drift etc. Let's see.

When the master oscillator is required to sweep a frequency range, the method of the present invention preferably comprises the following steps. That is, (1) using the corrected control signal as a starting point, changing the control signal calculated according to an algorithm that combines the oscillation frequency with the value of the control signal, and (2) reaching the final target frequency of the sweep. The output of the signal generator is suppressed, and (3) thereafter, the correction process including the above method is repeated until the beat signal is detected, and then the sweep process can be restarted. including.

The reference signal can usually be a so-called harmonic spectral signal derived from a crystal controlled source by a step-off diode.

It will be appreciated that for this type of correction, the sweep frequency linearity is determined, among other things, by the accuracy of the algorithm that couples the oscillator frequency to the control signal.

If the algorithm is an incomplete description of the frequency-to-control signal relationship, or if a particular master oscillator is relatively linear and the algorithm is a logical description of the performance of a more linear one of this kind, then The sweeps taken are not particularly linear.

If the sweep time is not tolerated, the preferred method according to the invention comprises the following steps. That is, 1. Identify a series of key frequencies throughout the range to be swept, start at the lowest or highest, and start the master oscillator until the beat signal is generated by the interaction of the master oscillator output signal with the reference signal component. 2. Compensating the supplied control signal, 2. Compensating the compensated control signal according to a known algorithm for generating a control signal to obtain a frequency between a first frequency and a next target frequency. Changing the control signal, 3. When the next target frequency is approached, repeat the calibration process for the oscillator control signal and then continue to change the oscillator frequency to the next target frequency through the next frequency range. including.

Thus, the frequency of the master oscillator is corrected over each range in each of a series of steps, and if high accuracy is required, a correspondingly large number of steps are employed.

Usually, a digital signal is generated by a microprocessor and a digital-to-analog converter (DAC) serves to convert the digital signal into a voltage or current, which can be used to control the frequency of the master oscillator.

It is very convenient to select an appropriate beat signal from DC to f.
Is achieved using a Roper filter set which transmits signals in the range (where f may be, for example, in the range 500 KHz to 5 MHz).

Considering the influence of the attenuation of the low-pass filter, it is preferable to provide a signal amplification and pulse adjustment circuit after the low-pass filter and before the microprocessor.

Usually, the precision fixed frequency oscillator is a crystal controlled oscillator.

A high level of accuracy is obtained by determining the exact center position of the selected beat signal pulse from the width of the beat signal pulse. Thus, this central position corresponds to the zero frequency or DC content in the beat signal. Therefore, the microprocessor is preferably programmed to seek the center position of the beat signal pulse detected thereby and use the determined center phase of the pulse as a target.

If the stored information is in digital form and the modification to this information is in the form of a digital error signal generated by the microprocessor, both the stored information and the error signal can be converted to an analog signal, otherwise Make them easier to add than if they were.

In swept mode, that is, when the generator produces a signal that changes in frequency over time from a first frequency (f1) to a second frequency (f2) that defines a sweep band, two things of information are Conveniently it is loaded into the memory associated with the processor.

1. Sweep width (ie F2-F1) 2. Center of sweep range The process of finding the starting point of the sweep range includes the following steps.

1. A digital-to-analog converter, which is initialized by a microprocessor, theoretically calculates a control signal to produce one or more analog signals that should cause the master oscillator to generate the start frequency,
Program the microprocessor from the sweep width and center information.

2. At the same time, set the error DAC, whose output is combined with the first mentioned DAC means, to the mid range.

3. The error signal is corrected by the microprocessor so that the output from the error DAC is changed until a beat or difference signal is detected.

4. The total correction value for the value of the error signal needed to produce the beat signal pulse is stored in the buffer memory for later reference.

5. Using the value stored in the buffer as the start point, the control signal supplied to the main oscillator is adjusted according to the frequency / control signal characteristics of the main oscillator, and the main frequency corresponding to the sweep start frequency is adjusted. Obtain the new operating frequency of the oscillator.

6. Sweep by microprocessor to produce varying output signal. It is fed to the frequency control element of the master oscillator to cause the desired sweep of f1 to f2 at the output frequency of the master oscillator.

At the end of each sweep, the microprocessor returns to the search routine to look for the beat signal to recalibrate the oscillator, so that the generator is calibrated at the start of each sweep.

Preferably, the master oscillator comprises two frequency control elements, a first one that causes a large change in frequency and a second one that causes a smaller change in frequency, and such as a microprocessor drive controller. The controller is configured to generate a first control signal for an input of the first control element and a second control signal for an input of the second control element. If an error signal is generated by the control device, this signal is added to the value of the second control signal,
Will be subtracted.

For high frequency applications, the master oscillator is preferably a YIG oscillator with a master tuning coil for wide range tuning and a small FM coil for fine range tuning.

Alternatively, a palactor tuned oscillator can be used.

[Explanation of Examples]

Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 does not exemplify the embodiment of the present invention, but shows how the temperature correction is applied to an oscillator. Corrections of this nature can be included in embodiments of the invention.

In FIG. 1, a YIG oscillator 10 has a coarse equivalent port 12 associated with the main tuning coil and a fine tuning port 14 associated with the FM coil. Signal amplifiers 16 and 18 serve to provide control signals to ports 12 and 14, respectively. The coarse frequency adjustment, usually in the form of a potentiometer, is not shown, but the fine frequency drive input is shown as being derived from amplifier 20. Thus, the input of the amplifier comprises a temperature compensating resistor or thermistor 22.
By positioning a temperature compensation resistor or thermistor to sense changes in the temperature of oscillator 10, a compensation error signal can be provided to input 14 via amplifiers 20 and 18 to compensate for temperature drift.

The output frequency on line 24 is better regulated than without temperature compensation.

FIG. 2 illustrates a more complex closed loop phase locked oscillator. Similar reference numerals have been used to indicate parts in common with FIG.

The main difference between the two circuits is that a closed loop is formed between the output 24 and the input of the fine frequency drive amplifier 18 at 26. This loop detects low frequency signals in the phase detector 30
It is closed by a programmable divider 28 which feeds to. Thus, the phase detector 30 is normally supplied with a reference signal 3 from a crystal controlled oscillator.

If there is a small change in the frequency between the output control frequency on line 24 and the crystal control frequency on input 32, this will appear as a phase difference and the error signal generated by the phase detector will cause amplifier 18 to It is supplied to the fine tuning port 14 via. Very high levels of accuracy can be obtained with this type of circuit.

Since this kind of circuit is complex and costly, especially at very high frequencies, there is a role of an alternative approach of the invention.

FIG. 3 is a block circuit diagram of an embodiment of the present invention. As previously mentioned, common parts are designated by reference numbers already used in FIGS. 1 and 2.

The present invention is primarily directed to, but is not limited to, ultra high frequency signal generators,
It is especially directed to signal generators that generate signals in the range 1MHz to 2000MHz.

According to the invention, the digital signal from the microprocessor (not shown) is fed to the amplifier 16 via the DAC 34 and to the D
It is supplied to the input of the amplifier 18 via AC36. DAC38 is D
Provides an error signal that is combined with the output of AC36.

The sampled signal from line 24 is provided as an input to a mixer or sampler 40. The other input of the mixer is
This is a signal derived from the crystal controlled oscillator 42, which normally operates at 25 MHz. The output of this oscillator is then amplified by the power amplifier 44 and then the step-off diode 46.
To produce a so-called "comb-row" signal or harmonic spectrum signal. In this signal train, the lowest frequency is 25 MHz and the highest is defined above all by the bandwidth of the circuit.

The conversion of a fixed frequency signal of 25 MHz into a harmonic spectrum signal reliably produces a number of so-called "BIRDI" markers, and the sampled signal can be compared with this.

The comparison is done by a mixing technique that provides sum and difference signals at the output of mixer device 40. The Low Pass Filter 48
It eliminates all but the useful beat signal pulse, and is thus a lowpass filter with a cutoff frequency of 1 MHz. The attenuated output is the amplifier
It is amplified by 50 and supplied to the microprocessor via the pulse adjusting circuit 52.

4a and 4b represent the output nature of the pulse at the output of the regulation circuit 52.

In Figure 4a, the output pulse from the low pass filter is shown on a small scale. This has an oscillation frequency of 25 MH
It is generated every time a harmonic component of the z reference signal is passed,
And each pulse is itself a large number of pulses (see Figure 4b).
And its repetition frequency varies from relatively high levels near the edges of the pulse to mid DC levels (theoretical) in the pulse. The edge region is designated by reference numerals 54 and 56 in FIGS. 4a and 4b and the central DC band is designated by reference numeral 58.

The pulses such as 60 shown in Figure 4a are relatively narrow,
Because of the approximation, the leading edge (or trailing edge) of each pulse is detectable and can be used to indicate the arrival of the beat signal.

In accordance with a preferred aspect of the present invention, each pulse 60
A device for determining the midpoint of the
The DC or zero frequency band is adapted to be used to determine the actual presence of the pulse.

FIG. 5 illustrates a system developed from the system shown in FIG. 3 and includes, in general form, a microprocessor controller not shown previously.

Where common parts are used as in the previous figures, the same reference numbers are used. Thus, the YIG oscillator 10 has line 2
Providing RF output along 4 and elements 40, 42, 44, 46, 48, 5
The contents of 0 and 52 are shown as a single element, designated by reference numeral 62 in FIG. 5, for convenience.
One output from this element constitutes the RF output socket 64 and the other output constitutes the so-called marker output. Electrical pulses containing beat signal pulses or markers at this output are generated by the interaction of the output from the YIG oscillator with the harmonics derived from the output from the local crystal controlled oscillator 42 of FIG.

The individual pulses are referred to as markers, and in the inset in FIG. 5, a plurality of such markers and an enlarged view of the first marker are shown. From the enlarged view, the marker consists of a plurality of individual pulses of variable amplitude and frequency and has an essentially zero frequency or center region of DC, indicated by reference numeral 68.

According to the manner in which pulses such as 66 are generated, pulse 66
The presence of a DC level within the indicates the particular relationship between the output of the YIG oscillator and the output of the crystal controlled oscillator 42, and may also indicate the value of the control signal. This control signal is first supplied to the YIG oscillator.

The determination of the presence of a zero frequency band or DC level in a pulse, such as 66, is most simply accomplished using a microprocessor-controlled pulse analysis circuit, generally indicated at 70, and in block 62. A marker pulse interface device 72 (a part of which is incorporated in the pulse adjusting circuit 52 of FIG. 3) is provided between the output of the mixer and low pass filter of the included circuit and the input of the microprocessor controller 70. ) Is required.

The analysis circuit determines the width and midpoint of the first marker pulse 66. This point corresponds to the fact that there is a 1: 1 relationship between the YIG oscillator frequency and the frequency of the crystal controlled oscillator 42 of FIG. The microprocessor controller is equipped with a keyboard or other data entry device such as 74, which is dedicated to the device, including dedicated controls such as start / stop and center / width keys. Can be transformed.

The signal generator of FIG. 5 normally uses the sweep mode of operation, but for most of the subsequent discussion of circuit operation it is assumed to be the selected mode of operation.

The sweep width (scaling) and the initial preset of the center are determined by the start and stop frequencies required by the source to sweep. Thus, the YIG oscillator must be driven between start and stop frequencies by controlling the electrical signals supplied to two different frequency control elements within the oscillator, as described with respect to FIG. However, instead of the two elements described with respect to FIG. 3, three digital-to-analog converters are provided in order to have more control over the sweep settings. The first DAC 76 determines the center of the sweep, the second DAC 78 produces a ramp voltage that must be supplied to one or the other of the drive amplifiers 16 and 18 via the scaling DAC 80, and the third DAC 82 drifts. And a conversion of the error signal to the input of the second drive amplifier for controlling the input signal and controlling the tuning of the source.

Selector switch 84 allows the output from scaling DAC 80 to be provided as an input to amplifier 16 or 18.

A common source 86 provides a reference signal to the three DACs 76, 78 and 82, and a data bus from the microprocessor drive controller 70 is provided as a main data input to each of the DACs.

The data highway 88 provides information about tuning the YIG oscillator 10 and sweep parameters such as start and stop frequencies, as well as DAC 80, sweep DAC 78 and center DAC 76.
Provides sweep width information for.

During each sweep, the sweep DAC is the only converter that needs to be changed dynamically. Data highways 88 and 92
The information supplied via the swept DAC78 produces a fixed slope signal, but its actual shape and amplitude is
It is determined by the parameters within the microprocessor.
The actual amplitude of the ramp signal is assigned by converter 80, again using information from the microprocessor, to cover the appropriate sweep width determined by the information provided via data entry keyboard 74.

The function of the error DAC is to vary the frequency generated by the YIG oscillator 10 by up to +/- 25 MHz under the control of the microprocessor. This is used to shift the frequency of the signal generated by the YIG oscillator circuit 10 until it is an integer multiple of the harmonic component of the comb-column signal from the circuit element 46.

The response of the error DAC must be calibrated, stable and rapid so that the frequency of the YIG oscillator can be changed accurately and quickly anywhere within the 50MHz range dominated by the variator. In this way, the beat signal is 50
As long as it can be located at some point in the MHz band, the YIG oscillator can be calibrated to some frequency within +/− 25 MHz of the desired final frequency, then DAC82 is applied to the frequency control signal already supplied to the oscillator during calibration. By adding an additional error signal via, it is possible to shift to the desired frequency of the YIG oscillator.

Thus, the varying effects of the microprocessor and error DAC 82 serve two purposes. That is: 1. During calibration of the YIG oscillator at the beginning of each sweep, the variator shifts the frequency of the YIG oscillator quickly and accurately in the 50 MHz bandwidth, and at least one (preferably two) beat signal ( (Usually referred to as a marker).

2. After calibration, the same two elements (ie microprocessor 70 and error DAC 82) are needed to shift the frequency of the YIG oscillator to the desired frequency required by the input information supplied to the microprocessor. Functions to generate a DC shift signal.

The process of locating a beat signal or marker pulse such as 66 is as follows.

1. From frequency span selection, center, sweep width and sweep
All DACs have been initialized, and Micro Processor 70
Under the control of, the error DAC 82 is adjusted to the center of the range.

2. Trigger a search routine by the microprocessor when attempting to initiate a sweep. In this case, the error DAC82
Is adjusted in one direction (usually downward) until the marker pulse 66 is detected by the marker interface 72.

Usually, this process is set to look for changes in amplitude with a transformation from high-frequency content to DC and then to high-frequency content in the amplitude variation involved. Detected pulse
The location of the zero or DC level within 66 is identified, and the error signal or variation value required to produce a particular beat signal is stored in the microprocessor's memory.

3. Once you have set the required signal in the FM coil of the YIG oscillator to produce the marker pulse, the oscillator is enabled. Now, to get the desired frequency, it should be added (or subtracted) to the known signal to get the same frequency component as the identified comb string signal component
Calculating the additional signal is straightforward for the microprocessor.

If the desired frequency happens to be the frequency of the marker (comb-column signal component), no additional addition or subtraction is required.

In many common cases where the desired start frequency is not equal to one of the comb string signal components, an algorithm or lookup table is used to determine the correction of the signal needed to obtain the desired frequency from the calibration frequency. Is adopted.

The algorithm or lookup table may be stored in microprocessor memory (or may be loaded into ROM or machine memory via a keyboard) and the different signals supplied to the main and sub frequency decision coils. Regarding the frequency response of the YIG oscillator 10.

If very high accuracy is required, the microprocessor search routine includes the steps needed to identify the high frequency edge regions of the marker pulse 66 identified at 94 and 95 in FIG. The microprocessor is then programmed to interleave between the two edges of the marker pulse to find the center position between the two edges 94 and 96. The pulse 66 is generated when the YIG oscillator frequency moves from one frequency above the comb signal frequency to the bottom (or vice versa), so that the center point 68 changes the frequency of the YIG oscillator 10 to the comb signal frequency. Correspond when exactly equal. The frequency of oscillator 10 is mixed with this frequency. By incorporating this additional computational process into the microprocessor search program, the processor 70 can define unique and precise signal parameters for the output from the error DAC 82, which allows the YIG oscillator 10 to It is possible to generate a signal having exactly the same frequency as the frequency of the comb-shaped signal component derived from the controlled oscillator 42.

Currently, open loop signal generators provide frequency accuracy of about +/- 5 MHz. A device embodying the invention has achieved an accuracy of +/- 100 KHz at 2000 MHz. YIG oscillator 10
Has a good linearity and has a predictable frequency response to changes in the control signals from amplifiers 16 and 18, then a very precise sweep is made using the system shown in FIG. be able to.

If CW operation is required, the sweep width is set to zero and the operating frequency of YIG oscillator 10 is determined by central DAC 76. By setting the error DAC82 to the center range and invoking the microprocessor search routine, the YIG oscillator 1
0 finds a marker pulse that is as close as 66 (and its center position if that level of precision is needed),
It is calibrated by calculating the error or variation signal needed to shift the actual frequency of the YIG oscillator 10 to the desired frequency that the source 10 should generate.

Drift, especially due to heat during CW operation, can be controlled by the thermal compensation circuit described with respect to FIG.

If CW operation can be interrupted at regular intervals, the microprocessor 70 will be programmed to make this interruption and perform subsequent search and calibration routines before switching the RF back on during each interruption. Is good.

To reduce transient and switching problems, the YIG oscillator 10 should preferably not be turned on and off, but the RF circuit 62 should have a suitable attenuator to attenuate the output signal during initial calibration and subsequent calibration. including.

An attenuator of this kind is also preferably incorporated into the sweep mode of operation to attenuate the RF signal during calibration at the beginning of each sweep.

FIG. 6 shows an embodiment of hardware that does not incorporate a microprocessor. However, this embodiment is limited to such accuracy that it simply detects the presence of marker pulses such as 66.

Here, Marker Interface is a pulse presence detector
This detector comprises 114 and detects, by any convenient means, either the leading or trailing edge of the pulse indicated at 66.

The frequency corresponding to the required sweep is front panel 98
, And the frequency command circuit 100 calculates the appropriate drive signal to set the swept-digital data for the drive DAC 76 or the analog voltage for the drive amplifiers 16,18. The circuit also produces a voltage corresponding to the distance the required start frequency is away from the calibration point. This is called a fluctuation signal and can be turned on and off by the switch 81. Thus, the required start frequency is 57MHz
And when the calibration point is obtained at 50MHz, a signal corresponding to + 7MHz is generated. If 42MHz is the required starting point, a signal corresponding to -8MHz must be generated. A null signal (0 volts) is generated for a start frequency equal to the calibration point. This is because the start frequency
The same applies when it is a multiple of 25 MHz.

The frequency command circuit 100 sets the drive circuit so that the start frequency is a multiple of the calibration point, after calibration, puts a variation signal and adds this to the signal set by 100 to obtain the required start frequency. obtain.

The sweep ramp generator 102 produces a fixed ramp signal and drives the oscillator 10 via drive electronics 78, 80 over the range required by this signal. The generator initiates a ramp signal in response to the signal on the trigger input. When the ramp signal ends, the generator 102 indicates this by providing a signal to the sweep end output 104.

The other part of the hardware, the lock controller 108
Provides a second ramp signal spanning a small frequency range sufficient to cover the maximum expected error. When required by the signal on the lock clamp start input 110, the ramp signal starts from its minimum point and stops when commanded by the lock clamp stop input 112.

The RF output is provided to the marker presence detector 114 (already mentioned), and its output is latched by the latch circuit 116. Lock controller 108 causes a lock clamp stop signal to be generated on input 112 in the presence of marker pulse 66 (corresponding to the calibration point) so that the ramp value from 108 is held in sample and hold circuit 118. Operate.

The sequence of events that occur during a typical sweep under the control of the signal from timing circuit 120 is as follows.

Frequency parameters are loaded via the controller on the front panel 98. The frequency command circuit 100 sets the frequency to the desired stop frequency.

It will be appreciated that while the YIG oscillator 10 is being calibrated at the start and end of each sweep, the fluctuating signal must be removed. For this reason, switch S1 is provided.

If greater precision is required, the detector 114 will be a more complex device as it interleaves from the width of the pulse 66 and produces information corresponding to the detector zero 68, as described above with respect to FIG. obtain.

FIG. 7 shows a double reduction conversion system according to FIG. 3, which allows the software fixing to reach above 30 GHz by the appropriate selection of the two drive frequencies.

The design and operation of the system follows similar lines as in FIG. 3 and the same reference numerals are used where appropriate.

The RF output frequency samples are passed to a first down conversion stage that includes a mixer or sampling device 126. This mixer includes a high frequency reference source 128 (eg 500MHz SAW oscillator), a power amplifier 130 and a step-off diode 132.
A comb-shaped column signal for driving is supplied. The low frequency reduced transform signal is amplified and waved by 134, 136 to provide a wideband drive signal to a second reduced transform stage comprising a mixer or sampling device 138 (corresponding to the mixer or sampling device of FIG. 3). . The mixer 138 is driven by a drive signal having a frequency lower than that of the drive signal for the mixer 126. The drive reference signal for mixer 138 is derived from the reduced signal divided from the first reference signal (ie, 500 MHz SAW source) by use of divider 140.

The rest of the circuit functions much as described with respect to FIG.

Both low frequency and high frequency pulses are processed to allow for the increased non-linearity and increased inaccuracy of the indication that may occur at such high frequencies during initial tuning of the output frequency.
For this purpose, a second processing line 48 ', 5 for the output of 136
0'and 52 'are provided.

In use, the YIG oscillator 10 is generally tuned to find a closely related 500 MHz marker. Once this is found, it is passed to the relevant 25MHz on the low frequency marker output.
Can be compared to the marker. Then, for that output frequency range, only comparisons to the 25MHz marker are needed. Only if the output frequency should be shifted significantly (eg 3GHz) will a comparison to the 500MHz marker output be needed.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram of an open loop oscillator with temperature compensation, FIG. 2 is a schematic circuit diagram of a closed loop oscillator or synthesizer, and FIG. 3 is a frequency diagram of a master oscillator embodying the present invention. A block diagram of a crystal control beat signal (marker), FIGS. 4a and 4b are diagrams showing a typical marker pulse configuration, and FIG. 5 shows a drive circuit and a beat signal (marker) fixed loop embodying the present invention. A block diagram of the RF source provided, FIG. 6 is an alternative system embodying the invention, but without the programmed microprocessor required for FIG. 5, FIG. 7 is the RF range. But
Based on the circuit of Fig. 3, which can reach as high as 30GHz 2
It is a block diagram which shows a heavy reduction conversion system. 10: YIG oscillator 12: Coarse tuning port 14: Fine tuning port 16, 18: (Signal) amplifier 20: Amplifier 22: Temperature compensation resistor or thermistor 28: Programmable amplifier 30: Phase detector 34, 36, 38: DAC (Digital-analog converter) 40: Mixer or sampling device (or sampler) 42: Crystal controlled oscillator 44: Power amplifier 46: Step-off diode 48: Low-pass filter 50: Amplifier 52: Adjustment circuit

Claims (6)

[Claims] 1. F within a range of up to hundreds to thousands of MHz
With coarse and fine frequency control elements that provide an output frequency of MHz and are provided with a frequency control signal, with fine frequency control, over only a small range of N MHz, corresponding to the frequency of the electrical signal provided to the element. In the method of setting the output frequency of a signal generator that can cause a linear change in the output frequency with respect to changes, the output of the device is set to a frequency of L MHz that is within +/- N MHz of the desired frequency of F MHz. The frequency control signal supplied to the device, which is combined with the multi-component reference signal containing at least the component having
Adjusted to produce an output signal having a frequency in the range of − / − N MHz, and the fine frequency control element detects a corresponding signal indicating a one-to-one relationship between the output signal and said reference signal (or a component thereof). Value of the frequency control signal, which is adjusted until the corresponding signal is detected, is stored, and an algorithm or a look-up table is used to shift the frequency of the device by (F−L) MHz. Determines the value of the correction signal required and the desired output signal at F MHz adds the correction signal to the stored frequency control signal and adds the correction signal to the stored control signal associated with the corresponding signal. A method for setting an output frequency of a signal generator, which is obtained by using a frequency control signal obtained by adding as a control signal for a device. 2. The setting method according to claim 1, wherein the calibration procedure and the frequency shift, zero point detection, signal storage and addition are performed under the control of a microprocessor. 3. A signal generator having an output frequency set to a frequency F, having an output generated by a radio frequency signal when in operation, having a large band frequency control element and a small band control element. , In the one provided with the main oscillator capable of changing the oscillation frequency over a small frequency band by linearly changing the frequency of the electric signal supplied thereto by the element, A. From the input information, A controller configured to generate an electrical signal for controlling the frequency of the master oscillator, B. means for deriving the sample signal from the output of the master oscillator, and C. a stable device for generating the reference signal F (ref). A fixed frequency oscillating signal source, and D. a reference signal F (ref), a harmonic spectrum of a signal in which at least one component is in the small frequency band from F, that is, a comb array F (ref); 3F (ref) ... nF ref)
A circuit for generating (called a harmonic spectrum signal), and E. combining the sampled signal with the harmonic spectrum signal, between the beat signal, namely the frequency of the sample signal and the components of said harmonic spectrum signal, among others. It has a mixing or sampling circuit that produces a signal with a frequency that is an arithmetic difference, and F. a beat signal detection circuit that responds to the output of the mixing circuit to identify that a beat signal pulse is being generated. For the purpose of calibration, upon detection of the selected beat signal (caused by the interaction of the main oscillator output signal and one component NF (ref) of the harmonic spectrum signal), the frequency determining signal supplied to the main oscillator is If the value is (NF (ref)
Until a new value of the control signal for the master oscillator is taken into account in the control device in order to obtain an oscillation frequency equal to + X) (where X is the frequency required between NF (ref) and the desired frequency F). A shift), said controller being programmed to change the frequency control signal supplied to the master oscillator tuning controller. 4. A method for controlling an oscillation frequency of a main oscillator in a signal generator having a linear frequency control element having a limited frequency sweep capability, comprising: A. Frequency control for logically generating a frequency F at the output of the main oscillator. Generating a signal, B. combining a sample of the master oscillator output signal with a reference signal having one component within said limited sweep frequency of the master oscillator, C. selecting between the master oscillator output signal and the reference signal component. Adjust the value of the frequency control signal until the beat signal is detected, D. then describe the value of the frequency control signal, from the value corresponding to the calibration, the frequency response of the master oscillator to the value of the frequency control signal Oscillation frequency control method with steps to adjust to a new value calculated using a look-up table or algorithm, thus shifting the master oscillator output to the desired frequency . 5. When the master oscillator is required to sweep a frequency range, A. Calculated according to an algorithm that combines the oscillation frequency with the value of the control signal, using the corrected control signal as a starting point. B. suppress the output of the signal generator when the final target frequency of the sweep is reached, and C. then repeat the correction process including the method described above until the beat signal is detected again. A method according to claim 4, including the steps of allowing the sweep process to be restarted thereafter. 6. The reference signal is a harmonic spectrum signal,
And A. Identify a series of key frequencies through the range to be swept, start at the lowest or highest, and continue until the beat signal is generated by the interaction of the master oscillator output signal with one component of the reference signal. Correcting the control signal supplied to B. modifying the corrected control signal according to a known algorithm for generating a control signal to obtain a frequency between the first frequency and the next target frequency; C. 6. The method of claim 5 including the steps of repeating the calibration process for the oscillator control signal as the next target frequency is approached, and then continuing to change the oscillator frequency through the next frequency range to the next target frequency. The described oscillation frequency control method.