JPH0779003A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPH0779003A
JPH0779003A JP5161270A JP16127093A JPH0779003A JP H0779003 A JPH0779003 A JP H0779003A JP 5161270 A JP5161270 A JP 5161270A JP 16127093 A JP16127093 A JP 16127093A JP H0779003 A JPH0779003 A JP H0779003A
Authority
JP
Japan
Prior art keywords
film
ito
transparent conductive
conductive film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5161270A
Other languages
Japanese (ja)
Inventor
Katsumi Okuda
勝己 奥田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP5161270A priority Critical patent/JPH0779003A/en
Publication of JPH0779003A publication Critical patent/JPH0779003A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

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  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To suppress the generation of peeling of a transparent conductive film by forming the transparent film having ITO crystals, an average crystal grain diameter exceeding a specified value, and further forming a semiconductor film by a plasma containing reducing active species on this transparent conductive film. CONSTITUTION:A transparent conductive film having an ITO crystal is formed by a thin film forming means on a transparent substrate so that an average crystal grain diameter will be over 0.025mum. On this ITO transparent conductive film, another type of semiconductor film is formed by using a plasma which contains reducing active species such as a hydrogen radical. As a result, ruggedness is produced on the ITO surface, and this ruggedness relaxes stress inside the other type of semiconductor film and between the other type of semiconductor film and the ITO film. This enables the peeling of the ITO film to be suppressed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体デバイスの製法に
おいて、特に透明基体上に透明導電膜と半導体膜が積層
して形成される半導体素子の製法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor element in which a transparent conductive film and a semiconductor film are laminated on a transparent substrate.

【0002】[0002]

【従来の技術】透明基体上に形成される半導体デバイ
ス、例えば液晶ディスプレイパネルやELディスプレイ
パネル、密着型イメージセンサ、電子写真感光体などに
おいては、その透明基体としてガラスや樹脂フィルムな
ど導電性を有しない材料が用いられることが多いが、基
体には透明性と同時に導電性も要求されることがほとん
どである。その場合、透明基体の半導体膜が形成される
面に透明性を維持しつつ導電性を持たせるために、基体
上に薄膜形成手段により透明導電膜が形成されることが
一般に行なわれている。このような透明導電膜として
は、通常、ITO(インジウム・スズ・酸化物)やIn
2 3 (酸化インジウム)、SnO2 (二酸化スズ)な
どが使用されている。
2. Description of the Related Art In a semiconductor device formed on a transparent substrate, such as a liquid crystal display panel, an EL display panel, a contact type image sensor, an electrophotographic photosensitive member, etc., the transparent substrate has conductivity such as glass or resin film. Often, non-use materials are used, but in most cases, the substrate is required to have conductivity as well as transparency. In that case, a transparent conductive film is generally formed on the substrate by means of a thin film forming means in order to have conductivity while maintaining transparency on the surface of the transparent substrate on which the semiconductor film is formed. As such a transparent conductive film, ITO (indium tin oxide) or In is usually used.
2 O 3 (indium oxide), SnO 2 (tin dioxide) and the like are used.

【0003】[0003]

【発明が解決しようとする問題点】透明導電膜として広
く用いられているITOは、例えばスパッタリング法や
イオンプレーティング法、活性反応蒸着法などの薄膜形
成方法により大面積への成膜が可能で、エッチングによ
るパターン形成などの加工性が良好な優れた性質を有し
ているが、反面、その膜上にプラズマCVD法によって
半導体膜を積層する場合に、プラズマによるダメージを
受けやすく、膜表面の荒れや変色による透明性の低下を
生じやすいという問題も有している。また、半導体膜を
形成するためのプラズマが水素などの還元性活性種を含
んでいると、ITO膜と基体との密着性が低下し、半導
体膜を積層した後で、その半導体膜の応力によってIT
O膜の剥離が発生するという問題もあった。
ITO, which is widely used as a transparent conductive film, can be formed on a large area by a thin film forming method such as a sputtering method, an ion plating method, or an active reaction vapor deposition method. , And has excellent workability such as patterning by etching, but on the other hand, when a semiconductor film is laminated on the film by a plasma CVD method, it is easily damaged by plasma and the film surface There is also a problem that transparency is likely to decrease due to roughness and discoloration. Further, when the plasma for forming the semiconductor film contains a reducing active species such as hydrogen, the adhesion between the ITO film and the substrate decreases, and after the semiconductor films are stacked, the stress of the semiconductor film causes IT
There is also a problem that peeling of the O film occurs.

【0004】このような透明導電膜の剥離対策として、
特開平2−109294号には、透明電極が形成される
ガラス基板に、透明電極の膜厚の半分に匹敵する程度の
凹凸を設けることが開示されているが、大面積の基板に
そのような微細な加工を均一に施すことは技術的にもコ
スト的にも困難であり、プラズマによるダメージを受け
やすいという問題は残されていた。また特開平2−15
19号には、酸化インジウムを主成分とする透明導電層
の(222)面の配向度を50%以上にすることが開示
されているが、これはショットキーバリア構造の接合特
性を改良するものであって、上記の剥離やダメージの問
題は改善されておらず、特定の結晶面の配向度を大面積
の基板上で均一に制御することは、技術的にも困難であ
った。さらに、ITO膜表面のプラズマによるダメージ
を軽減する対策として、ITO膜上にプラズマによるダ
メージに強いSnO2 を薄く積層することも行なわれて
いるが、このように2種類の膜を積層することは、透明
導電膜を成膜する装置の構造や条件の複雑化をもたらし
製造上不利となると共に、2種類の膜の界面で光の反射
が生じたり透明導電膜全体としての光透過率が低下する
問題もあり、加えてSnO2 はエッチングによる加工性
がITOより劣るため、パターン形成に際しても不利と
なっていた。
As a measure for peeling such a transparent conductive film,
Japanese Unexamined Patent Publication (Kokai) No. 2-109294 discloses that a glass substrate on which a transparent electrode is formed is provided with irregularities to the extent of half the film thickness of the transparent electrode. It is technically and costly to uniformly perform fine processing, and there remains a problem that plasma is easily damaged. In addition, JP-A-2-15
No. 19 discloses that the degree of orientation of the (222) plane of the transparent conductive layer containing indium oxide as a main component is set to 50% or more, which improves the bonding characteristics of the Schottky barrier structure. However, the problems of peeling and damage have not been improved, and it has been technically difficult to uniformly control the degree of orientation of a specific crystal plane on a large-area substrate. Further, as a measure for reducing plasma damage on the ITO film surface, a thin layer of SnO 2 that is resistant to plasma damage has been thinly stacked on the ITO film. However, it is not possible to stack two types of films in this way. , The structure and conditions of the apparatus for forming the transparent conductive film are complicated, which is disadvantageous in manufacturing, and light is reflected at the interface between the two kinds of films, or the light transmittance of the entire transparent conductive film is reduced. There is also a problem, and in addition, since SnO 2 is inferior to ITO in workability by etching, it is disadvantageous in pattern formation.

【0005】本発明は上記の問題点を透明導電膜の改良
により解決すべくなされた半導体素子の製法であり、透
明導電膜の表面状態を制御することによって、技術的な
困難さや膜形成に係るコストの増加をもたらすことな
く、透明導電膜表面の荒れや変色による透明性の低下お
よび半導体膜を積層した後の透明導電膜の剥離の発生を
抑制することを目的とする。
The present invention is a method for manufacturing a semiconductor device, which has been made to solve the above problems by improving a transparent conductive film. The present invention relates to technical difficulties and film formation by controlling the surface state of the transparent conductive film. An object of the present invention is to suppress the deterioration of the transparency due to the surface roughness and discoloration of the transparent conductive film and the peeling of the transparent conductive film after the semiconductor films are laminated without increasing the cost.

【0006】[0006]

【問題点を解決するための手段】本発明の半導体素子の
製法は、透明基体上に薄膜形成手段により、平均結晶粒
径が0.025μm以上となるようなITO結晶を有す
る透明導電膜を形成し、更にこの透明導電膜上に還元性
活性種を含むプラズマにより半導体膜を形成することを
特徴として成る半導体素子の製法である。
According to the method of manufacturing a semiconductor element of the present invention, a transparent conductive film having ITO crystals having an average crystal grain size of 0.025 μm or more is formed on a transparent substrate by a thin film forming means. In addition, a semiconductor film is formed on the transparent conductive film by plasma containing reducing active species.

【0007】[0007]

【作用】透明基体上に薄膜形成手段により形成されたI
TO透明導電膜の上に、水素ラジカルなどの還元性活性
種を含むプラズマを用いて、別種の半導体膜を形成する
と、その別種半導体膜内および別種半導体膜とITO膜
との間に応力が発生する。その応力がITO膜と透明基
体との密着性より強くなると、ITO膜の剥離を発生さ
せる。
Operation: I formed on the transparent substrate by the thin film forming means
When a different type of semiconductor film is formed on the TO transparent conductive film by using plasma containing a reducing active species such as hydrogen radicals, stress is generated in the different type of semiconductor film and between the different type of semiconductor film and the ITO film. To do. When the stress becomes stronger than the adhesion between the ITO film and the transparent substrate, the ITO film is peeled off.

【0008】このような半導体素子に用いられる透明基
体としては、パイレックスガラスやソーダガラス、ホウ
珪酸ガラスなどのガラスや、石英やサファイアなどの透
明な無機質系、並びに弗素樹脂やポリエステル、ポリカ
ーボネート、ポリエチレンテレフタレート、ビニロン、
エポキシ、マイラーなどの透明な有機樹脂系が挙げら
れ、平板状やシート状、ドラム状あるいはベルト状など
の形状で用いられる。
As the transparent substrate used for such a semiconductor element, glass such as Pyrex glass, soda glass, borosilicate glass, transparent inorganic materials such as quartz and sapphire, fluororesin, polyester, polycarbonate, polyethylene terephthalate. , Vinylon,
Examples thereof include transparent organic resin materials such as epoxy and mylar, which are used in the shape of a flat plate, a sheet, a drum, or a belt.

【0009】また、上記透明導電膜を構成する材料に
は、ITOを始めとしてSnO2 、In2 3 、酸化鉛
(ZnO)、ヨウ化銅(CuI)、硫化銅(CuS)、
InOF、Cd2 SnO4 、Auなどがある。そして、
これら透明導電膜を形成するための薄膜形成手段には、
イオンプレーティング法や活性反応蒸着法、真空蒸着
法、RFスパッタリング法、DCスパッタリング法RF
マグネトロンスパッタリング法、DCマグネトロンスパ
ッタリング法、熱CVD法、プラズマCVD法、触媒C
VD法、スプレー法、塗布法、浸漬法などがある。
In addition, as the material forming the transparent conductive film, ITO, SnO 2 , In 2 O 3 , lead oxide (ZnO), copper iodide (CuI), copper sulfide (CuS),
InOF, Cd 2 SnO 4 , Au, etc. are available. And
The thin film forming means for forming these transparent conductive films includes
Ion plating method, active reaction vapor deposition method, vacuum vapor deposition method, RF sputtering method, DC sputtering method RF
Magnetron sputtering method, DC magnetron sputtering method, thermal CVD method, plasma CVD method, catalyst C
There are a VD method, a spray method, a coating method, a dipping method and the like.

【0010】ここで、透明基体上に例えばITO透明導
電膜を形成するに当たってその形成条件を制御し、透明
導電膜中のITO結晶の配向性をある特定の方向に強く
なるようにして作製すると、その特定方向の配向を持っ
たITO結晶の平均粒径が大きくなり、ITO膜の表面
に凹凸ができる。このような凹凸ができると、ITO膜
上に別種半導体膜を形成した場合の別種半導体膜内およ
び別種半導体膜とITO膜との間の応力を緩和すること
ができるため、ITO膜の剥離を抑制することができ
る。
Here, when forming, for example, an ITO transparent conductive film on a transparent substrate, the formation conditions are controlled so that the orientation of the ITO crystal in the transparent conductive film becomes strong in a specific direction. The average grain size of the ITO crystal having the orientation in the specific direction becomes large, and irregularities are formed on the surface of the ITO film. When such unevenness is formed, the stress in the different semiconductor film and between the different semiconductor film and the ITO film when the different semiconductor film is formed on the ITO film can be relieved, so that the peeling of the ITO film is suppressed. can do.

【0011】また、このような凹凸による応力緩和の作
用はITO透明導電膜の場合に限らず、SnO2 やIn
2 3 等の他の透明導電膜やその他の多結晶膜に別種半
導体膜を積層する場合にも、応用できるものと考えられ
る。
The effect of stress relaxation due to such unevenness is not limited to the case of the ITO transparent conductive film, but SnO 2 and In
It is considered to be applicable to the case where another kind of semiconductor film is laminated on another transparent conductive film such as 2 O 3 or another polycrystalline film.

【0012】[0012]

【実施例】以下、実施例を具体的に示す。 〔例1〕図2に、ITO膜の成膜に用いたイオンプレー
ティング装置1の概略構成図を示す。イオンプレーティ
ング装置1は、本体2aとその底体2bとからなる真空
容器2の中に、成膜用イオン供給源としての蒸発源3と
反応性プラズマ生成用の高周波コイル4、陰極ベースを
兼ねた基体支持体5、ハロゲンヒーター等からなる基体
加熱用ヒーター6、成膜の開始と終了を制御するための
シャッター7とが配置されており、蒸発源3には蒸発源
電源8が、高周波コイル4には高周波電源9が、基体支
持体5には直流電源10がそれぞれ接続されている。ま
た真空容器の本体2aには、バルブ11とガス流量調整
器12を介した反応ガス導入口13と、イオンポンプや
油拡散ポンプなどの真空排気手段(図示せず)に接続さ
れたガス排気口14とが配設されている。図中の矢印
は、ガスの流れを表わす。
EXAMPLES Examples will be specifically described below. Example 1 FIG. 2 shows a schematic configuration diagram of the ion plating apparatus 1 used for forming the ITO film. The ion plating apparatus 1 also serves as an evaporation source 3 as a film forming ion supply source, a high frequency coil 4 for generating a reactive plasma, and a cathode base in a vacuum container 2 composed of a main body 2a and a bottom body 2b thereof. A substrate support 5, a substrate heating heater 6 including a halogen heater, and a shutter 7 for controlling the start and end of film formation are arranged. The evaporation source 3 includes an evaporation source power source 8 and a high-frequency coil. A high frequency power source 9 is connected to the base 4, and a direct current power source 10 is connected to the base support 5. Further, in the main body 2a of the vacuum container, a reaction gas introduction port 13 via a valve 11 and a gas flow rate controller 12, and a gas exhaust port connected to a vacuum exhaust unit (not shown) such as an ion pump or an oil diffusion pump. And 14 are provided. The arrows in the figure represent the flow of gas.

【0013】このイオンプレーティング装置1によりI
TO成膜を行なうには、まず基体支持体5に被成膜基体
15を装着して真空容器2内を真空排気手段により10
-6Torr程度の真空度まで排気すると共に、ヒーター6に
よって基体15を所定の成膜温度まで加熱する。次い
で、バルブ11を開け、アルゴン(Ar)と酸素
(O)の混合ガス等からなる反応ガスを、流量調整器
12により所定の流量に設定してガス導入口13より容
器2内に導入し、容器2内を所定圧力に設定する。次
に、蒸発源電源8をONにして蒸発源3からインジウム
(In)とスズ(Sn)の酸化物などからなる成膜用材
料を蒸発させると共に、高周波電源9よりコイル4に高
周波を印加して反応性プラズマを生成し、また直流電源
10により基体支持体5に負電圧を印加して、成膜条件
を調整し、安定化させる。その後、シャッター7を開け
ることにより蒸発源3からの成膜用材料が反応性プラズ
マを通過して基体15へ到達し、ITO膜が成膜され
る。そして、所望の膜厚が得られたら再びシャッター7
を閉じて成膜を終了する。
With this ion plating apparatus 1, I
In order to perform TO film formation, first, the film formation substrate 15 is mounted on the substrate support 5 and the inside of the vacuum container 2 is evacuated to 10
The substrate 6 is evacuated to a vacuum degree of about -6 Torr and the substrate 15 is heated to a predetermined film forming temperature by the heater 6. Next, the valve 11 is opened, and a reaction gas composed of a mixed gas of argon (Ar) and oxygen (O 2 ) or the like is set to a predetermined flow rate by the flow rate controller 12 and introduced into the container 2 through the gas introduction port 13. The inside of the container 2 is set to a predetermined pressure. Next, the evaporation source power source 8 is turned on to evaporate the film forming material composed of oxides of indium (In) and tin (Sn) from the evaporation source 3 and apply a high frequency to the coil 4 from the high frequency power source 9. Reactive plasma is generated, and a negative voltage is applied to the substrate support 5 by the DC power source 10 to adjust and stabilize the film forming conditions. After that, by opening the shutter 7, the film forming material from the evaporation source 3 passes through the reactive plasma and reaches the substrate 15, and the ITO film is formed. Then, when the desired film thickness is obtained, the shutter 7 is pressed again.
Is closed to complete the film formation.

【0014】上記のイオンプレーティング装置1によ
り、以下の条件で成膜速度の異なる2種のITO膜を成
膜した。両者に共通の条件として、基体には外径30m
m、長さ260mmのガラス管を用い、成膜温度は25
0℃に設定した。反応性ガスにはAr5sccmとO2
15sccmの混合ガスを用い、コイル4に印加する高周波
電力は200Wとした。また、蒸発源には酸化錫(Sn
2 )を5重量%添加した酸化インジウム(In
2 3 )からなる金属酸化物ターゲットを用い、成膜速
度の制御は、蒸発源に印加する電力を調整して蒸発量を
変えることで行なった。この蒸発量の確認は、蒸発源を
蒸発させる前後の真空容器2内の圧力上昇値を真空計で
モニターすることで行なった。そして、成膜速度の異な
る2種のITO膜として、成膜速度3Å/secの試料
Aと成膜速度1Å/secの試料Bとを、それぞれ10
00Åの厚みで作製した。
Using the above-mentioned ion plating apparatus 1, two kinds of ITO films having different film forming rates were formed under the following conditions. As a condition common to both, the outer diameter of the base is 30 m
m, glass tube of 260 mm in length, film formation temperature is 25
It was set to 0 ° C. Ar 5 sccm and O 2 as reactive gas
The mixed gas of 15 sccm was used, and the high frequency power applied to the coil 4 was 200 W. Further, tin oxide (Sn
O 2) 5 wt% added indium oxide (In
The deposition rate was controlled by adjusting the electric power applied to the evaporation source and changing the evaporation amount using a metal oxide target composed of 2 O 3 ). The amount of evaporation was confirmed by monitoring the pressure rise value in the vacuum container 2 before and after the evaporation source was evaporated with a vacuum gauge. Then, as two kinds of ITO films having different film forming speeds, a sample A having a film forming speed of 3 Å / sec and a sample B having a film forming speed of 1 Å / sec were respectively used.
It was manufactured with a thickness of 00Å.

【0015】これら試料AおよびBについてのX線回折
測定の結果と膜表面のSEM(走査型電子顕微鏡)写真
とを、それぞれ図1(a)および(b)に示す。X線回
折測定は、日本電子製JDX−10RA型を使用して、
X線源としてCu管球に電圧50kV、電流200 mAを印
加し、2軸縦型ゴニオメータを用いてサンプリング角度
0.010 度、スキャン速度2.00度/分、走査軸2θ/θと
し、受光スリット幅0.60mm、発散スリット角度と散乱
スリット角度と受光スリット角度をそれぞれ1度に設定
して行なった。またSEM写真は、日立製S800走査
型電子顕微鏡を使用して、試料表面にPt−Pd蒸着を行な
って、チルト角度0度で撮影した。
The results of X-ray diffraction measurement and SEM (scanning electron microscope) photographs of the film surface of these samples A and B are shown in FIGS. 1 (a) and 1 (b), respectively. For X-ray diffraction measurement, using JEOL JDX-10RA type,
Applying a voltage of 50 kV and a current of 200 mA to a Cu tube as an X-ray source, and using a two-axis vertical goniometer to sample the angle.
The scanning speed was set to 0.010 degrees, the scanning speed was set to 2.00 degrees / minute, the scanning axis was set to 2θ / θ, the receiving slit width was set to 0.60 mm, and the divergence slit angle, the scattering slit angle, and the receiving slit angle were set to 1 degree. Moreover, the SEM photograph was taken at a tilt angle of 0 degree by performing Pt-Pd vapor deposition on the sample surface using a Hitachi S800 scanning electron microscope.

【0016】ITO透明導電膜の平均結晶粒径は、5万
倍の倍率で撮影したSEM写真に長さ50mmの線を1
0本引き、各線にかかる結晶粒子の個数を数えて50m
m当たりの結晶粒子の平均個数を求め、その平均個数よ
り平均結晶粒径を計算して求めた。前記SEM写真より
試料AおよびBの平均結晶粒径を求めたところ、成膜速
度が3Å/secと速い試料Aでは結晶粒子の平均個数
が48.8個であり、平均結晶粒径は(50mm/4
8.8)÷50,000=2.049×10-5mmすな
わち0.020μmと小さく、成膜速度が1Å/sec
と遅い試料Bでは結晶粒子の平均個数が28.6個であ
り、平均結晶粒径は(50mm/28.6)÷50,0
00=3.497×10-5mmすなわち0.035μm
と大きくなっており、それぞれ成膜速度との対応が見ら
れた。また成膜速度の遅い試料Bでは、X線回折の結果
に試料Aに見られた(332) 、(521) 、(611) 、(541) 等
のピークが認められなくなっていることから、(211) 、
(222) 、(400) 、(440) といった特定方向の配向を持っ
た結晶が大きくなっていることが判る。これらの結果、
SEM写真からも判るようにITO膜表面に形成される
凹凸が大きくなっており、成膜速度を遅くすることでI
TO膜の結晶の配向性や平均粒径を制御でき、それによ
り膜表面に形成される凹凸の大きさを制御できることが
確認できた。
The average crystal grain size of the ITO transparent conductive film is a SEM photograph taken at a magnification of 50,000 times, and a line with a length of 50 mm is 1
Draw 0 and count the number of crystal particles on each line to 50 m
The average number of crystal grains per m was determined, and the average crystal grain size was calculated from the average number. When the average crystal grain size of Samples A and B was determined from the SEM photograph, the average number of crystal grains was 48.8 in Sample A having a high film formation rate of 3Å / sec, and the average crystal grain size was (50 mm / 4
8.8) ÷ 50,000 = 2.049 × 10 −5 mm, that is, as small as 0.020 μm, and the film formation rate is 1Å / sec.
The average number of crystal grains is 28.6 in Sample B, which is slow, and the average crystal grain size is (50 mm / 28.6) ÷ 50,0.
00 = 3.497 × 10 −5 mm or 0.035 μm
It was found that there was a correspondence with the film formation rate. In addition, since the peaks of (332), (521), (611), (541), etc. found in Sample A are not observed in the result of X-ray diffraction in Sample B having a slow film formation rate, 211),
It can be seen that crystals with (222), (400), (440) orientations in a particular direction are large. These results,
As can be seen from the SEM photograph, the unevenness formed on the surface of the ITO film is large.
It was confirmed that the crystal orientation of the TO film and the average grain size can be controlled, and thereby the size of the irregularities formed on the film surface can be controlled.

【0017】〔例2〕〔例1〕と同様にして、外径30
mm、長さ260mmのガラス管基体に成膜速度を変え
て平均結晶粒径を変えたITO膜を形成したものをいく
つか作製し、その上にプラズマCVD法によりa−Si
膜を積層した。
[Example 2] In the same manner as in [Example 1], an outer diameter of 30
mm glass, 260 mm long glass tube substrate having several ITO films with different average crystal grain sizes formed by changing the film forming speed were prepared, and a-Si was formed on the ITO film by the plasma CVD method.
The membrane was laminated.

【0018】ここで、a−Si膜を形成するためのプラ
ズマCVD成膜反応炉の例を、図3に基づいて説明す
る。図3は、プラズマCVD成膜反応炉16の概略構成
図である。図3に示したプラズマCVD成膜反応炉16
において、17は円筒状の金属製反応炉、18はITO
膜が形成されたガラス管基体15を装着する筒状の導電
性支持体であり、基体15は、ITO膜と支持体18と
の導通を取り、かつ基体15の端部に非成膜部を設ける
ためのマスク19と、ダミーリング20とによって、支
持体18に保持されている。21は基体加熱用ヒータ
ー、22はa−Siの成膜に用いられる筒状のグロー放
電用電極板であり、この電極板22には多数のガス噴出
口23が形成されている。そして、24は反応炉内部へ
ガスを導入するためのガス導入口、25はグロー放電に
晒されたガスの残余ガスを排気するためのガス排出口で
あり、26は導電性支持体18とグロー放電用電極板2
2の間でグロー放電を発生させるための高周波電源であ
る。ここで図中の矢印は、ガスの流れを表わす。また、
この反応炉16は円筒体17aと蓋体17bと底体17
cとからなり、そして、円筒体17aと蓋体17bとの
間、並びに円筒体17aと底体17cとの間には、それ
ぞれ絶縁性のリング17dを設けており、これによって
高周波電源26の一方の端子は円筒体17aを介してグ
ロー放電用電極板22と導通しており、他方の端子は蓋
体17bや底体17cを介して導電性支持体18と導通
し、接地されている。また、蓋体17bの上に付設した
モーター27により回転軸28を介して導電性支持体1
8が回転駆動され、これに伴って基体15も回転する。
Here, an example of a plasma CVD film forming reaction furnace for forming an a-Si film will be described with reference to FIG. FIG. 3 is a schematic configuration diagram of the plasma CVD film forming reaction furnace 16. Plasma CVD film forming reaction furnace 16 shown in FIG.
In the figure, 17 is a cylindrical metal reaction furnace, and 18 is ITO.
It is a cylindrical conductive support on which the glass tube substrate 15 on which the film is formed is mounted. The substrate 15 establishes electrical continuity between the ITO film and the support 18, and a non-film-forming portion is formed at the end of the substrate 15. It is held on the support 18 by a mask 19 for providing and a dummy ring 20. Reference numeral 21 is a heater for heating the substrate, 22 is a cylindrical glow discharge electrode plate used for film formation of a-Si, and a large number of gas ejection ports 23 are formed in this electrode plate 22. Further, 24 is a gas inlet for introducing gas into the reaction furnace, 25 is a gas outlet for exhausting residual gas of the gas exposed to glow discharge, and 26 is a conductive support 18 and a glow. Discharge electrode plate 2
It is a high frequency power supply for generating glow discharge between the two. Here, the arrows in the figure represent the flow of gas. Also,
The reactor 16 includes a cylindrical body 17a, a lid body 17b, and a bottom body 17a.
and an insulating ring 17d is provided between the cylindrical body 17a and the lid body 17b, and between the cylindrical body 17a and the bottom body 17c. The terminal is electrically connected to the glow discharge electrode plate 22 through the cylindrical body 17a, and the other terminal is electrically connected to the conductive support body 18 through the lid body 17b and the bottom body 17c and is grounded. In addition, the motor 27 attached on the lid 17b causes the conductive support 1 to pass through the rotary shaft 28.
8 is driven to rotate, and the base 15 also rotates accordingly.

【0019】このプラズマCVD成膜反応炉16を用い
てa−Si膜を成膜する場合には、基体15を支持体1
8に装着し、a−Si生成用ガスをガス導入口24より
反応炉内部へ導入し、このガスをガス噴出口23を介し
て基体15表面へ向けて噴出し、更にヒーター21によ
って基体15を所要の温度に設定するとともに、高周波
電源26より高周波電力を供給して支持体18と電極板
22との間でグロー放電を発生させ、更に基体15を回
転させることによって基体15の周面にa−Si膜を成
膜する。このようにしてa−Si膜を成膜するグロ−放
電プラズマ中には、a−Si生成用の原料ガスとしての
シランガスやジシランガス等に含まれている水素、ある
いはそれら原料ガスやa−Siの特性調整用に添加され
る不純物ガスの希釈用として用いられる水素ガスから、
還元性活性種である水素ラジカルが生成されて含まれて
いる。
When an a-Si film is formed using this plasma CVD film forming reaction furnace 16, the substrate 15 is used as the support 1.
8, the gas for a-Si generation is introduced into the reaction furnace through the gas introduction port 24, the gas is ejected toward the surface of the substrate 15 through the gas ejection port 23, and the substrate 15 is further heated by the heater 21. The temperature is set to a required temperature, high-frequency power is supplied from the high-frequency power source 26 to generate glow discharge between the support 18 and the electrode plate 22, and the base 15 is further rotated to a. -Form a Si film. In the glow discharge plasma for forming the a-Si film in this manner, hydrogen contained in silane gas or disilane gas as a raw material gas for generating a-Si, or the raw material gas or a-Si From the hydrogen gas used for dilution of the impurity gas added for characteristic adjustment,
Hydrogen radicals that are reducing active species are generated and included.

【0020】実験として、まずイオンプレーティング装
置1を用いて〔例1〕と同様に、外径30mm、長さ2
60mmのガラス管基体に成膜速度を変えて平均結晶粒
径を0.015〜0.035μmの間で変えたITO膜
を形成したものを5種類作製し、その上にプラズマCV
D成膜反応炉16を用いて、シランガス 700sccm、ガス
圧力 0.5Torr、成膜温度 250℃、高周波電力 700Wの条
件で、それぞれ4時間の成膜を行なって厚み8μmのa
−Si膜を積層し、試料C〜Gを作製した。
As an experiment, first, using the ion plating apparatus 1, as in [Example 1], the outer diameter was 30 mm and the length was 2 mm.
Five types of 60 mm glass tube substrates on which an ITO film was formed by changing the film formation rate and changing the average crystal grain size between 0.015 and 0.035 μm were prepared, and plasma CV was formed on the ITO film.
D film-forming reaction furnace 16 was used to perform film formation for 4 hours under the conditions of silane gas 700sccm, gas pressure 0.5 Torr, film formation temperature 250 ° C., and high-frequency power 700W.
-Si films were laminated to prepare samples C to G.

【0021】次いで、これらの試料についてITO膜の
密着性を評価するため、a−Si成膜後の成膜反応炉か
らの取り出し時に、目視にてITO膜剥離の有無を確認
した。また、密着性評価の加速試験として、各試料を水
中に12時間放置した後と、更に88時間(合計100
時間)放置した後に、それぞれ目視にてITO膜剥離の
有無を確認した。この評価結果を、ITO膜の成膜速度
と平均結晶粒径の条件と共に、表1にまとめた。
Next, in order to evaluate the adhesion of the ITO film with respect to these samples, the presence or absence of the peeling of the ITO film was visually confirmed at the time of taking out from the film forming reaction furnace after forming the a-Si film. As an accelerated test for adhesion evaluation, each sample was allowed to stand in water for 12 hours and then for another 88 hours (total 100
After standing, the presence or absence of peeling of the ITO film was visually confirmed. The evaluation results are summarized in Table 1 together with the conditions for the film formation rate of the ITO film and the average crystal grain size.

【0022】[0022]

【表1】 [Table 1]

【0023】表1においては、剥離がなかったものは○
で、剥離が認められたものは×で結果を示した。これよ
り分かるように、膜の剥離の発生すなわち密着性の良否
とITO膜の平均結晶粒径との間には対応が見られ、平
均結晶粒径が約0.025μmより大きくなることによ
り剥離の発生が抑制され、密着性が向上している。
In Table 1, those without peeling are ◯.
When the peeling was observed, the result was indicated by x. As can be seen, there is a correspondence between the occurrence of film peeling, that is, the quality of adhesion and the average crystal grain size of the ITO film, and when the average crystal grain size exceeds about 0.025 μm, peeling Generation is suppressed and adhesion is improved.

【0024】このように平均結晶粒径を0.025μm
以上とすることにより密着性が向上するが、その際の結
晶粒径のばらつきの下限としては、粒径が小さ過ぎると
表面の凹凸の形成が不十分となって応力を吸収しきれず
に剥離が発生することから、0.012μm以上である
ことが望ましい。一方、結晶粒径の上限としては、この
結晶粒径が大きくなると導電率が低くなってしまい、ま
た環境の変化に対する特性の変動が大きくなるといった
理由により、あまり大きくない方が良いことから、0.
05μm以下であることが好ましい。
Thus, the average crystal grain size is 0.025 μm.
Adhesion is improved by the above, but as the lower limit of the variation of the crystal grain size at that time, if the grain size is too small, the formation of irregularities on the surface becomes insufficient and the stress cannot be absorbed completely and peeling occurs. Therefore, 0.012 μm or more is desirable. On the other hand, as the upper limit of the crystal grain size, the larger the grain size, the lower the conductivity, and the larger the variation in the characteristics due to the change in the environment. .
It is preferably not more than 05 μm.

【0025】[0025]

【発明の効果】以上詳述したように、本発明により、I
TO膜の成膜条件、特に成膜速度を制御して平均結晶粒
径や結晶の配向性、膜表面の凹凸などを制御するという
簡便な方法で、その上に半導体膜が積層される場合にお
けるITO膜の密着性を高めることができた。
As described above in detail, according to the present invention, I
In the case where the semiconductor film is laminated on the TO film by a simple method of controlling the film forming conditions, particularly the film forming speed, to control the average crystal grain size, the crystal orientation, the film surface irregularities, and the like. The adhesion of the ITO film could be increased.

【0026】また本発明によれば、技術的な困難さや膜
形成に係るコストの増加をもたらすことなく、ITO膜
の剥離の発生を抑制できた。
Further, according to the present invention, the occurrence of peeling of the ITO film can be suppressed without causing technical difficulties and an increase in cost for forming the film.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)および(b)はX線回折測定の結果およ
び膜表面の走査型電子顕微鏡写真である。
FIG. 1 (a) and (b) are the results of X-ray diffraction measurement and scanning electron micrographs of the film surface.

【図2】本実施例に使用したイオンプレーティング装置
の概略構成図である。
FIG. 2 is a schematic configuration diagram of an ion plating apparatus used in this example.

【図3】本実施例に使用したプラズマCVD成膜反応炉
の概略構成図である。
FIG. 3 is a schematic configuration diagram of a plasma CVD film forming reaction furnace used in this example.

【符号の説明】[Explanation of symbols]

1・・・・・イオンプレーティング装置 3・・・・・蒸発源 4・・・・・高周波コイル 9、26・・高周波電源 15・・・・基体 16・・・・プラズマCVD成膜反応炉 22・・・・グロー放電用電極板 1 ... Ion plating device 3 ... Evaporation source 4 ... High frequency coil 9, 26 ... High frequency power supply 15 ... Base 16 ... Plasma CVD film forming reactor 22 ...- Glow discharge electrode plate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 透明基体上に薄膜形成手段により平均結
晶粒径が0.025μm以上となるようなITO結晶を
有する透明導電膜を形成し、該透明導電膜の上に還元性
活性種を含むプラズマにより半導体膜を形成して成る半
導体素子の製法。
1. A transparent conductive film having an ITO crystal having an average crystal grain size of 0.025 μm or more is formed on a transparent substrate by a thin film forming means, and a reducing active species is contained on the transparent conductive film. A method of manufacturing a semiconductor element formed by forming a semiconductor film with plasma.
JP5161270A 1993-06-30 1993-06-30 Manufacture of semiconductor element Pending JPH0779003A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5161270A JPH0779003A (en) 1993-06-30 1993-06-30 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5161270A JPH0779003A (en) 1993-06-30 1993-06-30 Manufacture of semiconductor element

Publications (1)

Publication Number Publication Date
JPH0779003A true JPH0779003A (en) 1995-03-20

Family

ID=15731918

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH0779003A (en)

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KR100669064B1 (en) * 1999-02-24 2007-01-15 데이진 가부시키가이샤 Transparent conductive laminate, its manufacturing method, and display comprising transparent conductive laminate
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US6617056B1 (en) 1999-02-24 2003-09-09 Teijin Ltd. Transparent conductive laminate, its manufacturing method, and display comprising transparent conductive laminate
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US6677062B2 (en) 2000-07-19 2004-01-13 Matsushita Electric Industrial Co., Ltd. Substrate with an electrode and method of producing the same
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KR20040076104A (en) * 2003-02-24 2004-08-31 액세스나노 주식회사 A film for display device coated with nano particle of indume tin oxide
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US9581875B2 (en) 2005-02-23 2017-02-28 Sage Electrochromics, Inc. Electrochromic devices and methods
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