JPH077898B2 - Phase shift circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a phase shift circuit suitable for being integrated into an IC.

[Prior Art] As a means for delaying a signal, there is a phase shift circuit. For example, in a color television receiver, a color signal is extracted from a color video signal by a bandpass filter,
When the luminance signal No. 2 is extracted by attenuating the color signal by the trap filter, the delay time of the luminance signal of the color signal becomes longer than that of the luminance signal 4. Therefore, the luminance signal is delayed by the phase shift circuit to compensate for it.

When making a circuit including a filter such as a phase shift circuit into an IC, how to incorporate the filter into the IC and reduce the number of external parts is an important issue. In general, an active filter is used when the filter is integrated into an IC. (1) The accuracy of the resistance value and the capacitance value of the capacitor is not good, and the cutoff frequency determined by the product of them varies.

(2) Since the resistance value and the capacitance value of the capacitor cannot be increased so much, it is difficult to make one with a low cutoff frequency.

There are problems such as.

Devices related to this kind of device for solving the above-mentioned problems are disclosed in, for example, JP-A-55-45224 and JP-A-55-4.
Examples include the circuit described in Japanese Patent No. 5266.

[Problems to be solved by the invention]

As described above, in order to delay a wideband signal such as a luminance signal, a wideband phase shift circuit is naturally required, and in an active filter, it is sometimes necessary to improve the high frequency performance of an amplifier circuit.

Generally, the transition frequency r, which is an index indicating the high frequency performance of a transistor, changes as shown in FIG. 2 depending on the emitter current. In order to improve the high frequency performance, the emitter current should be increased and used in a region where r can be large.

In the above-mentioned conventional technique, the time constant of the filter is determined by the product of the emitter resistance of the transistor forming the amplifier circuit and the capacitance value of the capacitor, and the variation of the capacitance value is controlled by controlling the current of the amplifier circuit. Therefore, inconvenient cases may occur in which the conditions for using the transistor do not match in the state where the high-frequency performance is improved as described above.

An object of the present invention is to eliminate the above-mentioned inconveniences and provide a phase shift circuit suitable for IC implementation.

[Means for solving problems]

To achieve the above object, in the present invention, the phase shift circuit comprises a first differential pair for converting an input signal voltage into a signal current.
The first and second transistors, the third and fourth transistors forming a second differential pair that divides the signal current flowing through the collector of the second transistor at a certain fixed ratio, and the first transistor. A load resistance connected to the collector of the transistor, and a load capacitor having one terminal connected to the collector of the fourth transistor and the other terminal supplied with a signal voltage obtained as the terminal voltage of the load resistance. , Means for controlling the current shunt ratio of the third and fourth transistors by varying the control voltage applied to the base of the fourth transistor.

[Action]

The first and second transistors that make up the first differential pair are always
_The signal current flowing in the load capacitor is shunted by the third and fourth transistors operated by the emitter current with which _T increases, and the time constant is controlled by controlling the shunt ratio. Therefore, it is possible to improve the high frequency performance of the first differential pair, which serves as an amplifier circuit, and at the same time, to compensate for variations in the capacitors.

〔Example〕

 An embodiment of the present invention will be described below with reference to FIG.

In Figure 1, resistor R ₁ to the emitter of transistor Q _1,
A resistor R ₂ is connected to the emitter of the transistor Q _{2, the} other ends of the resistors R ₁ and R ₂ are connected to a constant current source A ₁ , respectively, and the transistors Q ₁ and Q _{2 form} a differential pair. . The base of the transistor Q ₁ is the input signal Vin to the input terminal T ₁ is connected to the input terminal T ₁ is being added. The collector of the transistor Q ₁ is connected to the load resistor R ₃ whose other end is grounded and also to the base of the transistor Q ₉ . A constant current source A ₃ is connected to the emitter of the transistor Q ₉ to form an emitter follower. Further, the collector current of the transistor Q ₂ is shunted by the differential pair transistors Q ₃ and Q ₄ whose emitters are connected to the collector of Q ₂ , respectively. A bias current V _B1 is applied to the base of the transistor Q _3, a base of the transistor Q ₄ is connected to the control terminal T ₂ , and a control voltage V _C for adjusting the degree of the shunt is applied to T ₂ . The collector of the transistor Q ₄ is connected to the collector of the transistor Q ₅ and also to one terminal of the load capacitor C, and the other terminal of the capacitor C is connected to the transistor Q ₉
Connected to the emitter of. Further the collector of the transistor Q ₄ is connected to the base of the transistor Q _10, the transistors _{Q 10, Q 11, Q 12} , Q 13, the constant current source A ₄ constitute the emitter follower for DC level shifting type. The emitter of the transistor Q ₁₃ is connected to the output terminal T ₃ is connected to the base of the transistor Q _2, an output from an output terminal T ₃
Vout is taken out. The base of transistor Q ₅ is the base of the transistor Q _6, is connected to the collector, and a current mirror operation, current approximately equal to the collector current of the transistor Q ₆ flows substantially constant current to the collector of the transistor Q _5. On the other hand, the respective emitters of the transistors Q ₇ and Q ₈ are connected and also connected to the constant current source A ₂ . The current value of the constant current source A ₂ is 1/2 of the I of the current I ₀ of the constant current source A _{1 0/2}
Value. The bases of the transistors Q ₇ and Q ₈ are connected to the bases of the transistors Q ₃ and Q ₄ , respectively, and have the same current shunt function. Therefore, the collector current of the transistor Q _4, the collector current of Q ₈ , the collector current of Q ₆ , and the collector current of Q ₅ are made approximately equal.

In such a configuration, the input voltage applied to the terminal T ₁ is Vin, the output voltage of the terminal T ₃ is Vout, the alternating current flowing in the collector of the transistor Q _{2 due to} the input voltage is is, and the current due to the transistors Q ₃ and Q ₄ is is K is the shunt ratio (the ratio of Q ₄ flowing to the collector), and γ is the emitter resistance of each of the transistors Q ₁ and Q _2.
If you say e Is established, and is flows into the capacitor C, so that the terminal voltage of the capacitor C is obtained. At the same time, in the collector of the transistor Q ₁ , an alternating current having the same phase as is and having the same magnitude as is flows, and this flows in the load resistor R ₃ to extract the terminal voltage of the resistor R ₃ , which is the emitter voltage of the transistor Q ₉ . The added voltage is added to the terminal voltage of the capacitor C via the follower and the capacitor C, and the added signal is output from the terminal T ₃ via the transistors Q ₁₀ , Q ₁₁ , Q ₁₂ and Q ₁₃ to the output voltage Vou.
It is taken out as t and is also added to the base of the transistor Q ₂ to form a negative feedback loop. Here, when the angular frequency of the signal is ω, the output voltage Vout is Here, it becomes S: Laplace operator, and the transfer function H of this circuit can be calculated from Eqs. (1) and (2).
₁ (S) is calculated Becomes Where R ₃ / (2γe + R ₁ + Re) is the load resistance R ₃
The gain of the signal taken out as the terminal voltage of is shown. When this value is 0.5, the denominator numerator of the equation (3) has the same size. That is, it shows that the circuit gain is 1 regardless of the frequency of the input signal, and the phase circuit changes only the phase of the output signal with respect to the frequency. The emitter resistance γe is determined by the emitter current I _E. k: Boltzmann's constant T: absolute temperature q: electron charge, γe at room temperature with an emitter current of 100 μA
= 260Ω.

Here, the values of R ₁ and R ₂ are set sufficiently larger than the emitter resistance γe so that the gain of the signal extracted as the terminal voltage of the resistor 3 is determined by the resistors R ₁ , R ₂ and R ₃ , and the resistances R ₁ and R _{If 2} is made equal to R _E , equation (3) is almost It is represented by. When this phase shift circuit is integrated, even if the values of the capacitor C and the resistor R _E vary, the shunt ratio K of the signal current flowing through the collector of the transistor Q ₄ is controlled by controlling the control voltage V _C of the control terminal T _2. Control and K / (C ・ 2R _E )
The value of can be constant. Also the resistance R ₃
The gain of the signal extracted as the terminal voltage of R ₃ / (2 ・
The value of R _E ) varies in the same way for resistors formed on the same IC chip, so the resistance ratio remains almost unchanged.

That is, according to this embodiment, even if the values of the capacitors and the resistances are varied in the case of an IC, it can be compensated by controlling the current shunt ratio K of the transistors Q ₃ and Q ₄ , so that the current value of the constant current source A ₁ is increased. Can be selected to any value. Therefore, as shown in FIG. 2, the value of the constant current source A ₁ can be set to an emitter current value at which _T of the transistors Q ₁ and Q ₂ can be large, and the high frequency performance of the transistors Q ₁ and Q ₂ can be improved. it can.

Further, the signal obtained as the terminal voltage of the resistor R ₃ is obtained by inverting the phase by 180 degrees with respect to the input signal, and it is necessary for the phase shift circuit to invert and add the input signal to the terminal voltage of the capacitor C. . In this embodiment, the amplifier circuit that inverts the input signal and the amplifier circuit that converts the input signal into a current and extracts the current as the terminal voltage of the capacitor C are common, and the number of elements can be reduced.

Next, another embodiment of the present invention will be described with reference to FIG.

The circuit shown in FIG. 3 is a secondary type phase shift circuit in which the phase shift circuit shown in FIG. 1 is configured in two stages. The first stage circuit is the 100s,
The circuit in the second stage is given the code of the 200s, and the two digits are the same as those in the configuration of FIG. Further, the control voltage V _C for controlling the diversion ratio is common to the first and second stages, and the equal diversion ratio K is set. Further, the resistors R ₁₀₁ and R ₁₀₂ are equal to R _E1 , the resistors R ₂₀₁ and R ₂₀₂ are equal to R _E2 , and the resistors R _E1 and R _E2 are equal to each other.
Is the emitter resistance γ of the transistors Q ₁₀₁ , Q ₁₀₂ , Q ₂₀₁ , Q ₂₀₂
If the value is sufficiently larger than e, the signal voltage input from the input terminal T ₄ will be Vou the output voltage obtained from the Vin output terminal T _5.
When the circuit transfer function H ₂ (s) is calculated as t, Therefore, R in Eq. (6) is the same as explained in Fig. 1.
_When the value of ₁₀₃ / (2 · R _E1 ) is 0.5, the denominator and the numerator have the same size. In equation (6), the circuit gain is 1 with respect to the input signal frequency, and only the phase of the output signal changes. It is shown to be a secondary type phase shift circuit. Also transistor Q ₁₄
Is a base current compensation transistor for making the current mirror operation more accurate. It is obvious that the effect of the present invention is the same as that in the embodiment shown in FIG.

Further, in the equation (6), the gain of the signal taken out as the terminal voltage of the load resistor R _{103 represented} by R ₁₀₃ / (2 · R _E1 ) is M, and when the value of the gain M is other than 0.5, the phase shift circuit The circuit gain changes as follows.

First, when the gain M becomes smaller than 0.5 and M = 0, the equation (6) becomes Next to Then, when the input angular frequency ω is ω = ω ₀ , the circuit becomes a trap filter having a circuit gain of 0.

On the contrary, when the gain M becomes larger than 0.5, the circuit gain becomes large at the point where the input angular frequency ω becomes ω = ω ₀ contrary to the above description. By changing the value of the gain M, the gain in the vicinity of ω ₀ which is the natural angular frequency of the phase shift circuit can be changed. FIG. 4 shows a circuit using the phase shift circuit according to the present invention as an image quality adjusting circuit of a color television receiver utilizing this characteristic.

FIG. 4 is a block diagram showing an embodiment of a color television receiver using the phase shift circuit according to the present invention as an image quality adjusting circuit. In FIG. 4, 1 is an antenna and 2 is a broadcast signal received by the antenna 1. A tuner circuit that selects an arbitrary station and outputs an audio signal composite color video signal (hereinafter abbreviated as video signal), 3 is a switch circuit that switches an audio signal to be output, and 4 is an amplifier circuit that amplifies the audio signal,
Reference numeral 5 is a speaker for outputting voice.

Reference numerals 6 and 7 are input terminals for inputting a video signal and an audio signal from the outside of the color television receiver, and 8 is a switch circuit for switching between the video signal output from the tuner circuit 2 and the video signal input from the input terminal 6. , 9
Is an input terminal for inputting a switching signal for controlling the switch circuits 3 and 8.

10 is a bandpass filter (hereinafter abbreviated as BPF) that extracts the chroma signal from the video signal, 11 is the demodulator of the chroma signal and 3
The color demodulation circuit outputs two color difference signals R-Y, G-Y, and B-Y.

Reference numeral 12 is a trap filter that attenuates only the chroma signal from the video signal to extract the luminance signal, and 13 is a delay circuit that corrects the delay time difference caused by the difference in the processing paths of the luminance signal and the chrominance signal. The described phase shift circuit is used. 14 is an image quality adjusting circuit, 15 is an input terminal for inputting a luminance signal to the image quality adjusting circuit 14, 16 is an input terminal for inputting a control voltage Vs for adjusting the image quality, 17 is a voltage source for generating the control voltage Vs, Reference numeral 18 is an output terminal for outputting a luminance signal whose image quality is adjusted.

22 is a contrast adjustment circuit, 23 is a contrast adjustment circuit
A voltage source for generating a control voltage for controlling 22, a luminance control circuit (a circuit for adjusting the brightness) 24, a voltage source 25 for generating a control voltage for controlling the luminance control circuit 24, and 26 three color difference signals R -Y, G-Y, B-Y and a matrix circuit for outputting the three primary color signals R, G, B from the luminance signal output from the luminance adjusting circuit 24, 28 is a color cathode ray tube, 27 is a color cathode ray tube 28
Is an amplifier circuit for driving the.

Next, in the image quality adjusting circuit 14, the luminance signal input from the input terminal 15 is an amplifier circuit that converts the input signal voltage into a current.
It is supplied to one input of 20 and is also supplied to one input of an amplifier circuit 19 for voltage amplification. The other input of the amplifier circuits 20 and 19 is supplied with the same image quality adjusted luminance signal as output from the output terminal 18, and the other luminance signal of the amplifier circuit 21 which converts the input signal voltage into a current. It is also supplied to the input. The load capacitor C ₁₀₁ has one end connected to the output of the amplifier circuit 19 and the other end connected to the output of the amplifier circuit 20 and to one input of the amplifier circuit 21. The load capacitor C ₂₀₁ has one end connected to the input terminal 15 and the other end connected to the output of the amplifier circuit 21 and also to the output terminal 18. The gain of the amplifier circuit 19 is controlled by the control voltage Vs input from the terminal 16.

Image quality adjustment emphasizes the outline of the image to make it clearer,
It is a kind of lifted image by blunting the outline part,
There is a method of controlling a gain of a high frequency component included in a contour portion in a video signal. Therefore, the phase shift circuit shown in FIG. 3 is used as the image quality adjustment circuit, and the natural angular frequency ω ₀ of the phase shift circuit is set as the frequency for controlling the gain included in the contour portion in the video signal. The image quality can be adjusted by controlling the gain M described in the above. In the image quality adjusting circuit 14 shown in FIG. 4, the amplifier circuits 19 and 20 correspond to the circuits with the reference numerals of the 100th generation shown in FIG. 3, and the amplifier circuit 21 has the 200th generation shown in FIG. It corresponds to a circuit with a reference numeral. A concrete circuit of the image quality adjusting circuit 14 is shown in FIG.

FIG. 5 shows an embodiment of a concrete circuit of an image quality adjusting circuit using a phase circuit according to the present invention. The same parts as those shown in FIGS. 3 and 4 are designated by the same reference numerals.

In FIG. 5, the transistors Q ₁₅ and Q _{16 form} a differential pair, each emitter being connected to the collector of Q _101.
The current flowing to the collector of ₁₀₁ is shunted. The base of the transistor Q ₁₅ is connected to the control terminal 16, the base of the transistor Q ₁₆ is applied with the bias voltage V _B2 ,
A control voltage Vs for controlling the current shunt ratio in the transistors Q ₁₅ and Q ₁₆ is applied to ₁₆ . Also transistor Q
The collector of ₁₅ is connected to the load resistor R ₁₀₃ .

In such a configuration, the difference between the circuit shown in FIG. 3 and the circuit shown in FIG. 5 is that the signal current flowing in the collector of the transistor Q ₁₀₁ is shunted by the transistors Q ₁₅ and Q _{16 at} a certain ratio. The divided and divided signal current is
Lies in the terminal voltage of the resistor R ₁₀₃ flows to R ₁₀₃ is taken out. Assuming that the shunt ratio of the signal current flowing through the collector of the transistor Q ₁₀₁ by the transistors Q ₁₅ and Q ₁₆ (ratio of flowing into the collector of Q ₁₅ ) is m and the other conditions are the same as those described in FIG. 3, the transfer function H ₃ (S) is By varying the control voltage Vs applied from the control terminal 16 and controlling the current shunt ratio m, the gain of the signal extracted as the terminal voltage of the resistor R ₁₀₃ (m · R ₁₀₃ ) /
The value of (2 · R _E1 ) can be controlled, and according to this embodiment, the image quality can be adjusted as described above.

Further, in the circuit shown in FIG. 1, the output resistance γ _C seen from the collectors of the transistors Q ₅ and Q ₄ is ideally infinite because it is a current source. However, in reality, the output resistance γ _C decreases as the collector current increases, and the output resistance γ _C of the PNP transistor can be large, especially in the IC transistor, but the output resistance γ _C of the PNP transistor is small and is several hundred kΩ to several tens of kΩ. It drops to kΩ. In this case, as shown in FIG. 1, the signal extracted as the terminal voltage of the resistor R ₃ added to the output signal Vout via the capacitor C is determined by the product of the output resistor γ _C and the load capacitor C. It may be attenuated in a region lower than the frequency, which may cause an inconvenience that the original circuit operation cannot be obtained. In such a case, the circuit shown in FIG. 6 may be used.

In FIG. 6, Q ₂₁ is a PNP transistor, V _B3 is a bias voltage source, and the same components as those shown in FIG. 1 are designated by the same reference numerals. Transistor Q ₂₁ in FIG has a cascode connection, based Q ₂₁ are added bias voltage V _B3, the emitter of Q ₂₁ is connected to the collector of the transistor Q _5, the collector of Q ₂₁ to the transistor It is connected.

In the configuration shown in FIG. 6, assuming that the output resistance seen from the collector of the transistor Q ₂₁ is r _C and the current amplification factor is hfe, by connecting the transistors Q ₅ and Q ₂₁ in cascode, the output terminal T ₃ Q ₂₁ side impedance Z ₀
Is approximately represented by Z ₀ = hfe r _C.

Therefore, by using the cascode-connected PNP transistor as the load current source of the integrating circuit, the output impedance can be increased up to the output resistance hfe of the transistor itself. As a result, the low-frequency side operating region of the integrator circuit also increases to hfe times (when Q ₄ output resistance >> Q ₂₁ output resistance). Also, if the operating region on the low frequency side is the same, the capacitance value of the integrating capacitor can be reduced to 1 / hfe.
When converting to C, it is convenient because it is easy to incorporate a capacitor.

The operation of the circuit shown in FIG. 6 as a phase shift circuit is the same as that of the circuit shown in FIG.

〔The invention's effect〕

According to the present invention, a differential pair transistor serving as an amplifier circuit
Since it can be operated with an emitter current that increases _T, high-frequency performance can be improved. At the same time, control is performed by shunting the signal current flowing through the load capacitor against variations in the values of the capacitor and resistance that occur when integrated into an IC. Since it is possible, it becomes easy to make IC.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment according to the present invention, FIG. 2 is a graph showing a high frequency performance of a transistor, FIG. 3 is a circuit diagram showing an embodiment of a secondary phase shift circuit according to the present invention, and FIG. FIG. 5 is a block diagram showing an embodiment of a color television receiver using a secondary phase shift circuit according to the present invention as an image quality adjusting circuit. FIG. 5 is a circuit diagram showing a concrete circuit of the image quality adjusting circuit. FIG. 6 is a circuit diagram showing still another embodiment according to the present invention. T ₁ ... input terminal, T ₂ ... control terminal, T ₃ ... output terminal,
Q ₃ , Q ₄ ...... Diversion transistors.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masanori Kamiya 471 Kamono-cho, Minokamo City, Gifu Prefecture Gifu Factory, Hitachi Ltd. (56) References JP-A-55-45224 (JP, A) JP-A-SHO 55-45266 (JP, A)

Claims (1)

[Claims] 1. An emitter of a first transistor to which an input signal is supplied is connected to a first constant current source via a first resistor, and an emitter of a second transistor is connected to a first constant current source via a second resistor. And a second differential pair for shunting the collector current of the second transistor.
Third and fourth transistors forming a differential pair, a second constant current source connected to the collector of the fourth transistor, and a load resistor connected to the collector of the first transistor, A fifth transistor forming a first emitter follower connected to the collector of the first transistor; and a load capacitor connected between the emitter of the fifth transistor and the collector of the fourth transistor. A first control voltage applied to the base of the fourth transistor is made variable to control a current shunt ratio in each of the third and fourth transistors forming the second differential pair. 1 means, and a sixth transistor constituting a second emitter follower connected to the collector of the fourth transistor, the second emitter source Together with the input signal so as to obtain a signal phase-shifted from the Lower, the phase shift circuit and supplying the phase-shifted signal to the base of said second transistor.