JPH0778907A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0778907A JPH0778907A JP5222691A JP22269193A JPH0778907A JP H0778907 A JPH0778907 A JP H0778907A JP 5222691 A JP5222691 A JP 5222691A JP 22269193 A JP22269193 A JP 22269193A JP H0778907 A JPH0778907 A JP H0778907A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor
- semiconductor element
- semiconductor device
- element body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Die Bonding (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、1枚の金属支持板にト
ランジスタ、ダイオード、サイリスタなどの1種あるい
は2種以上の半導体チップの複数個を固着した半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which one or more semiconductor chips such as transistors, diodes, and thyristors are fixedly attached to one metal supporting plate.
【0002】[0002]
【従来の技術】大容量の半導体装置としては、大面積の
半導体基板に1個の素子を形成したものと、1枚の金属
支持板上に小面積の半導体チップの複数個を搭載して構
成したものとがある。後者は、大面積のシリコンウエー
ハなどを、ウエーハプロセスを終了した後に分割して複
数の小面積の半導体チップとし、その半導体チップのう
ちの特性の良好なもののみを使用するので、製造歩留ま
りが良好になるほか、2種類以上の半導体チップ、例え
ばサイリスタとフライホイールダイオードからなる回路
を1枚の支持板上に構成することを可能にする利点を有
する。2. Description of the Related Art A large-capacity semiconductor device is constructed by forming one element on a large-area semiconductor substrate and mounting a plurality of small-area semiconductor chips on one metal supporting plate. There is something I did. In the latter case, a large-area silicon wafer is divided into a plurality of small-area semiconductor chips after the wafer process is completed, and only the semiconductor chips with good characteristics are used, so the manufacturing yield is good. Besides, there is an advantage that it is possible to form a circuit composed of two or more kinds of semiconductor chips, for example, a thyristor and a flywheel diode on one support plate.
【0003】図2は、そのような半導体装置の一例で、
平坦な金属支持板2の上にトランジスタ、ダイオード、
サイリスタなどの半導体チップ1の複数個をはんだ3を
用いて固着した状態を示す。チップが高耐圧を要求され
るときには、チップの外周部に、チップの両面の間に電
圧を印加したときの空乏層の広がりを制御して耐圧を確
保するためのガードリングなどが構成されている。FIG. 2 shows an example of such a semiconductor device.
On the flat metal support plate 2, a transistor, a diode,
A state in which a plurality of semiconductor chips 1 such as thyristors are fixed using solder 3 is shown. When a chip is required to have a high breakdown voltage, a guard ring or the like is formed on the outer periphery of the chip to control the spread of the depletion layer when a voltage is applied between both sides of the chip to secure the breakdown voltage. .
【0004】[0004]
【発明が解決しようとする課題】図2のような半導体装
置において、図のA部に示すように過剰のはんだ3がは
み出し、チップ1の側面上にはい上がることがある。は
んだ3はチップ下面の電極と等電位であり、数百μm程
度のチップ厚さによって定まる数百μm程度の両面電極
間の絶縁距離がはんだ3により小さくなるため、必要な
耐圧が得られなくなるという問題があった。耐圧特性を
満足する複数個のチップを用いても、このような欠陥が
生ずると半導体装置全体で耐圧の信頼性が低くなる。In the semiconductor device as shown in FIG. 2, excessive solder 3 may protrude and rise to the side surface of the chip 1 as shown in A part of the figure. Since the solder 3 has the same electric potential as the electrodes on the lower surface of the chip and the insulation distance between the double-sided electrodes of about several hundred μm, which is determined by the chip thickness of about several hundred μm, is reduced by the solder 3, the required withstand voltage cannot be obtained. There was a problem. Even if a plurality of chips satisfying the withstand voltage characteristics are used, the reliability of the withstand voltage becomes low in the entire semiconductor device when such a defect occurs.
【0005】本発明の目的は、このような問題を解決
し、1枚の金属支持板に固着される複数の半導体素体か
らなる半導体装置の耐圧の信頼性を向上することにあ
る。An object of the present invention is to solve such a problem and improve the reliability of the breakdown voltage of a semiconductor device composed of a plurality of semiconductor elements fixed to one metal supporting plate.
【0006】[0006]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、両主面に電極を有する半導体素体の複
数個が、それぞれ全面に電極の設けられた一主面で1枚
の金属支持板にろう付けされる半導体装置において、半
導体素体の前記一主面が、金属支持板の一面に形成され
た半導体素体の主面より小さい寸法の台部の頂面にろう
付けされたものとする。そして、金属支持板の台部を囲
む凹部に、半導体素体側面の被覆もする絶縁材が充てん
されることが良く、その絶縁材がシリコーンゴムである
ことが有効である。In order to achieve the above object, the present invention provides a plurality of semiconductor elements having electrodes on both main surfaces, each of which has one main surface on which electrodes are provided. In a semiconductor device brazed to a single metal support plate, the one main surface of the semiconductor element body is a top surface of a pedestal having a size smaller than the main surface of the semiconductor element body formed on one surface of the metal support plate. Be attached. The recess surrounding the base of the metal support plate is preferably filled with an insulating material that also covers the side surface of the semiconductor element body, and it is effective that the insulating material is silicone rubber.
【0007】[0007]
【作用】金属支持板の一面に形成された台部の頂面上
に、その台部頂面より大きい寸法の半導体素体主面がろ
う付けされることにより、ろう材の半導体素体側面への
はい上がりがなく、半導体素体外周部と金属支持板の台
部を囲む凹部底面との間には、半導体素体厚さと基板突
出部高さとの和に相当する絶縁距離が得られるため、耐
圧の低下のおそれがない。さらに、金属支持板凹部に絶
縁材を充てんし、半導体素体側面の被覆もさせることに
より、耐圧の信頼性は一層向上する。Operation: By brazing the main surface of the semiconductor element body having a size larger than the top surface of the base portion on the top surface of the base portion formed on one surface of the metal supporting plate, the side surface of the semiconductor element body of the brazing material can be changed. Since there is no rising of the semiconductor element body, an insulation distance corresponding to the sum of the semiconductor element body thickness and the substrate protrusion height can be obtained between the outer periphery of the semiconductor element body and the bottom surface of the recess surrounding the base of the metal supporting plate. There is no risk of lowering the breakdown voltage. Further, by filling the concave portion of the metal supporting plate with an insulating material and covering the side surface of the semiconductor element body, the reliability of the breakdown voltage is further improved.
【0008】[0008]
【実施例】図1(a) 、(b) は、本発明の一実施例を示
す。それぞれ2000V以上の耐圧のトランジスタ、ダイオ
ードあるいはサイリスタなどの特性を示す、例えば12個
の20mm角の方形の半導体チップ1がモリブデンからなる
厚さ3mm金属支持板2にはんだなどのろう材3を用いて
3mm程度の間隔を明けて固着される。半導体チップ1の
外周部4には、チップの両面に電圧を印加したとき、所
定の耐圧を確保するためのガードリングが設けられてい
る。1 (a) and 1 (b) show an embodiment of the present invention. Each has characteristics of transistors, diodes, or thyristors with a withstand voltage of 2000 V or more. For example, twelve 20 mm square semiconductor chips 1 each having a thickness of 3 mm made of molybdenum and a brazing material 3 such as solder is used. It is fixed at intervals of about 3 mm. The outer peripheral portion 4 of the semiconductor chip 1 is provided with a guard ring for ensuring a predetermined breakdown voltage when a voltage is applied to both surfaces of the chip.
【0009】金属支持板2には、チップ1の大きさより
小さい寸法の台部6を残してチップ1をとり囲むように
深さ1.5μmの溝5を掘り、その溝によりとり囲まれた
台部6の平坦な頂面7に各半導体チップ1をろう付けす
る。これにより、外周部のガードリング部4と基板の金
属支持板2の表面との間の絶縁距離が、図2のような従
来の平坦な金属支持板に固着する場合に比べ、4倍以上
になるため、2000V以上の高電圧印加に対して安定な構
造となった。A groove 5 having a depth of 1.5 μm is formed in the metal supporting plate 2 so as to surround the chip 1, leaving a base 6 having a size smaller than the size of the chip 1, and a base surrounded by the groove. Each semiconductor chip 1 is brazed to the flat top surface 7 of the portion 6. As a result, the insulation distance between the outer peripheral guard ring portion 4 and the surface of the metal supporting plate 2 of the substrate is four times or more as compared with the case where it is fixed to the conventional flat metal supporting plate as shown in FIG. Therefore, the structure is stable against application of a high voltage of 2000 V or more.
【0010】図3は、本発明の別の実施例を示す。チッ
プ1をとり囲む金属支持板2に掘られた溝5に、チップ
1の外周部4のガードリングを覆うようにシリコーンゴ
ム8などの絶縁材を充てんしてある。これにより2000V
以上の高耐圧チップ1の耐圧の信頼性が向上した。FIG. 3 shows another embodiment of the present invention. The groove 5 dug in the metal supporting plate 2 surrounding the chip 1 is filled with an insulating material such as silicone rubber 8 so as to cover the guard ring of the outer peripheral portion 4 of the chip 1. 2000V by this
The reliability of the breakdown voltage of the high breakdown voltage chip 1 is improved.
【0011】[0011]
【発明の効果】本発明によれば、複数の半導体素体をそ
れぞれ金属支持板一面から突出した台部上に周縁部がは
り出すようにろう付けすることにより、素体上面と支持
板凹部底面との間の絶縁距離が平坦な支持板にろう付け
した場合に比して大幅に増大し、各半導体素体両面電極
間に2000V以上の高電圧を印加した場合の耐圧を確保で
きる。この結果、一部の半導体素体の耐圧低下で半導体
装置全体が不良となることがなくなる。さらに、金属支
持板台部を囲む凹部に絶縁材を充てんし、半導体素体側
面の被覆もすることにより、さらに耐圧の信頼性が向上
する。また、半導体素体の周縁部が金属基板台部からは
り出してろう付けされることにより、ろう付けの際の熱
応力がフリーになった半導体素体周縁部で緩和され、機
械的な信頼性を向上する。According to the present invention, a plurality of semiconductor elements are brazed so that their peripheral edges are projected onto a base portion projecting from one surface of a metal supporting plate, so that the upper surface of the element body and the bottom surface of the concave portion of the supporting plate. The insulating distance between and is significantly increased as compared with the case of brazing on a flat support plate, and the withstand voltage can be secured when a high voltage of 2000 V or more is applied between the double-sided electrodes of each semiconductor element. As a result, the semiconductor device as a whole does not become defective due to the breakdown voltage of some of the semiconductor elements. Furthermore, by filling the recess surrounding the metal support plate base with an insulating material and covering the side surface of the semiconductor element body, the reliability of the breakdown voltage is further improved. Also, since the peripheral edge of the semiconductor element body is protruded from the metal substrate base and brazed, the thermal stress at the time of brazing is relieved at the peripheral edge of the semiconductor element body, and mechanical reliability is improved. To improve.
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明の一実施例の半導体装置を示し、(a) は
要部断面図、(b) は平面図1A and 1B show a semiconductor device according to an embodiment of the present invention, in which FIG. 1A is a sectional view of a main part, and FIG.
【図2】従来の一実施例の半導体装置の要部断面図FIG. 2 is a cross-sectional view of a main part of a conventional semiconductor device according to an embodiment.
【図3】本発明の別の実施例の半導体装置の要部断面図FIG. 3 is a cross-sectional view of essential parts of a semiconductor device according to another embodiment of the present invention.
1 半導体チップ 2 金属支持板 3 はんだ 5 溝 6 台部 7 台部頂面 8 シリコーンゴム 1 Semiconductor Chip 2 Metal Support Plate 3 Solder 5 Groove 6 Stand 7 Stand Top 8 Silicone Rubber
Claims (3)
が、それぞれ全面に電極の設けられた一主面で1枚の金
属支持板にろう付けされるものにおいて、半導体素体の
前記一主面が、金属支持板の一面に形成された半導体素
体の主面より小さい寸法の台部の頂面にろう付けされた
ことを特徴とする半導体装置。1. A semiconductor element body having a plurality of semiconductor elements having electrodes on both main surfaces, which are brazed to a single metal supporting plate on one main surface having electrodes on the entire surfaces, respectively. A semiconductor device, wherein the one main surface is brazed to a top surface of a pedestal having a size smaller than a main surface of a semiconductor element body formed on one surface of a metal supporting plate.
体の側面の被覆もする絶縁材が充てんされた請求項1記
載の半導体装置。2. The semiconductor device according to claim 1, wherein the recess surrounding the pedestal of the metal supporting portion is filled with an insulating material that also covers the side surface of the semiconductor element body.
載の半導体装置。3. The semiconductor device according to claim 2, wherein the insulating material is silicone rubber.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5222691A JPH0778907A (en) | 1993-09-08 | 1993-09-08 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5222691A JPH0778907A (en) | 1993-09-08 | 1993-09-08 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0778907A true JPH0778907A (en) | 1995-03-20 |
Family
ID=16786408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5222691A Pending JPH0778907A (en) | 1993-09-08 | 1993-09-08 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0778907A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180286703A1 (en) * | 2017-03-31 | 2018-10-04 | Sansha Electric Manufacturing Co., Ltd. | Laminated Member |
-
1993
- 1993-09-08 JP JP5222691A patent/JPH0778907A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180286703A1 (en) * | 2017-03-31 | 2018-10-04 | Sansha Electric Manufacturing Co., Ltd. | Laminated Member |
JP2018174280A (en) * | 2017-03-31 | 2018-11-08 | 株式会社三社電機製作所 | Manufacturing method of lamination member |
US10515826B2 (en) | 2017-03-31 | 2019-12-24 | Sansha Electric Manufacturing Co., Ltd. | Laminated member |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |