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JPH0778844A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH0778844A
JPH0778844A JP22298193A JP22298193A JPH0778844A JP H0778844 A JPH0778844 A JP H0778844A JP 22298193 A JP22298193 A JP 22298193A JP 22298193 A JP22298193 A JP 22298193A JP H0778844 A JPH0778844 A JP H0778844A
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JP
Grant status
Application
Patent type
Prior art keywords
parts
pad
insulating
film
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22298193A
Other languages
Japanese (ja)
Inventor
Hirosuke Yagi
裕輔 八木
Original Assignee
Miyazaki Oki Electric Co Ltd
Oki Electric Ind Co Ltd
宮崎沖電気株式会社
沖電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures

Abstract

PURPOSE: To make an insulating film on bonding pad electrode parts provided on a semiconductor substrate flat and its thickness uniform by making the bonding pad electrode parts rugged.
CONSTITUTION: A plurality of removed parts 13 are juxtaposed in the longitudinal and lateral directions at specific intervals on pad parts 7. When the pad parts 7 are made fine fugged, the insulating film 4 thereon can be formed as if falling into the removed parts 13 so that the thickness of the insulating film 4 on a flat wiring part 3 and the one on the pad parts 7 may be make almost equal and uniform. Accordingly, the etching time for making are aperture parts 2 in the insulating film 4 on the pad parts 7 can be almost equalized with the etching time required for simultaneously etching the insulating film 4 on the other parts thereby enabling the excessive etching in the other parts to be avoided.
COPYRIGHT: (C)1995,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】この発明は、半導体装置におけるボンディングパッド電極部の構造に関するものである。 BACKGROUND OF THE INVENTION This invention relates to a structure of the bonding pad electrode portion of a semiconductor device.

【0002】 [0002]

【従来の技術】半導体装置におけるボンディングパッド電極(以下、単にパッドと称す)部の構造を図2に示し、以下に説明する。 Bonding pad electrode (hereinafter, simply referred to as pad) in the Background of the Invention Semiconductor device structure portion shown in FIG. 2 will be described below. 図2の(a)は上面図、(b)はそのA−A断面図である。 (A) is a top view of FIG. 2, (b) is its A-A sectional view.

【0003】図2において、6は半導体基板(以下、単に基板と称す)であり、その上に絶縁膜(例えば酸化膜)5が形成されている。 [0003] In FIG. 2, 6 denotes a semiconductor substrate (hereinafter, simply referred to as substrate), and on the insulating film (e.g., oxide film) 5 is formed thereon. そして、その上の所定部分に電極配線(例えばAlあるいはその合金や高融点金属など。以下、単に配線と称す)3が形成されており、その配線3の一部が外部と電気的接続(一般に金線によるボンディング)をするボンディングパッド電極(パッド) Then, the electrode wiring in a predetermined portion thereon (e.g. Al or the like alloy and refractory metal. Hereinafter simply wiring and referred) 3 is formed, on its part of the wiring 3 is an external electrical connection (typically bonding pad electrode for bonding) by gold wires (pads)
部1になっている。 It has become part 1. その上に、該パッド部1の上部に開口部2を有する絶縁膜4が設けられている。 Thereon, an insulating film 4 having an opening 2 is provided in the upper portion of the pad portion 1.

【0004】このような構造の製法は改めて説明するまでもないが、以下に簡単に述べておく。 [0004] is not even described manufacturing method of such a structure again, it should be mentioned briefly below.

【0005】まず、基板6上に絶縁膜5として例えば熱酸化法で酸化膜を形成し、その上に配線4として例えばAlあるいはその合金または高融点金属(Wあるいはその合金など)を公知の真空蒸着法やスパッタ法などで形成し、ホトリソ(ホトリソグラフィ)・エッチング技術で、フォトレジストパターンをマスクにして所定形状(図2に示すようにパッド部1を有する配線3の形状) [0005] First, the insulating film 5 on the substrate 6 to form an oxide film, for example, thermal oxidation, thereon as a wiring 4 such as Al or an alloy or a refractory metal (such as W or its alloys) the known vacuum formed by vapor deposition or sputtering, photolithography (photolithography) in etching technique (shape of the wiring 3 having a pad portion 1 as shown in FIG. 2) a predetermined shape using the photoresist pattern as a mask
にパターニングする。 It is patterned to. 次いで、前記フォトレジストを除去して、配線3上に絶縁膜4として、例えば、プラズマCVD窒化膜あるいは該窒化膜とCVD酸化膜との積層膜などをCVD法(化学気相成長法、プラズマCVD法も含む)により形成し、パッド部1の上をホトリソ・エッチング技術で開口してパッド部の開口部2を形成する。 Then, by removing the photoresist, as the insulating film 4 on the wiring 3, for example, a plasma CVD nitride film or nitride film and the CVD oxide film and the laminated film such as a CVD method (chemical vapor deposition method, a plasma CVD law is formed by including), open the top of the pad section 1 by photolithography etching technique to form the opening 2 of the pad portion.

【0006】 [0006]

【発明が解決しようとする課題】しかしながら、前述した従来の構造ではパッド部において、その上の絶縁膜の膜厚が均一でないという問題があった。 [SUMMARY OF THE INVENTION However, in the pad portion in the conventional structure described above, there is a problem that the thickness of the insulating film thereon is not uniform. つまり、図2で示すように、一般に平面的に見て四角形のパッド部1の各辺端部上でその他の部分(ロ)より高く(イ)なっていた。 That is, as shown in Figure 2, were generally higher than planarly viewed square of the other parts on each side edge of the pad portion 1 (b) is (b). これは、絶縁膜、例えばプラズマ窒化膜生成のとき、膜生成レートが下地の凹凸の度合いにより異なることに起因する。 This insulating film, for example, when the plasma nitride layer produced film generation rate is due to the different the degree of unevenness of the substrate. 例えば、プラズマCVD装置にてパッド部1の各辺端部上に生成されるプラズマ窒化膜4は、パッド部1に続く配線部3の平坦な部分の上に生成される窒化膜4の厚さ(ロ)の1.5倍の厚さ(イ)となる。 For example, the thickness of the plasma CVD plasma nitride layer 4 that is generated on each side edge of the pad unit 1 in device, the nitride film 4 is produced on the flat part of the wiring portion 3 continuing to the pad portion 1 to become 1.5 times the thickness of the (b) (i).
これは前述したように、パッド部1まで配線3の続きとして平坦な構造をしていて、パッド部1の各辺端部のみ角のある形状になっていることに起因している。 This is because, as described above, to the pad portion 1 has a planar structure as a continuation of the wiring 3 is due to the fact that a shape with a corner only each side edge of the pad portion 1. つまり、凹凸の度合いが前記パッド部の辺のみでいわば疎であるからである。 That is because the degree of unevenness is so to speak sparse only sides of the pad portion.

【0007】このため、前記絶縁膜生成後の工程であるパッド部上の開口におけるエッチングでは、前述した厚さの分の時間がかかる。 [0007] Therefore, in the etching in the openings on the pad portion is a step after the insulating film generation takes minute time in thickness as described above. 従って、その部分以外の前記絶縁膜のエッチングを同時にする場合、その部分のエッチングは過剰となり、技術的に満足できなかった。 Therefore, when the etching of the insulating film other than its portion at the same time, the etching of that portion becomes excessive, it could not be technically satisfactory.

【0008】本発明は、以上述べた不満足な点を除去するため、パッド部の構造を密な凹凸形状にすることにより、その上の絶縁膜の厚さをより平坦に均一化することを目的とする。 The present invention, in order to remove unsatisfactory points mentioned above, by the structure of the pad portion to a dense irregular shape, intended to more evenly uniform the thickness of the insulating film thereon to.

【0009】 [0009]

【課題を解決するための手段】前記目的達成のために本発明は、半導体装置におけるボンディングパッド部の構造を凹凸形状(パッド部に複数の開口部(削除部)を設ける)にして、平坦な部分の面積を少なくした、つまり、凹凸の度合いを密にしたものである。 SUMMARY OF THE INVENTION The present invention for the purpose achieve, and the structure of the bonding pad portion of the semiconductor device to irregularities (multiple openings in the pad portion provided with (deletion unit)), flat the area of ​​the portion was less, i.e., in which the degree of unevenness tightly.

【0010】 [0010]

【作用】前述したように、本発明はパッド部の構造を凹凸状にしたので、その部分において平坦な部分の面積が少なくなり、つまり凹凸の度合いが密になり、その上に生成される絶縁膜の膜厚は凹凸が少なくなり均一化される。 [Action] As described above, since the present invention has a structure of the pad portion uneven, the less area of ​​the flat portion in the portion, i.e. the degree of irregularity becomes dense, it is produced on the insulating the film thickness of the film is uniform fewer irregularities. 従って、パッド部上の絶縁膜に開口部を形成するためのエッチングの時間が短くなり、前述した他の部分に対する過剰なエッチングを行なわずにすむ。 Therefore, the time of etching for forming the opening in the insulating film on the pad portion is shortened, need without excessive etching of the other parts mentioned above.

【0011】ただ、以上述べたような凹凸が疎である場合、そこの部分で前記絶縁膜(窒化膜)がなぜ盛り上がるかは完全に解明されていない。 [0011] However, above the case mentioned above unevenness is sparse, is not completely understood the one insulating layer (nitride film) why rises there parts. おそらく窒化膜形成時のSiH 4ラジカルとNH 3ラジカルの発生量に起因するものと考えられている。 Perhaps it is believed to be due to the generation amount of SiH 4 radicals and NH 3 radical nitriding film.

【0012】 [0012]

【実施例】図1に本発明の実施例の構造を、従来例と同様図1(a)に上面図、(b)にそのB−B断面図で示し、以下に説明する。 The structure of the example of the embodiment of the present invention in FIG. 1, the conventional example and the top view in the same manner Figure 1 (a), shown in the sectional view taken along B-B (b), a described below. なお、従来例と同じ部分には同じ符号を付してある。 Incidentally, the same portions as the conventional example are denoted by the same reference numerals.

【0013】図1において、6は半導体基板(以下、単に基板と称す)であり、従来同様その上に絶縁膜(例えば酸化膜)5が形成されている。 [0013] In FIG 1, 6 denotes a semiconductor substrate (hereinafter, simply referred to as substrate), and the conventional similar that on the insulating film (e.g., oxide film) 5 is formed. そして、その上の所定部分に電極配線(例えばAlあるいはその合金や高融点金属など)3が従来同様形成されており、その配線3の一部が後述する形状のボンディングパッド電極(パッド)部7になっている。 Then, the electrode wiring in a predetermined portion of the upper (e.g. Al or an alloy or a refractory metal, etc.) 3 are conventionally similarly formed, the bonding pad electrode (pad) portion 7 of a shape portion of the wire 3 is described below It has become. その上に、該パッド部7の上部に開口部2を有する絶縁膜(従来同様窒化膜など)4が従来同様設けられている。 Thereon (such as a conventional similar nitride film) an insulating film having an opening 2 on the top of the pad section 7 4 are similarly provided conventionally.

【0014】本実施例では、前記パッド部7の形状を凹凸状、つまり、図1に示すようにパッド部に複数の削除部(いわばパッド部の複数箇所を開口削除して中抜き状にした開口部分)13が所定の間隔をおいて縦、横に並べた形状としてある。 [0014] In this embodiment, the pad portion 7 of the shape uneven, i.e., it has a plurality of deletion unit (so to speak hollowed shape a plurality of locations of the pad portion is opened remove the pad portion as shown in FIG. 1 aperture) 13 is a shape arranged vertically, laterally at predetermined intervals. なお、この削除部13の平面的に見た形は本実施例では図1(a)に示すように四角形にしているが円形でもよい。 Incidentally, plan view, form the removed portion 13 in this embodiment is a square as shown in FIG. 1 (a) may be circular. 言い換えれば、このパッド部7は前記削除部13が格子状に複数設けられているので、全体として凹凸形状となっている。 In other words, since the pad portion 7 the deletion unit 13 is provided with a plurality of the grid pattern, and has a whole irregularities. このように凹凸を特に規則正しく格子状にする必要もないが、その上に形成する絶縁膜4の厚さをできるだけ均一化するにはこのようにバランスをとった形状がよい。 This way there is no particular need to regularly lattice shape irregularities, good shape balanced in this way to as uniform as possible the thickness of the insulating film 4 formed thereon.

【0015】このようなパッド部7の削除部13の形成は、公知のホトリソ・エッチング技術でパターニングすれば容易にできることは説明するまでもない。 [0015] formation of deletion unit 13 of such pad section 7 goes without explaining that can be easily be patterned by a known photolithography etching technique.

【0016】以上のようにパッド部7を密な凹凸状にすると、その上に形成する絶縁膜4はパッド部7の前記削除部13に落ち込むように形成されるので、従来例のようにパッド部7の外辺端部で極端に厚く盛り上がるようなことはなくなり、絶縁膜4は平坦な配線部3上の厚さ(ニ)とパッド部7上の厚さ(ハ)とはほぼ等しくなる。 [0016] With the pad section 7 on the dense uneven shape as described above, since the insulating film 4 formed thereon is formed to fall in the deletion unit 13 of the pad portion 7, pads as in the prior art extremely thick rise such is no longer in the outer side end portion of the part 7, made substantially equal to the insulating film 4 has a thickness on the flat wire section 3 and (d) the thickness of the pad section 7 and (c) . つまり均一化される。 That is homogenized. 従って、パッド部7上に絶縁膜4の開口部2を形成する際のエッチングも、同時にエッチングする他の部分の絶縁膜4に必要なエッチング時間とほぼ同じでよく、前記他の部分が過剰エッチングになるようなことはない。 Thus, the etching for forming the opening 2 of the insulating film 4 on the pad section 7 also may be the substantially the same as the etching time required for an insulating film 4 of the other part to be etched at the same time, the other portion is excessively etched is not such that.

【0017】 [0017]

【発明の効果】以上説明したように、本発明によれば、 As described in the foregoing, according to the present invention,
ボンディングパッド電極部の形状を凹凸状にしたので、 Since the shape of the bonding pad electrode portion uneven,
その上に形成する絶縁膜の厚さが前述したように均一化され、従来例のように他の部分が過剰エッチングされる不具合が解消される。 The thickness of the insulating film formed thereon is made uniform as described above, a problem that the other portion as in the conventional example is excessively etched is eliminated.

【0018】また、従来例のようにパッド部上の絶縁膜が異常に厚く形成されているために引き起こされる絶縁膜ストレスによる悪影響も防止できる。 Further, it is possible to prevent adverse effects due insulating film stress caused in the insulating film on the pad portion as in the conventional example is abnormally thick.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の実施例によるボンディングパッド部構造図 Bonding pad portion structural diagram according to an embodiment of the invention, FIG

【図2】従来例のボンディングパッド部構造図 [2] Bonding pad section structure diagram of a conventional example

【符号の説明】 DESCRIPTION OF SYMBOLS

2 ボンディングパッド部開口部 3 配線 4、5 絶縁膜 6 半導体基板 7 ボンディングパッド部 Second bonding pad opening 3 wire 4,5 insulating film 6 semiconductor substrate 7 bonding pad portion

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 半導体基板上に設けられているボンディングパッド電極部を凹凸形状にしたことを特徴とする半導体装置。 1. A semiconductor device is characterized in that the irregularities bonding pad electrode portion provided on the semiconductor substrate.
  2. 【請求項2】 前記ボンディングパッド電極部の凹凸形状として、該ボンディングパッド電極部の複数箇所に開口部(削除部)を設けてあることを特徴とする請求項1 As wherein irregularities of the bonding pad electrode portions, claim 1, characterized in that are opening (deletion portion) provided at a plurality of positions of the bonding pad electrode portion
    記載の半導体装置。 The semiconductor device according.
JP22298193A 1993-09-08 1993-09-08 Semiconductor device Pending JPH0778844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22298193A JPH0778844A (en) 1993-09-08 1993-09-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22298193A JPH0778844A (en) 1993-09-08 1993-09-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0778844A true true JPH0778844A (en) 1995-03-20

Family

ID=16790932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22298193A Pending JPH0778844A (en) 1993-09-08 1993-09-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0778844A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010507022A (en) * 2006-10-20 2010-03-04 スリーエム イノベイティブ プロパティズ カンパニー The methods and articles according to it for easy cleaning substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010507022A (en) * 2006-10-20 2010-03-04 スリーエム イノベイティブ プロパティズ カンパニー The methods and articles according to it for easy cleaning substrate

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