JPH0778497A - Testing method for dynamic ram - Google Patents

Abstract

PURPOSE:To realize the shortening of a testing time without increasing external terminals by a combination in which a row address strobe signal, a column address strobe signal and a write enabling signal are combined and which is not present in a normal mode. CONSTITUTION:In a timming when the row address strobe signal RASB is fallen from a high level to a low level, the column address strobe signal CASB and the write enabling signal WEB are turned to the low level. In this way, an operating mode is identified in a timming generating circuit TG and a high level signal is supplied to a latching circuit FF. In the latching circuit, the circuit is set by the signal to make a test signal TE to be the high level and testing circuits of the output side and input side included in multiplexers MPX1, 2 and data outputting circuit DOB are made to be in operating states. Thus, the starting-up/releasing of a testing mode is made possible without increasing numbers of external control signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dynamic RAM.
Regarding the test method of (random access memory),
For example, the present invention relates to a technique effectively used for a device having a large storage capacity of about 4 Mbits.

[0002]

2. Description of the Related Art With the progress of semiconductor technology, a dynamic RAM having a large storage capacity of about 1 Mbit has been developed. The test time increases as the storage capacity increases. Therefore, a test circuit is provided inside the RAM, the same signal is written in the memory array in units of x4 bits, and any one bit of the x4 bit signals read from the memory array does not match. If there is one, it puts the output terminal in a high impedance state. If all the x4 bit read signals are high level or low level, a high level or low level signal is output from the output terminal. (Mitsubishi Electric Co., Ltd., 1985 issue "Mitsubishi Technical Report"
Vol. 59, No. 9).

[0003]

In the above test method, one empty pin of the 18-pin package is used to distinguish between the normal mode and the test mode, and the test circuit is set to the operating state. To do. Therefore, if a dynamic RAM having a large storage capacity of about 4 Mbits is mounted on the 18-pin package, the empty pins will be used as address terminals. Therefore, the test method is used. Can not.

An object of the present invention is to provide a dynamic RAM test method which realizes a reduction in test time without increasing the number of external terminals.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

In the present application, a brief description will be given to the outline of the representative one of the disclosed inventions.
It is as follows.

That is, a test of an address multiplexed dynamic RAM having a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal, and a third external terminal for receiving a write enable signal. In the method, in response to changing a signal supplied to the first external terminal from a logical high level to a logical low level while supplying a logical low level signal to the second and third external terminals, the normal operation mode is changed. A step of entering a test mode; a row address signal supplied to a row decoder in response to changing a signal supplied to the first external terminal from a logic high level to a logic low level in the test mode; The signal supplied to the second external terminal is changed from logic high level to logic low level. A plurality of memory cells to be tested based on the column address signal supplied to the column decoder in response to the change to the above, and write the data having the same logical value to the selected plurality of memory cells. A step, a row address signal supplied to a row decoder in response to changing a signal supplied to the first external terminal from a logic high level to a logic low level in the test mode, and the second external terminal. Select a plurality of memory cells to be tested based on a column address signal supplied to a column decoder in response to changing a signal supplied to the column from a logic high level to a logic low level, and select the plurality of memory cells. Steps for reading data from each cell and verifying whether the read data match When dynamic R a verification result and outputting to the external terminal
An AM test method, wherein a logical low level signal is supplied to the second external terminal and a logical high level signal is supplied to the third external terminal, and the signal is supplied to the first external terminal. A step of returning to the normal operation mode in response to changing the signal from the logic high level to the logic low level is included.

[0008]

According to the above means, the test mode can be set by the combination of the external control signals required in the normal operation. Therefore, the test time can be shortened without increasing the number of external terminals. You can

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a dynamic RA according to the present invention.
A block diagram of one embodiment of M is shown. Each circuit element and circuit block in FIG.
Although not particularly limited, the (complementary MOSFET) type semiconductor integrated circuit is formed on one semiconductor substrate such as P − type single crystal silicon by a manufacturing technique thereof.

A 1-bit memory cell MC is composed of an information storage capacitor Cs and an N-channel MOSFET Qm for address selection which is connected in series to the information storage capacitor Cs.
Information of "1" and "0" is stored in the capacitor Cs in the form of electric charges. The fixed potential VG is applied to one electrode of the capacitor Cs.
(= 1/2 Vcc) is applied.

The memory array M-ARY is of the folded bit line type, although not particularly limited thereto. The pair of rows is specifically shown in FIG.
To the pair of complementary data lines DL, DLB arranged in parallel,
The respective input / output nodes of the plurality of memory cells MC are distributed and coupled with a predetermined regularity. Here, the row active signal line (signal) is shown with B (bar) attached.

The precharge circuit PC has complementary data lines DL and D like the MOSFET Q1 shown as a representative.
N-channel type switch MOSF provided between LB
It is composed of ET. As a result of the previous read or write cycle, one potential of the complementary data line is set to the power supply voltage Vcc and the other potential is set to the ground potential Vss by the sense amplifier SA. Prior to the next cycle, the complementary data lines DL and DLB are turned on by the high level of the precharge signal PC formed by the timing generation circuit TG.
It is short-circuited through the FET Q1. As a result, the precharge level Vcc / 2 of the data lines DL and DLB is obtained.

The sense amplifier SA includes P-channel MOSFETs Q2 and Q3 and an N-channel M which are representatively shown.
It is composed of OSFETs Q4 and Q5. That is, the sense amplifier SA is a CMOS composed of MOSFETs Q2 and Q4.
Inverter and CMO consisting of MOSFETs Q3 and Q5
C configured by connecting the input and output with the S inverter to each other
It is composed of a MOS latch circuit, and its pair of input / output nodes are coupled to the complementary data lines DL and DLB. Although not particularly limited, the latch circuit is supplied with the power supply voltage Vcc through parallel P-channel MOSFETs Q6 and Q7, and the parallel N-channel MOSF.
The circuit ground voltage Vss is supplied through ETQ8 and Q9. These power switch MOSFETs Q6, Q7
, And MOSFETs Q8 and Q9 are commonly used for latch circuits provided in other similar rows in the same memory mat. In other words, the sources of the P-channel MOSFET and the N-channel MOSFET in the latch circuit in the same memory mat are commonly connected.

Complementary timing pulses φpa1 and φpa1B for activating the sense amplifier SA in the operation cycle are applied to the gates of the MOSFETs Q8 and Q6, and gates of the MOSFETs Q9 and Q7 are delayed from the timing pulses φpa1 and φpa1B. Complementary timing pulses φpa2 and φpa2B are applied. By doing so, the operation of the sense amplifier SA is 2
It is divided into stages. Timing pulse φpa1, φpa
When 1B is generated, that is, in the first stage,
Due to the current limiting action of the MOSFETs Q8 and Q6 having a relatively small conductance, the minute read voltage applied between the pair of data lines from the memory cell is amplified without undergoing an undesired level fluctuation. After the difference between the complementary data line potentials is increased by the amplifying operation of the sense amplifier SA, the timing pulses φpa2 and φp
When a2B is generated, that is, when the second stage is entered, MOSFETs Q9, Q having a relatively large conductance are generated.
7 is turned on. The amplifying operation of the sense amplifier SA is accelerated by turning on the MOSFETs Q9 and Q7. By thus performing the amplifying operation of the sense amplifier SA in two stages, high-speed data reading can be performed while preventing an undesired level change of the complementary data line.

When the potential applied from memory cell MC to data line DL is higher (lower) than precharge voltage Vcc / 2, sense amplifier SA sets the potential to power supply potential Vc.
c (ground potential Vss). As a result of the differential amplification operation of the sense amplifier SA, finally, the complementary data lines DL, D
Regarding the potential of LB, one is the power supply potential Vcc and the other is the ground potential Vss.

The row address decoder R-DCR forms a selection signal for selecting one word line to address a memory cell. That is, the row address decoder R-DCR has an internal complementary address signal ax0 supplied from a row address buffer R-ADB described later.
~ Axn-1 is decoded and word line selection timing signal φ
A predetermined word line selection operation is performed in synchronization with x. The word line selection timing signal φx is formed by the timing generation circuit TG described later.

The row address buffer R-ADB has a timing signal φar formed in the timing generation circuit TG based on the row address strobe signal RASB.
The row address signals AX0 to AXn supplied from the external terminals A0 to An are fetched in synchronism with. Address signal AX
From 0 to AXn, the row address buffer R-ADB is
An internal address signal having the same phase as the address signals AX0 to AXn and an internal address signal having the opposite phase (these are collectively referred to as internal complementary address signals ax0 to axn) are formed.
This also applies to other internal address signals in the following description and drawings.

The column switch C-SW has complementary data lines DL and DLB and common complementary data lines CD and CDB like MOSFETs Q10 and Q11 shown as representative.
Are selectively combined. These MOSFET Q10,
A selection signal from the column decoder C-DCR is supplied to the gate of Q11.

The column decoder C-DCR forms a data line selection signal for selecting one data line and supplies it to the column switch CW. That is, the column address decoder C-DCR has an internal complementary address signal ay supplied from a column address buffer C-ADB described later.
0 to ayn-1 are decoded, and a predetermined data line selection operation is performed in synchronization with the data line selection timing signal φy.

The column address buffer C-ADB has a timing signal φ generated in the timing generation circuit TG based on the column address strobe signal CASB.
The column address signals AY0 to AYn supplied from the external terminals A0 to An are fetched in synchronization with ac. The column address buffer CA from the address signals AY0 to AYn
DB forms internal complementary address signals ay0 to ayn.

In this embodiment, although not particularly limited,
The moly array M-ARY consists of four. Each memory array
B) Each has a storage capacity of about 1 Mbit.
To be done. Therefore, the dynamic RAM of this embodiment is
Has a large storage capacity of about 4 Mbits in total.
To be Although not particularly limited, the above four memory arrays
4 pairs of complementary data lines corresponding to a are set as one set, and
It is made to correspond to the data line selection signal. The above four pairs of complementary data
The data line runs vertically through the column switch circuit C-SW.
4 pairs of common complementary data lines running parallel to each otherCD0,CD
1,CD2 andCDCombined with 3. In addition, non-inverted common
Align the data line CD0 with the inverted common data line CD0B
Common complementary data lineCDRepresented as 0.

Complementary address signals ax0-axn, ay0
Each specific bit of ayn to ayn, for example, the most significant bit signals axn and ayn are supplied to the decoder circuit DEC. The decoder circuit DEC forms a selection signal supplied from the signals axn and ayn to multiplexers MPX1 and MPX2 provided in an input circuit and an output circuit of a signal described later.

[0023] the common complementary data lines CD 0~ CD 3 is,
Each is coupled to the input terminals of main amplifiers MA0-MA3. These main amplifiers MA0~MA3 amplifies the signal of the common complementary data lines CD 0 to CD 3 is in the operating state by not the main amplifier operation timing signal (shown formed by the timing generator TG. These main amplifiers MA0 The complementary output signals of -MA3 are multiplexer MPX1 which is an output selection circuit controlled by the selection signal formed by the decoder circuit DEC.
Through one input terminal of the data output circuit DOB. The multiplexer MPX1 receives the decoder circuit DE during the normal operation in which the test signal TE is at the low level.
According to the output signal of C, the output signals of the main amplifiers MA0 to MA3 are alternatively selected. Multiplexer MPX1
The one complementary signal selected by is transmitted to the input terminal (one input terminal of the data output circuit DOB) of the output circuit OC forming the data output circuit DOB. The output circuit OC is activated by the timing signal φrwB, and the input signal is amplified and sent to the external terminal Dout.
As a result, the read operation is performed in units of 1 bit. The timing signal φrwB is generated in the timing control circuit TC during the read operation in which the write enable signal WEB is set to the high level. In the write operation, the output circuit OC, that is, the data output circuit D
The output of OB is brought to a high impedance state by the signal φrwB.

[0024] the common complementary data lines CD 0~ CD 3 is,
It is coupled to the output terminal of the data input circuit DIB via the multiplexer MPX2 as the input selection circuit. The multiplexer MPX2 is in normal operation, it is controlled by a selection signal formed by the decoder circuit DEC, transmitted to the common complementary data lines CD 0 to CD 3 which alternatively corresponding complementary output signal of the data input circuit DIB .
As a result, the write operation is performed in units of 1 bit. The data input circuit DIB has a timing signal φrw.
By being operational, transmitting the write signal supplied from an external terminal Din to the pair of common complementary data lines CD 0 to CD 3 which corresponds via the multiplexer MPX2. The data input circuit DIB is activated by the timing signal φrw and transmits the write signal supplied from the external terminal Din to the corresponding pair of common complementary data lines CD 0 to CD 3 via the multiplexer MPX2.
As a result, the write operation is performed in units of 1 bit. The timing signal φrw is generated in the timing generation circuit TG after the operation timing signal of the main amplifier MA, although it is not particularly limited in the write operation in which the write enable signal WEB is low level. In the read operation, the data input circuit DIB
The output of is brought to a high impedance state by the signal φrw.

The timing generation circuit TG has three external control signals RASB (row address strobe signal) and CA.
Upon receiving SB (column address strobe signal) and WEB (write enable signal), the above various timing signals necessary for the memory operation are formed and transmitted.

In this embodiment, a test circuit is incorporated in order to shorten the test time of the dynamic RAM having a large storage capacity as described above.

The test circuit on the data input side is included in the multiplexer MPX2 in this embodiment. In the test period or test operation of the test signal TE is at a high level, the test circuit conveys a write signal supplied from an external terminal Din to all selected multiplexer MPX2 to the common complementary data lines CD 0 to CD 3. As a result, the same signal is simultaneously written in the four memory cells in the selected state of the memory array M-ARY. That is, in the test mode, it is apparently 4
Writing is done in bit units.

This test circuit is, for example, a switch circuit (for example, M, which is provided in parallel with each unit circuit of the multiplexer MPX2 and which conducts at a high level of the test signal TE).
OSFET). Moreover, in the test mode, each unit circuit of the multiplexer MPX2 may be in a non-operating state.

The test circuit on the data output side is included in the multiplexer MPX1 and the data output circuit DOB. In the test period or the test operation in which the test signal TE is at the high level, the test circuit of the multiplexer MPX1 sets all the multiplexer MPX1 to the selected state and transmits the output signals of the main amplifiers MA0 to MA3 to the determination circuit JC.

This test circuit is, for example, a switch circuit (for example, M, which is provided in parallel with each unit circuit of the multiplexer MPX1 and which conducts at a high level of the test signal TE).
OSFET). In the test mode, each unit circuit of the multiplexer MPX1 is in a non-operating state, and the output of the multiplexer MPX1 to the output circuit OC is in a high impedance state.

The judgment circuit JC is a test circuit included in the data output circuit DOC and constitutes the data output circuit DOC. The determination circuit JC is activated by the test signal TE in the test mode and is not particularly limited.
Receiving the output signals of the respective main amplifiers MA0 to MA3, detecting (determining) the coincidence / non-coincidence thereof, forming an output signal according to the detection result and transmitting the output signal to the external terminal Dout through the output circuit OC. As a result, the read operation can be performed in units of 4 bits.

Although not particularly limited, the judgment circuit JC is composed of an exclusive OR (or NOR) circuit. Outputs of main amplifiers MA0 and MA1 and main amplifier MA2
And the outputs of MA3 are compared in the first and second exclusive OR circuits, respectively, and further the first and second exclusive OR circuits are provided.
The outputs of the circuits are compared in a third exclusive OR circuit. The determination circuit JC sends an output signal based on the output of the third exclusive OR circuit to the output circuit OC. As a result, the output circuit OC forms a high-level or low-level output signal if the 4-bit read signals from the main amplifiers MA0 to MA3 match at high level or low level. If even one bit of the read signal consisting of 4 bits does not match, the output terminal Do
Set ut to high impedance.

When a defect or an error that inverts the stored data occurs in all the 4-bit memory cells, it is determined that there is no defect or error, and a high level or a low level is output. Therefore, it is desirable to hold the write data as an expected value in the tester and compare the expected value with the read signal.

The activation and deactivation of the test circuit as described above are
The operation mode identification output included in the timing generation circuit TG is controlled by the test signal TE obtained from the output of the latch circuit FF which is set / reset. For example, if the test signal TE is at high level, each of the test circuits is activated, and if the test signal TE is at low level, each of the test circuits is deactivated. As a result, the test mode and the normal mode are switched.

The activation / cancellation of the test mode will be described below with reference to the timing chart shown in FIG.

At the timing when the row address strobe signal RASB falls from the high level to the low level, the column address strobe signal CASB and the write enable signal WEB are set to the low level. The timing generation circuit TG identifies this and supplies a high level signal to the latch circuit FF. As a result, the latch circuit FF is set and the test signal TE is set to the high level.
That is, only the test mode is set in this memory cycle TEST.

For example, when the dynamic RAM has an internal refresh circuit of CAS before RAS refresh system, the address strobe signal RAS is used.
Due to the relationship between B and CASB, the refresh operation is performed in parallel with the setting of the test mode. The parallel setting of the test mode and the refresh mode may be avoided by prohibiting the refresh mode by the low level of the write enable signal WEB.

For the write / read operation for the actual test, the signals RASB and CASB are once set to the high level to put the dynamic RAM in the reset state. After this, normal mode (normal read / write operation)
Is done. The row address strobe signal RASB is set to the low level to capture the row address signals AX0 to AXn, and then the column address strobe signal CASB.
To low level and the column address signal AY is taken in. After the signal φar, the signals φx and φpa (φpa1
And φpa1B, φpa2 and φpa2B) and the operation signal of the main amplifier are sequentially generated at a predetermined timing. On the other hand, the signal φy is generated after the signal φac. As a result, the address signals ax0 to axn-1 and a
four memory cells corresponding to y0~ayn-1 is connected to the common data line CD 0 to CD 3.

At this time, since the test data is written, the write enable signal WEB is set to the low level at the timing shown. The signal φr generated by this
w and φrwB activate the data input circuit DIB and deactivate the output circuit OC. Test signal TE
There so high, complementary signal corresponding to the signal supplied to the external terminal Din is, from the data input circuit DIB, through multiplexer MPX2 which is all selected, is transmitted to the common data line CD 0 to CD 3. Thereby, one data is written in four memory cells. That is, apparently, writing is performed in units of 4 bits. The potential difference of the complementary signals due to the operation of the main amplifier is, for example, about 200 mV, and that of the data input circuit DIB is as large as about 5V. Therefore, the data of the external terminal Din is written in the memory cell regardless of the operation of the main amplifier.

Next, the test data written in the memory cell is read.

As described above, the address signals ax0 to axn-1 and ay0 to ayn are set in the normal mode.
The four memory cells corresponding to -1 are common data lines CD
0 to CD3 are connected.

At this time, the write enable signal WEB is set to the high level as shown by the dotted line in FIG. 1 for reading the test data. The signals φrw and φrwB thus generated make the data input circuit DIB inactive and the output circuit OC active. Since the test signal TE is high level, the multiplexer MPX1
Transmits the output signals of the main amplifiers MA0 to MA3 to the judgment circuit JC and puts the alternative output in the high impedance state. Based on the high level of the test signal TE, the determination circuit determines whether the 4-bit signals match.
In response to this, the output circuit OC sets the external terminal Dout to a high level, a low level, or a high impedance state. As a result, it is apparent that reading is performed in units of 4 bits. Further, it is possible to know whether or not there are defective bits in the selected four memory cells.

The memory cycle TEST with the test signal TE at the high level is not particularly limited, but is repeatedly performed without setting the test signal TE at the low level. After writing the test data in units of 4 bits, reading may be repeated. Further, after writing test data to all bits or all bits of one memory array, data of these bits may be read.

After the test is completed, the test mode is released. Therefore, at the timing when the row address strobe signal RASB falls from the high level to the low level, the column address strobe signal CASB and the write enable signal WEB are set to the low level and the high level, respectively. The timing generation circuit TG identifies this and supplies a low level signal to the latch circuit FF. As a result, the latch circuit FF is reset and the test signal T
E is set to low level. That is, in this memory cycle RESET, only the test mode is released.

For example, when the dynamic RAM has an internal refresh circuit of the CAS before RAS refresh system, the address strobe signal RASB is used.
And CASB, the refresh operation is performed in parallel with the release of the test mode.

As a result, the test signal TE can be set to the low level, and the subsequent operation can be set to the normal mode. Therefore, the signals RASB and CASB are set to the high level, and the dynamic RAM is reset.

The effects obtained from the above embodiment are as follows.

(1) By combining the row address strobe signal, the column address strobe signal, and the write enable signal which are not in the normal mode, the test mode can be activated / released without increasing the number of external control signals.

(2) By the above (1), a dynamic RAM having a large storage capacity of about 4 Mbits can be accommodated in an 18-pin package. As a result, it is possible to add a test function and achieve consistency with a dynamic RAM having a storage capacity of 1 Mbit.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, an address signal can be added to the combination of the signals RASB, CASB and WEB to set and release the test mode.

As indicated by the dotted line in FIG. 2, the latch circuit FF
Is supplied with a signal ai from a specific address input external terminal Ai. The timing generation circuit TG sends a one-shot pulse for the column address strobe signal CASB and the write enable signal WEB according to the low level at the timing when the row address strobe signal RASB falls from the high level to the low level. The latch circuit FF takes in a signal from a specific address terminal at that time in response to the one-shot pulse. For example, as shown in FIG. 3, when the signal supplied from the address terminal Ai is at high level, the test mode is set, that is, the test signal TE is set at high level. The signal ai is not particularly limited, but the row address buffer R
-Supplied from ADB.

After the end of the memory cycle SET for setting the test mode, the test cycle TEST is repeated.

After the test is completed, the memory cycle RESET for releasing the test mode is performed as follows.
The timing generation circuit TG, as shown in FIG. 3, has the same signals RASB, CASB, WEB as the memory cycle SET.
One shot pulse is transmitted according to the combination of. The latch circuit FF fetches the low level signal of the address terminal Ai in response to this one shot pulse. As a result, the test signal TE is set to the low level. That is, the test mode is released.

In addition to starting / releasing the test mode, for example,
In the data output circuit DOB, the output signals that do not coincide with each other have a high impedance and an intermediate level (a potential intermediate between the power supply voltage Vcc and the ground potential Vss of the circuit, 1/2 Vcc).
One output function may be provided and selected. By adding the selection function of the above output functions, it is possible to switch the mismatch output signals according to the tester used. For example, dynamic RAM
Is mounted on a memory board, the output terminal Dout is connected by a data bus on the board in a wired OR configuration. Since the signal in the previous operation cycle remains on this data bus, it is difficult to identify if the mismatch output is sent by the output high impedance. Therefore, in the test of the dynamic RAM on the memory board, the intermediate level output may be switched.

The output function can be selected by using the address signal. That is, the memory cycle S of FIG.
At ET, as shown by the dotted line, the signal (address signal) given to the external terminal Ai-1 is latched by the latch circuit (not shown). The signal of the external terminal Ai-1 is valid only when the signal of the external terminal Ai is at the high level in the memory cycles SET and RESET. When the output of the latch circuit is high level and low level, the output circuit OC sets the mismatch signal to high impedance and intermediate level, respectively.

To select the output function of the data output circuit DOB, the output section at the final stage of the output circuit OC selects the power supply voltage Vcc.
And the first and second N-channel MOSFETs connected between the ground potential Vss and the external terminal Dout are as follows.

At the time of output in the normal mode, the first circuit in the output circuit OC supplies complementary signals to the gates of the first and second MOSFETs. The first circuit is the test signal TE
Are set to a non-operating state and an operating state, respectively. When the coincidence signal (high level or low level) is output in the test mode, the second circuit in the output circuit OC supplies complementary signals to the gates of the first and second MOSFETs. On the other hand, since the test modes do not match each other, the third and fourth circuits output the output circuit OC.
It is provided inside. The third circuit supplies a low level signal to the gates of the first and second MOSFETs when the mismatch signal is input. This allows two output MOSFE
T is turned off, and the external terminal Dout enters a high impedance state. The fourth circuit supplies a high level signal to the gates of the first and second MOSFETs when the mismatch signal is input. As a result, the two output MOSFETs are turned on, and the external terminal Dout is connected to the two output MOSFETs.
Potential according to the conductance (gm) of, for example, 1/2
It becomes the Vcc potential.

In practice, the second and third circuits and the second and fourth circuits are each configured as one circuit. These circuits have external terminals A when the test signal TE is at high level.
According to the signal i-1, either one of them is brought into the operating state.

Although not particularly limited, the address terminal Ai is a terminal for supplying the most significant bit of the address signal, for example,
The terminal A10 is used in a 1 Mbit DRAM. That is, the terminal Ai is the terminal An that supplies the internal signal axn in this embodiment. By doing this,
It is easy to change the function of the chip. For example, when the DRAM chip of 1 Mbit has a configuration of 256 kwords × 4 bits, the terminal A10 becomes unnecessary. If the present invention is applied to this case, the terminal A10 can be used as a terminal only for mode designation without any particular change. At this time, the terminal A10 is in a high impedance state, and when it is at a low level, it is at an intermediate level.

The output function depends on the signal at the terminal Ai-1.
It may be selected as follows. That is, the terminal Ai-1
When a high level signal is applied to the external terminal Dout, one of a high level, a low level and a high impedance (or an intermediate level) is supplied to the external terminal Dout. When a low-level signal is given, a high-level signal as a match signal and a low-level signal as a mismatch signal are supplied to the external terminal Dout.

By combining the address signal with the row address strobe signal, the column address strobe signal, and the write enable signal, it is possible to easily activate / cancel the test mode and add a test function having a plurality of modes.

Instead of the address terminals Ai and Ai-1,
The input terminal Din or the output terminal Dout may be used.

The test mode may be released by setting only the row address strobe signal RASB to the low level in one memory cycle.

The latch circuit FF is not particularly limited, but may be composed of a binary counter circuit using a master / slave flip-flop circuit. At the timing when the row address strobe signal RASB falls from the high level to the low level, the column address strobe signal CASB and the write enable signal WEB are set to the low level and the timing generating circuit TG supplies one shot pulse, whereby the counter circuit is stepped up. It The test mode or the normal mode is selected according to the output of the counter circuit. In this case, it is desirable that the counter circuit is configured so as to be in either the test mode or the normal mode when the power of the dynamic RAM is turned on.

Dynamic RAM to which the present invention is applied
May have a nibble mode function of serially outputting signals read in parallel from the memory array in units of a plurality of bits by a signal changed in synchronization with the column address strobe signal. In this case, the address signal supplied to the decoder circuit DEC of FIG. 2 may be changed by the shift register or the address counter circuit. Further, the specific configuration of the memory array M-ARY is to reduce the number of memory cells coupled to the word line and / or data line to increase the speed and to secure a level margin of a read signal from the memory cell. Further, it may be composed of a plurality of memory mats.

The number of memory cells selected by the addressing of the memory array, in other words, the number of common complementary data lines is 8 bits in addition to the above 4 bits.
Any number of bits may be used, such as 16 bits. Furthermore, the present invention may be applied to a dynamic RAM having a storage capacity of about 1 Mbits or 256 kbits, and when a vacant pin occurs, it may be used for another operation mode.

The present invention can be widely used for a dynamic RAM containing a test circuit.

[0069]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the combination of the row address strobe signal, the column address strobe signal, and the write enable signal, which is not in the normal mode, is used to activate / deactivate the test mode without increasing the number of external control signals.
It will be possible to cancel.

[Brief description of drawings]

FIG. 1 is a timing chart for explaining an embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

FIG. 3 is a timing chart for explaining another embodiment of the present invention.

[Explanation of symbols]

SA ... sense amplifier, M-ARY ... memory array, C
-SW ... Column switch circuit, R-DCR ... Row address decoder, C-DCR ... Column address decoder, MA0-MA3 ... Main amplifier, MPX1, 2 ...
Multiplexer, DIB ... Data input circuit, DOB ...
Data output circuit, TG ... Timing generation circuit, FF ...
Latch circuit, TC ... Test control circuit, C-ADB ... Column address buffer, R-ADB ... Row address buffer, JC ... Judgment circuit, DEC ... Decoder

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G11C 11/401 G11C 11/34 371 E (72) Inventor Katsutaka Kimura 1-chome, Higashi Koikeku, Kokubunji, Tokyo No. 280, Central Research Laboratory, Hitachi, Ltd.

Claims (2)

[Claims] 1. A first for receiving a row address strobe signal.
In a method of testing an address multiplexed dynamic RAM having an external terminal, a second external terminal for receiving a column address strobe signal, and a third external terminal for receiving a write enable signal, a logic is provided for the second and third external terminals. The step of entering the normal operation mode from the test mode in response to changing the signal supplied to the first external terminal from the logic high level to the logic low level while supplying the low level signal, and entering the test mode In this state, the row address signal supplied to the row decoder in response to changing the signal supplied to the first external terminal from the logical high level to the logical low level, and the signal supplied to the second external terminal from the logical high level. Columns supplied to the column decoder in response to changing to logical low level Selecting a plurality of memory cells to be tested based on the address signal and writing data having the same logical value to the selected plurality of memory cells; and the first mode in the test mode. In response to changing the signal supplied to the external terminal from the logical high level to the logical low level, the row address signal supplied to the row decoder and the signal supplied to the second external terminal are changed from the logical high level to the logical low level. Accordingly, a plurality of memory cells to be tested are selected based on the column address signal supplied to the column decoder, and data is read from each of the selected plurality of memory cells. A die including the steps of verifying whether they match and outputting the verification result to the external terminal. A method for testing a Mick RAM, comprising: supplying a logic low level signal to the second external terminal and a logic high level signal to the third external terminal while supplying the logic external high level signal to the first external terminal. A method of testing a dynamic RAM, comprising the step of returning to the normal operation mode in response to changing a signal to be applied from a logic high level to a logic low level. 2. A first for receiving a row address strobe signal.
In a method of testing an address multiplexed dynamic RAM having an external terminal, a second external terminal for receiving a column address strobe signal, and a third external terminal for receiving a write enable signal, a logic is provided for the second and third external terminals. The step of entering the normal operation mode from the test mode in response to changing the signal supplied to the first external terminal from the logic high level to the logic low level while supplying the low level signal, and entering the test mode In this state, the row address signal supplied to the row decoder in response to changing the signal supplied to the first external terminal from the logical high level to the logical low level, and the signal supplied to the second external terminal from the logical high level. Columns supplied to the column decoder in response to changing to logical low level Selecting a plurality of memory cells to be tested based on the address signal and writing data having the same logical value to the selected plurality of memory cells; and the first mode in the test mode. In response to changing the signal supplied to the external terminal from the logical high level to the logical low level, the row address signal supplied to the row decoder and the signal supplied to the second external terminal are changed from the logical high level to the logical low level. Accordingly, a plurality of memory cells to be tested are selected based on the column address signal supplied to the column decoder, and data is read from each of the selected plurality of memory cells. A die including the steps of verifying whether they match and outputting the verification result to the external terminal. A method for testing a Mick RAM, wherein a signal supplied to the first external terminal is changed from a logical high level to a logical low level when a logical high level signal is supplied to the second and third external terminals. A method of testing a dynamic RAM, comprising the step of returning to the normal operation mode accordingly.