KR950004625B1 - Method of testing dynamic ram - Google Patents

Abstract

No content.

Description

How to Test Dynamic RAM

1 is a timing diagram for explaining an embodiment of the present invention.

2 is a block diagram showing one embodiment of the applied dynamic RAM of the present invention.

3 is a timing diagram for explaining another embodiment of the present invention.

The present invention relates to a test method of a dynamic RAM (random access memory), and relates to a technique effective for use in, for example, having a storage capacity such as about 4 M bits.

With advances in semiconductor technology, dynamic RAMs with a storage capacity of about 1 Mbit have been developed. According to such atmospheric storage capacity increase, the test time increases. Therefore, if a test circuit is provided inside the RAM, the same signal is written to the memory array in units of x4 bits, and if any of the x4 bits signals read from the memory array match any one bit, the output terminal. This is to make high impedance state. In addition, if the read signals of the 4 bits are high level or low level, a high level or low level signal is outputted from the output terminal (Mitsubishi Denki Co., Ltd., 1985, Mitsubishi Kibo Vol 59, No9). .Reference).

In the test method, identification of the normal mode and the test mode is performed by using a spare pin of one of the 18-pin packages, and the test circuit is put into an operating state. Therefore, when a dynamic RAM having a storage capacity equal to about 4 M bits is to be mounted in the 18 pieces package, the spare pin is used as an address terminal, and thus the test method cannot be used.

SUMMARY OF THE INVENTION An object of the present invention is to provide a test method for a dynamic RAM in which test time is shortened without increasing the number of external terminals.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

The test method of the dynamic RAM disclosed herein is as follows.

(1) row address strobe First external terminal to receive signals, column address strobe Second external terminal to receive signal and light enable A test method of an address multiplexed dynamic RAM having a third external terminal receiving a signal, wherein the row address strobe signal is high level to low level when both the column address strobe signal and the write enable signal are low level. The step of changing from the normal operation mode to the test mode, the step of writing data of the same value to several memory cells in the dynamic RAM in the test mode, and the data read from the multiple memory cells coincide with each other. Detecting whether or not there is a match and outputting the result to the outside of the dynamic RAM.

(2) In the above configuration (1), the test is performed by changing the row address strobe signal from high level to low level when the column address strobe signal is low level and the write enable signal is high level. And testing the dynamic RAM in a normal mode.

(3) In the above configuration (1), the row address strobe signal is changed from a high level to a low level when the column address strobe signal and the write enable signal are both at a high level. A method of testing a dynamic RAM comprising a step of making a normal operation mode.

According to the above method, the test mode can be set by the combination of the external control signals required in the normal operation, so that the test time can be shortened without increasing the number of external terminals.

EXAMPLE

2 shows a flowchart of one embodiment of a dynamic RAM according to the present invention. Each circuit element and circuit block in the same drawing are formed on one semiconductor substrate such as p-type polycrystalline silicon, although not particularly limited by the manufacturing technology of a known CMOS (complementary MOSFET) type semiconductor integrated circuit.

The one-bit memory cell MC is composed of the information storage capacitor Cs and the n-channel MOSFET Q, m for address selection connected thereto, and the logic " 1 " and " 0 " information are stored in the capacitor Cs in the form of charge. A fixed potential VG (= 1/2 Vcc) is applied to one electrode of the capacitor Cs.

The memory array M-ARY is not particularly limited but is in a folded bit line manner. Figure 2 specifically shows its pair of rows. One pair of parallel complementary data lines DL, Each input / output node of several memory cells MC is distributed and combined with a predetermined regularity.

The precharge circuit PC has a complementary data line DL, like the MOSFET Q1 shown as a representative. It consists of an n-channel type switch MOSFET provided in between.

As a result of the previous read or write cycle, the sense amplifier SA causes the potential of one of the complementary data lines to be the power supply voltage Vcc and the other potential to the ground potential Vss.

Prior to the next cycle, by the high level of the precharge signal PC formed in the timing generation circuit TG, the complementary data line DL, Is shorted through MOSFET Q1. Thereby, the data line DL, A precharge level of Vcc / 2 is obtained.

The sense amplifier SA is composed of p-channel MOSFETs Q2, Q3 and n-channel MOSFETs Q4, q5 shown as representative. That is, the sense amplifier SA is composed of a CMOS latch circuit configured by combining inputs and outputs of a CMOS inverter composed of MOSFETs Q2 and Q4 and a CMOS inverter composed of MOSFETs Q3 and Q5. The pair of input / output nodes comprise the complementary data line. DL, Is coupled to The latch circuit is not particularly limited, but the supply voltage Vcc is supplied through the p-channel MOSFETs Q6 and Q7 in parallel, and the ground potential Vss of the circuit is supplied through the n-channel MOSFETs Q8 and Q9 in parallel. These power switch MOSFETs Q6, Q7 and MOSFETs Q8, Q9 are commonly used for the latch circuits provided in other similar rows in the same memory mat. In other words, each source is commonly connected to a p-channel MOSFET in a latch circuit in the same memory mat.

The gates of the MOSFETs Q8 and Q6 have complementary timing pulses Фpa1, which activate the sense amplifier SA in an operating cycle. Is applied, and the timing pulses Фpa1, Delayed complementary timing pulse Фpa2, Is applied. In this way, the operation of the sense amplifier SA is divided into two stages. Timing pulse Фpa1, Is generated, i.e., in the first step, the micro read voltage applied between the pair of data lines from the memory cell due to the current limiting action by the MOSFETs Q8 and Q6 having relatively small conductance is undesirably level shifted. Amplified without receiving. After the difference of the complementary data line potential is increased by the amplification operation in the sense amplifier SA, timing pulses Φpa2, Is generated, that is, when entering the second stage, MOSFETs Q9 and Q7 having relatively large conductances are turned on. The amplification operation of the sense amplifier SA is accelerated by turning on the MOSFETs Q9 and Q7. By performing the amplification operation of the sense amplifier SA in two steps as described above, it is possible to execute a high-speed read of data while preventing an undesirable level change of the complementary data line.

When the potential applied to the data line DL in the memory cell MC is higher (lower) than the precharge voltage Vcc / 2, the sense amplifier SA sets the potential as the power supply voltage Vcc (ground potential Vss). As a result of the differential amplification operation of the sense amplifier SA, the complementary data line DL, The potential of is the power supply voltage Vcc on one side and the ground potential Vss on the other.

The row address decoder R-DCR forms a selection signal for selecting one word line, and performs addressing of the memory cells. That is, the row address decoder R-DCR decodes the internal complementary address signals ax0 to ax-1 supplied from the row address buffer R-ADB described below, and selects a predetermined word line in synchronization with the word line selection timing signal Фx. Run

This word line selection timing signal Фx is formed by the timing circuit TG described next. Row address buffer R-ADB is a row address strobe signal In response to this, the row address signals AX0 to AXn supplied from the external terminals A0 to An are closed in synchronization with the timing signal Фar formed in the timing generation circuit TG. In the address signals AX0 to AXn, the row address bus R-ADB forms the address signals AX0 to AXn and the in-phase internal address signal and the inverted internal address signal (together referred to as the internal complementary address signals ax0 to axn).

This also applies to other internal address signals in the following description and drawings.

The column switches C-SW are complementary data lines DL, and common complementary data lines CD, like MOSFETs Q10 and Q11, which are shown as representative. Optionally combine The select signals from the column decoder C-DCR are supplied to the gates of these MOSFETs Q10 and Q11.

The column decoder C-DCR forms a data line selection signal for selecting one data line and supplies it to the column switch C-SW. That is, the column address decoder C-DCR decodes the internal complementary address signals ay0 to ayn-1 supplied from the column address buffer C-ADB described below, and selects a predetermined data line in synchronization with the data line selection timing signal Фy. Run

Column address buffer C-ADB is the column address strobe signal In response to this, the column address signals AY0 to AYn supplied from the external terminals A0 to An are fetched in synchronization with the timing signal Фac formed in the timing generation circuit TG. The column address buffer C-ADB forms the internal complementary address signals ay0 to ayn from the address signals AY0 to AYN.

This embodiment is not particularly limited, but there are four memory arrays M-ARY. Each memory array will each have a storage capacity of about 1M bits. Thus, the dynamic RAM of this embodiment has a storage capacity equal to about 4 M bits as a whole. Although not particularly limited, four pairs of complementary data lines corresponding to the four memory arrays are formed into one set, and correspond to one data line selection signal. The four pairs of complementary data lines are coupled to four pairs of common complementary data lines CD0, CD1, CD2 and CD3 extending in parallel in the longitudinal direction via the column switch circuit C-SW. Also, the non-inverted common data line CD0 and the inverted common data line Are summed up as a common complementary data line CD0.

The specific bits of the complementary address signals ax0 to axn and ay0 to ayn, for example, the signals axn and ayn of the most significant bit, are supplied to the decoder circuit DEC. This decoder circuit DEC forms the selection signals supplied to the multiplexers MPX1 and MPX2 provided in the input circuits and output circuits of the signals described below in the signals axn and ayn, respectively.

The common complementary data lines CD0 to CD3 are respectively coupled to input terminals of the main amplifiers MA0 to MA3. These main amplifiers MA0 to MA3 are brought into operation by a main amplifier operation timing signal (not shown) formed by the timing generator circuit TG, and amplify the signals of the common complementary data lines CD0 to CD3. The complementary output signals of these main amplifiers MA0 to MA3 are transmitted to one input terminal of the data output circuit DOB through the multiplexer MPX1, which is an output selection circuit controlled by the selection signal formed by the decoder circuit DEC. The multiplexer MPX1 selectively selects output signals of the main amplifiers MA0 to MA3 in accordance with the output signal of the decoder circuit DEC in the normal operation in which the test signal TE is at a low level (second predetermined potential). One complementary signal selected by the multiplexer MPX1 is transmitted to an input terminal (one input terminal of the decoder output circuit DOB) of the output circuit OC constituting the DOB of the data output circuit.

Output circuit OC is timing signal The unit enters the operating state by amplifying the input signal and sending it to the external terminal Dout. As a result, the read operation is performed in units of one bit. Timing signal Is the write enable signal in the timing control circuit TC. Is generated at the time of the read operation at which the high level is reached. In the write operation, the output circuit OC, i.e., the output of the data output circuit DOB, is a signal. This results in a high impedance state.

The common complementary data lines CD0 to CD3 are coupled to the output terminal of the data input circuit DIB via a multiplexer MPX2 as the input selection circuit. The multiplexer MPX2 is controlled by the selection signal formed by the data circuit DEC in normal operation, and alternatively transfers the complementary output signal of the data input circuit DIB to the corresponding common complementary data lines CD0 to CD3. The data input circuit DIB is brought into operation by the timing signal Фrw, and transfers the write signal supplied from the external terminal Din to the pair of self-complementary complementary data lines CD0 to CD3 via the multiplexer MPX2. As a result, the write operation is performed in units of one bit. Timing signal Фrw is a light enable signal The low level write operation is not particularly limited, but is delayed from the operation timing signal of the main amplifier MA and generated in the timing generation circuit TG. In the read operation, the output of the data input circuit DIB is in a high impedance state by the signal? Rw.

The timing generator circuit TG has three external control signals. (Low address strobe signal), (Column address strobe signal) and The write enable signal is received, and the various timing signals necessary for the memory operation are formed and sent.

In this embodiment, a test circuit is built in order to shorten the test time of the dynamic RAM having the above storage capacity.

The test circuit on the data input side is included in the multiplexer MPX2 in this embodiment. When the test signal TE is at a high level test period or test operation, the test circuit transfers the write signal supplied from the external terminal Din to the common complementary data lines CD0 to CD3 with all of the multiplexer MPX2 selected.

As a result, the same signals are simultaneously written to four memory cells in the selected state of the memory array M-ARY. That is, in the test mode, writing is performed in units of 4 bits in appearance. This test circuit may be, for example, a switch circuit (for example, a MOSFET) that conducts at a high level of the test signal TE provided in parallel to each unit circuit of the multiplexer MPX2. In the test mode, each unit circuit of the multiplexer MPX2 may be in a non-conductive state.

The test circuit on the data output side is included in the multiplexer MPX1 and the data output circuit DOB. When the test signal TE is at a high level test period or test operation, the test circuit of the multiplexer MPX1 transfers the output signals of the main amplifiers MA0 to MA3 to the decision circuit JC with all the multiplexers MPX1 selected.

This test circuit may be, for example, a switch circuit (for example, a MOSFET) that conducts at the high level of the test signal TE provided in parallel in each unit circuit of the multiplexer MPX1. In the test mode, each unit circuit of the multiplexer MPX1 is in an inoperative state, and the output of the multiplexer MPX1 to the output circuit OC is in a high impedance state.

The judging circuit JC is a test circuit included in the data output circuit DOC and constitutes the data output circuit DOC. The judging circuit JC enters an operating state by the test signal TE in the test mode, and is not particularly limited, but receives the output signals of the respective main amplifiers MA0 to MA3 and detects (determines) the matching / mismatch, and outputs the detection result. Form a signal and send it to external terminal Dout through output circuit OC.

This makes it possible to perform a read operation in units of 4 bits in appearance. Although not particularly limited, the determination circuit JC is constituted by an exclusive OR (or NOR) circuit. The outputs of the main amplifiers MA0 and MA1 and the outputs of MA2 and MA3 are compared in the first and second exclusive OR circuits, respectively, and the outputs of the first and second exclusive OR circuits in the third exclusive OR circuit. Are compared. The judging circuit JC sends an output signal corresponding to the output of the third exclusive OR circuit to the output circuit OC. As a result, the output circuit OC forms a high level or low level output signal when the 4-bit read signal from the main amplifiers MA0 to MA3 matches the high level or the low level.

If any one of the four bit read signals is inconsistent, the output terminal Dout is set to a high impedance state. In addition, in the above four bit memory cells, when a defect or an error that inverts the accumulated data occurs, a high level or a low level is output as if there is no defect or error. For this reason, it is desirable to keep the write data as an expected value in the tester and to compare the expected value with the read signal.

The start and release of the test circuit as described above is controlled by the test signal TE obtained at the output of the latch circuit FF on which the set / reset is performed by the operation mode identification output included in the timing generation circuit TG. For example, when the test signal TE is at a high level, the respective test circuits are in an operating state, and when the test signal TE is at a low level, the respective test circuits are in an inactive state. This switches between the test mode and the normal mode.

The start / release of the test mode will be described next with reference to the timing chart shown in FIG.

Row address strobe signal The column address trough signal at the timing of And light enable signal To the low level. The timing generation circuit TG identifies this and supplies a high level signal to the latch circuit FF. As a result, the set of the latch circuit FF is executed, and the test signal TE is brought to the high level. That is, only the test mode setting is executed in this memory cycle TEST.

For example, if the dynamic RAM includes an automatic refresh circuit of the CAS-before-RAS refresh method, the address strobe signal Wow The refresh operation is executed in parallel with the setting of the test mode in relation to. It is the write enable signal described above that the test mode is set in parallel with the refresh operation. By the low level of, the refresh mode may be avoided by prohibiting the refresh mode.

Signal for write / lead operation for actual testing , Set the dynamic RAM to the high level once. At this time, the normal mode (normal read / write operation) is executed. Row address strobe signal To bring the low address signals AX0 to AXn at a low level, and then the column address strobe signal. The column address signal AY is fetched with the low level. Later than signal Фar signal Фx, Фpa (Фpa1, Фpa2, and And the operation signals of the main amplifier are sequentially generated at predetermined timings. On the other hand, the signal Фy is generated later than the signal Фac. As a result, four memory cells corresponding to the address signals ax0 to axn-1 and ay0 to ay-1 are connected to the common data lines CD0 to CD3.

At this time, the write enable signal is used to write the test data. Becomes low level at the timing shown. The signal Фrw generated by this and Sets the data input circuit DIB in the operating state and the output circuit OC in the inactive state. Since the test signal TE is at the high level, the complementary signal according to the signal supplied to the external terminal Din is transferred from the data input circuit DIB through all selected multiplexers MPX2 to the common data lines CD0 to CD3. As a result, one data is written to four memory cells. In other words, writing is performed in units of four bits in appearance. The potential difference of the complementary signal by the operation of the main amplifier is, for example, about 200 mV, and the potential difference of the complementary signal by the data input circuit DIB is about 5V. Therefore, data of the external terminal Din is written to the memory cell regardless of the operation of the main amplifier.

Next, test data written to the memory cell is read.

As described above, four memory cells corresponding to the address signals ax0 to axn-1 and ay0 to ayn-1 are connected to the common data lines CD0 to CD3 in the normal mode.

At this time, the write enable signal is used to read the test data. As shown by the dotted line in Fig. 1, the signal becomes high level. Generated by this Sets the data input circuit DIB in an inoperative state and the output circuit OC in an inactive state. Since the test signal TE is at a high level, the multiplexer MPX1 transfers the output signals of the main amplifiers MA0 to MA3 to the determination circuit JC, and also sets the alternative output to a high impedance state. By the high level of the test signal TE, it is determined whether or not the signals of the determination circuit 4 bits match or not. Accordingly, the output circuit OC puts the external terminal Dout in the high or low level or high impedance state. As a result, the reading is performed in units of 4 bits in appearance. In addition, it is possible to know whether or not a bad bit exists in the selected four memory cells.

The memory cycle TEST is not particularly limited while the test signal TE is set to high level, but the test cycle TE is repeatedly executed without bringing the test signal TE to low level. After the test data is written in units of 4 bits, the read may be repeated. The test data may be written to all the bits or to all the bits of one memory array, and then the data of these bits may be read.

After the test ends, the test mode is released. For this reason, the row address strobe signal The column address strobe signal at the timing of falling from high level to low level And light enable signal Are set to low level and high level, respectively. The timing generation circuit TG identifies this and supplies a low level signal to the latch circuit FF. As a result, the reset of the latch circuit FF is executed, and the test signal TE is brought low. In other words, only the release of the test mode is executed in this memory cycle RESET.

For example, when the dynamic RAM includes a CAS-non-RAS refresh type automatic refresh circuit, the address strobe signal The refresh operation is executed in parallel with the release of the test mode in relation to.

As a result, since the test signal TE can be set at the low level, subsequent operations can be made into the normal mode. Because of this, the signal Goes to high level, and the dynamic RAM is reset.

The effect obtained in the above Example is as follows.

(1) The combination of the row address strobe signal, the column address strobe signal, and the write enable signal that are not in the normal mode enables the test mode to be started / released without increasing the number of external control signals.

(2) According to (1) above, a dynamic RAM having a storage capacity equal to about 4M bits can be stored in an 18-pin package. This makes it possible to achieve matching with a dynamic RAM having a storage capacity of 1 M bits while adding a test function.

As mentioned above, although the invention made by the present inventor was described concretely according to the Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary.

For example, to turn test mode on and off, The address signal can be added to the combination of.

As shown by a dotted line in FIG. 2, the signal ai is supplied to a specific address input external terminal Ai to FF by the latch code. Timing Generation Circuit TG is a row address strobe signal The column address strobe signal at the timing of falling from high level to low level And light enable signal Sends one short pulse at low level. The latch circuit FF fetches a signal from the specific address terminal at that time in response to this one short pulse. For example, as shown in FIG. 3, if the signal supplied from the address terminal Ai is at a high level, the test mode is set. That is, the test signal TE is set at high level. The signal ai is not particularly limited but is supplied from the row address buffer R-ADB.

After the memory cycle SET for the test mode is set, the test cycle TEST is repeated.

After the end of the test, the memory cycle RESET for the release of the test mode is executed as follows. The timing generator circuit TG has the same signal as the memory cycle SET, as shown in FIG. One short pulse is sent in accordance with the combination of. The latch circuit FF fetches the low level signal of the address terminal Ai in response to this one short pulse. As a result, the test signal TE goes low, that is, the test mode is released.

In addition to the start / release of the test mode, for example, in the data output circuit DOB, two output functions of high impedance and intermediate level (half potential 1/2 Vcc between the power supply voltage Vcc and the ground potential Vss of the circuit) are outputted. It may be to choose it.

By adding a selection function to the output function, the inconsistent output signal can be switched in accordance with the tester to be used. For example, when the dynamic RAM is mounted on a memory board, the output terminal Dout is contacted in a wired OR configuration by the data bus on the board. Since the signal from the previous operation cycle remains on this data bus, identification of the mismatched output by the output high impedance becomes difficult. Therefore, in the test of the dynamic RAM on the memory board, the intermediate level output may be switched.

The output function can be selected using the address signal. That is, as shown by the dotted line in the memory cycle SET of FIG. 3, the signal (address signal) applied to the external terminal Ai-1 is latched (not shown). The signal of the external terminal Ai-1 is valid only when the signal of the external terminal Ai is high level in the memory cycle SET and RESET. When the output of this latch circuit is high level and low level, the output circuit OC sets the inconsistency signal to high impedance and intermediate level, respectively.

The output function of the data output circuit DOB is selected as follows when the output section of the final stage of the output circuit OC consists of the first and second n-channel MOSFETs in which the power supply voltage Vcc and the ground potential Vss are connected between the external terminal Dout. Become together.

In the case of the output in the normal mode, the complementary signal is supplied to the gates of the first and second MOSFETs by the first circuit in the output circuit OC. The first circuit is in an inoperative state and an operating state, respectively, in accordance with the high level and low level of the test signal TE. When the coincidence signal (high level or low level) is output in the test mode, the complementary signal is supplied to the gates of the first and second MOSFETs by the second circuit in the output circuit OC. On the other hand, for the inconsistent output of the test mode, the third and fourth circuits are provided in the output circuit OC. The third circuit supplies a low level signal to the gates of the first and second MOSFETs when a mismatch signal is input. As a result, the two output MOSFETs are turned off, and the external terminal Dout is brought into a high impedance state. The fourth time, when a mismatch signal is input, the high level signal is supplied to the gates of the first and second MOSFETs. As a result, the two output MOSFETs are turned on, and the external terminal Dout becomes a potential corresponding to the conductance gm of the two output MOSFETs, for example, 1 / 2Vcc potential. In practice, the second and third circuits and the second and fourth circuits are configured as one circuit, respectively. In these circuits, when the test signal TE is at a high level, one of the circuits is in an operating state in accordance with the signal of the external terminal Ai-1.

Although not particularly limited, the address terminal Ai is a terminal for supplying the most significant bit of the address signal, for example, the terminal A10 is used in a 1 M bit DRAM. In other words, the terminal Ai becomes the terminal An which gives the internal signal axn in this embodiment. By doing in this way, the function change of a chip becomes easy. For example, when the DRAM chip of 1M bit is configured of 256 kwords x 4 bits, the terminal A10 becomes unnecessary. In this case, if the present invention is applied, the terminal A10 does not need to be changed particularly, and the terminal A10 can be used as a terminal only for mode designation.

The output function may be selected as follows according to the signal of the terminal Ai-1. That is, when a high level signal is applied to the terminal Ai-1, any one of a high level, a low level, and a high impedance (or intermediate level) is supplied to the external terminal Dout. When a low level signal is applied, a high level signal as a coincidence signal and a low level signal as a mismatch signal are supplied to the external terminal Dout.

By combining the address signal with the row address strobe signal, the column address strobe signal, and the write enable signal, the test mode can be easily started / released, and a test function composed of various modes can be added.

Instead of the address terminals Ai and Ai-1, an input terminal Din or an output terminal Dout may be used.

The release of the test mode is a signal in one memory cycle. It may be executed by only making the low level.

The latch circuit FF is not particularly limited but may be constituted by a binary counter circuit using a master / slave flip-flop circuit.

Row address strobe signal The column address strobe signal at the timing of falling from high level to low level And light enable signal The counter circuit is operated by supplying one short pulse from the timing generator circuit TG with the low level. According to the output of the counter circuit, the test mode or the normal mode is selected. In this case, it is preferable that the counter circuit be configured to be either the test mode or the normal mode when the dynamic RAM is powered on.

The dynamic RAM to which the present invention is applied may have a nibble mode function of outputting a signal read in parallel in units of bits in the memory array in series by a signal that changes in synchronization with a column address strobe signal. In this case, the address signal supplied to the decoder circuit DEC of FIG. 2 may be changed by a shift register or an address counter circuit. Further, the specific configuration of the memory array M-ARY is designed to reduce the number of memory cells coupled to its word lines and data lines, to increase the speed, to secure the level margin of read signals from the memory cells, and the like. It may consist of.

The number of memory cells selected by the addressing of the memory array, in other words, the number of common complementary data lines may be any number of bits such as 8 bits, 16 bits, etc. in addition to the above 4 bits.

In addition, the present invention may be applied to a dynamic RAM having a storage capacity of about 1 M bit or 256 K bits, and used in another operation mode when a spare pin is generated.

The present invention can be widely used for a dynamic RAM incorporating a test circuit.

Claims (3)

Row address strobe First external terminal receiving a signal, the column address strobe ( Second external terminal and ride enable () A method of testing an address multiplexed dynamic RAM having a third external terminal receiving a signal, wherein the row address strobe signal is low to low when both the column address strobe signal and the write enable signal are low level. A step of changing from the normal operation mode to the test mode in accordance with the level change, the step of writing data of the same value to several memory cells in the dynamic RAM in the test mode, and the data read from the multiple memory cells coincide. Detecting whether or not the data is matched and outputting the result to the outside of the dynamic RAM. The normal operation in the test mode according to claim 1, wherein the row address strobe signal is changed from a high level to a low level when the column address strobe signal is low level and the write enable signal is high level. A method of testing a dynamic RAM including a step to set the mode. 2. The test mode of claim 1, wherein the row address strobe signal is changed from a high level to a low level when both the column address strobe signal and the write enable signal are at a high level. Test method of dynamic RAM including steps.