JPH077772A - Transmitter - Google Patents

Abstract

PURPOSE:To extend the extent of application and to improve reliability. CONSTITUTION:An input/output part 10 inputs and outputs data between a CPU and another station through a data bus 4 and a transmission line 5, and a control part 11 switches modes for controlling the input/output part 10 by setting from an outside. At the time of a normal mode, the data are transmitted and received based on an address allocated to its own station between the other station and the input/output part 10 controlled by a normal mode control part 12. At the time of a monitoring mode, the data are received regardless of its own station address or the other station address by the input/output part 10 controlled by a monitoring mode control part 13. At the time of an analyzer mode, error information on the transmission line 5 monitored by the input/output part 10 controlled by an analyzer mode control part 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission device having an interface circuit for transmitting and receiving data.

[0002]

2. Description of the Related Art Conventionally, there is a transmission device for transmitting and receiving data by connecting a master station and a control device which is a terminal station in order to monitor a control device which controls a motor or the like from the master station. FIG. 3 is a block diagram of such a conventional transmission device, and FIG. 4 is a block diagram of an interface circuit in this transmission device.

In FIG. 3, reference numeral 21 is an interface circuit for performing communication processing such as interface with other stations (not shown), 22 is a CPU as a control device for performing processing such as motor control and current value measurement, and 23 is from the CPU 22. When a reset signal, which will be described later, is not output for a certain period of time or more, it is determined that the CPU is abnormal, and a CPU abnormality detection circuit that outputs a reset signal that resets the CPU 22 is denoted by 24
2 is a data bus for connecting the interface circuit 21 to input and output data, 25 is a transmission line for connecting another station and its own station, that is, this transmission device for transmitting and receiving data, and SR is The reset signal output from the CPU 22 and CR are reset signals output from the CPU abnormality detection circuit 23. In FIG. 4, reference numeral 30 denotes an input / output unit in the interface circuit 21 for inputting / outputting data to / from the CPU 22 and other stations via the data bus 24 and the transmission line 25, and 31 controls the input / output unit 30. It is a control unit.

Next, the operation of such a transmission device will be described. First, in data transmission, data is input from the CPU 22 to the input / output unit 30 via the data bus 24, and is transmitted from the input / output unit 30 controlled by the control unit 31 to another station via the transmission line 25. Sent. Next, in receiving data, the data transmitted from another station is input to the input / output unit 30 via the transmission line 25, and the input / output unit 30 controlled by the control unit 31 via the data bus 24. The data is output to the CPU 22.

In such reception, only data relating to the address assigned to the own station is received. Further, as an error check related to data transmission / reception, only a simple error check such as a frame check is performed. The CPU 22 as a control device performs various processes such as motor control and current value measurement, but transmits and receives data to and from other stations such as the master station via the data bus 24 and the interface circuit 21.

Further, the CPU 22 is a CPU abnormality detection circuit 2
The operation of the CPU abnormality detection circuit 23 is controlled by outputting the reset signal SR to 3 at a constant time interval. CPU
The abnormality detection circuit 23 receives the reset signal SR from the CPU 22.
Is not output for a certain time or more, it is determined that the CPU is abnormal and a reset signal CR is output to the CPU 22. And
When the reset signal CR is output, the CPU 22 restarts after being reset.

[0007]

Since the conventional transmission device is constructed as described above, if the transmission device is used as a bus analyzer or the like for monitoring and monitoring the state of the transmission line, it is addressed to itself. There is a problem that the application is limited because only data can be received, and the reliability is low because only error checking such as frame checking is performed. Further, since the transmission device does not transmit the CPU error information to the other station even if the CPU has an abnormality, the other station cannot recognize the CPU abnormality and the reliability of the system is low. There was a problem. An object of the present invention is to provide a transmission device that can be used in a wide range of applications and have improved reliability in order to solve the above problems.

[0008]

According to the present invention, an input / output unit for inputting / outputting data to / from another station and a control for switching a mode for controlling the input / output unit according to a setting from the outside are performed. A normal mode control unit that controls data transmission and reception based on station address, a monitor mode control unit that controls data reception regardless of own station address or other station address, control that monitors the system status based on error information And an interface circuit having a control unit composed of an analyzer mode control unit.

Further, a CPU that controls or performs arithmetic processing based on the data, a CPU abnormality detection circuit that determines that the CPU is abnormal and outputs a CPU abnormality signal when the reset signal is not output from the CPU for a certain period of time, and a CPU abnormality. An interface circuit that sends error information to another station when a CPU abnormality signal is output from the detection circuit.

[0010]

According to the present invention, in the normal mode, data is transmitted and received between the input / output unit in the interface circuit controlled by the normal mode control unit and the other station based on the address assigned to the own station. . Then, in the monitor mode, the input / output unit controlled by the monitor mode control unit receives data regardless of the own station address or the other station address. In the analyzer mode, the input / output unit controlled by the analyzer mode control unit monitors the error information on the transmission line. If the reset signal is not output from the CPU for a certain period of time, the CPU
The abnormality detection circuit determines that the CPU is abnormal and outputs a CPU abnormality signal. The CPU abnormality signal causes the interface circuit to send error information to another station.

[0011]

1 is a block diagram of an interface circuit in a transmission apparatus showing an embodiment of the present invention. 1 is this interface circuit, 4 is a data bus, 5 is a transmission line, 10 is an input / output unit in the interface circuit 1, 11
Is a control unit for controlling the input / output unit 10, 12 is a normal mode control unit in the control unit 11 for controlling transmission / reception of data based on the own station address, and 13 is data regardless of the own station and other station addresses. Is a monitor mode control unit for controlling the reception of the data, and 14 is an analyzer mode control unit for performing the control for monitoring the system state based on the error information.

Next, such an interface circuit 1
The operation of will be described. The control unit 11 controls the input / output unit 10 to input / output data to / from a CPU or another station not shown in FIG. 1, as in the example of FIGS. There are three types of operation: normal mode, monitor mode, and analyzer mode.

The control of the normal mode, the monitor mode and the analyzer mode is performed by the normal mode control unit 12, the monitor mode control unit 13 and the analyzer mode control unit 14 in the control unit 11, respectively, and the mode switching is performed by the transmission line. Command or data bus from another station via 5
It is performed by a command from the CPU via. Then, data can be transmitted and received by using these modes alone or in combination.

First, the normal mode is a mode in which data is transmitted / received based on the address assigned to its own station, that is, a mode in which the same operation as the data transmission / reception in the examples of FIGS. This normal mode further has two types: an information module mode and a control module mode.

When transmitting data in the information module mode, the data is input from the CPU to the input / output unit 10 via the data bus 4, and the normal mode control unit 12 performs control based on this data. The data is transmitted to the other station via the transmission line 5. Then, in receiving the data, after the data transmitted from another station is input to the input / output unit 10 via the transmission line 5 and the necessary data conversion and analysis are performed under the control of the normal mode control unit 12. , CP from the input / output unit 10 via the data bus 4
Data is output to U.

Further, in transmission / reception in the control module mode, the input / output unit 10 is controlled by the normal mode control unit 12 without exchanging data with the CPU, and transmission data creation and analysis are performed by the interface circuit 1 alone. .

Next, the monitor mode is a mode in which all data input from the transmission line 5 is received regardless of the own station address or the other station address. The operation is basically the same as the normal mode except that the monitor mode control unit 13 performs control irrelevant to the own station address or the other station address.

The analyzer mode then monitors all error information on the transmission line 5, such as frame checks, parity errors, and stop bit errors. The operation is controlled by the analyzer mode control unit 14 regardless of the address of the local station or the address of the other station, but unlike the normal mode or the monitor mode, data analysis is not performed only by the monitoring operation.

Therefore, when constructing the duplex system, the system can be switched easily by monitoring the transmission data by using the monitor mode function on the backup side. Further, by using the analyzer mode function for the bus analyzer that monitors the transmission line 5, the state of the system including the transmission line 5 can be easily monitored.

FIG. 2 is a block diagram of a transmission device showing another embodiment of the present invention. Reference numeral 1a is an interface circuit that sends error information to the master station via the transmission line 5 when a CPU abnormality signal is output from a CPU abnormality detection circuit, which will be described later, 2 is a CPU, and 3 is a reset signal SR from the CPU 2 for a certain time or more. When it is not output, it is determined that the CPU is abnormal, the reset signal CR is output, and the CPU abnormality detection circuit CE that outputs the CPU abnormality signal to the interface circuit 1a is a CPU abnormality signal.

The interface circuit 1a may be similar to the interface circuit 1 in the example of FIG. 1 or may be similar to the interface circuit 21 in the example of FIG.

Next, the operation of such a transmission device when the CPU is abnormal will be described. The CPU 2 outputs the reset signal SR at regular time intervals as in the example of FIG. When the reset signal SR from the CPU 2 is not output for a certain time or longer, the CPU abnormality detection circuit 3 determines that the CPU is abnormal due to some factor and outputs the reset signal CR to the CPU 2 to reset the CPU 2, and at the same time, the interface circuit 1a. The CPU abnormality signal CE is output to.

When the CPU abnormality signal CE is output from the CPU abnormality detection circuit 3, the interface circuit 1a outputs CP.
When it is judged as U abnormality, the CPU error is notified to the master station based on the master station address obtained by analyzing the master station address notification data transmitted from the master station at the normal time. Therefore, another station, such as the master station, uses this transmission device, that is, the CP of its own station.
U abnormality can be recognized.

[0024]

According to the present invention, the control section of the interface circuit is provided with a normal mode control section, a monitor mode control section, and an analyzer mode control section to have a plurality of modes, and an arbitrary mode is selected from the outside. I did so,
A duplex system or the like can be easily constructed, the application of the transmission device can be expanded, and the reliability can be improved by using the analyzer mode.

Further, since the error information is transmitted to the other station when the CPU of the own station is abnormal, the other station can recognize the abnormality of the CPU of the own station, and the reliability of the system can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an interface circuit in a transmission device showing an embodiment of the present invention.

FIG. 2 is a block diagram of a transmission device showing another embodiment of the present invention.

FIG. 3 is a block diagram of a conventional transmission device.

4 is a block diagram of an interface circuit in the transmission device of FIG.

[Explanation of symbols]

 1, 1a Interface circuit 2 CPU 3 CPU abnormality detection circuit 4 Data bus 5 Transmission line 10 Input / output unit 11 Control unit 12 Normal mode control unit 13 Monitor mode control unit 14 Analyzer mode control unit

Claims (2)

[Claims] 1. A data transmission / reception based on an address of an own station, which controls an input / output unit for inputting / outputting data to / from another station and a mode for controlling the input / output unit according to an external setting. It consists of a normal mode control unit that controls the above, a monitor mode control unit that controls the data reception regardless of the own station address or other station address, and an analyzer mode control unit that controls the system status based on error information. A transmission device comprising an interface circuit having a control unit. 2. In a transmission device for transmitting and receiving data to and from another station, a CPU that performs control or arithmetic processing based on the data, and if the reset signal is not output from the CPU for a certain time or more, it is determined that the CPU is abnormal. And a CPU abnormality detection circuit that outputs a CPU abnormality signal, and an interface circuit that sends error information to another station when the CPU abnormality signal is output from the CPU abnormality detection circuit.