JPH0773591A - Information reproducing device and information recording device - Google Patents

Abstract

PURPOSE:To suppress inter-symbol interference when an edge position of a pit is varied in a step state and a disk in which data is recorded is reproduced. CONSTITUTION:A level of a reproduced signal corresponding to an edge position of a pit is decoded by decoder circuits 84 to 86. A correction value (inter-symbol interference component) corresponding to the decoded result is read out, and it is added (subtracted) to a reproduced value Va (n) held in a flip-flop 82 and to be decoded in reverse polarity in an adder circuit 88. The added value (a value in which the inter-symbol interference component is eliminated) of the adder circuit 88 is further decoded by a decoder circuit 89.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information recording medium such as an optical disk and a magneto-optical disk, and an information reproducing apparatus suitable for reproducing information from the information recording medium.

[0002]

2. Description of the Related Art In an optical disk used in a conventional CAV (constant angular velocity) mode, a servo byte section is periodically provided at a predetermined position of each track, and a clock pit for generating a reference clock is provided in this servo byte section. , Wobbled pits for tracking are formed. Then, a reference clock (channel clock) is generated corresponding to the clock pits, and the information is digitally recorded by the pits having a length that is an integral multiple of the period of the reference clock.

In a system used in a CLV (constant linear velocity) mode such as a CD (compact disc), there is no clock pit, but
The length of the recorded pits and the pit interval are integer multiples of the period (0.3 μm) of the reference clock (channel clock) (in the case of a CD, about 0.9 μm to 3.3 μm).
9) (the so-called self-clock method is used), the clock component included in the reproduction RF signal is extracted, and the recorded information is cut out in bit units. There is.

By the way, in the case of a video disc which is the same optical disc, a video signal is FM-modulated with a much smaller difference in pit length than a CD, and then recorded and reproduced. Now, this will be described by taking a signal recorded at a radius of 55 mm in the CAV mode as an example. On a video disc, the brightest part of the video signal is 9.3 MH
z, the darkest part is recorded as a signal of 7.6 MHz, which corresponds to 1.075 μm and 1.316 μm on a disc with a radius of 55 mm. It is well known that when a disc recorded in this way is reproduced, a very beautiful image is reproduced.

Assuming that the change in the brightness of 128 gradations can be expressed in this image, this means that the pit period is finely changed on the disc in 128 steps or more, recorded, and reproduced. Means that. That is, (1.316 μm-1.075 μm) ÷ 128 = 0.0
The small pit length of 02 μm and the change in the pit interval are reflected in the video signal.

As for the change in the pit length, in spite of being able to record such a small change, in the CD,
The minimum unit of change in the pit length must be increased to 0.3 μm mainly because the recording / reproducing method is not optimal.

The applicant of the present application, as Japanese Patent Application No. 3-167585, records the digital information by shifting the position of the front or rear edge of the information pit from a predetermined reference position in a stepwise manner corresponding to the recorded information. I proposed to do it first.
According to this recording / reproducing method, changes in the pit length and the position of the pit edge can be detected with extremely high accuracy. Therefore, it is possible to record digital information with minute changes that have been considered impossible until now. Is possible, and as a result,
Higher density than ever can be realized.

FIG. 38 shows the principle of recording information by shifting the position of the edge proposed by the present applicant in a stepwise manner. As shown in the figure, the recording signal PWM-modulated corresponding to the recording data (FIG. 38 (B))
To generate. Then, a pit (FIG. 38 (A)) corresponding to the length at the time of the zero cross is formed. In this way, the position of the edge of the pit is set to the reference clock (Fig.
8 (C)) changes in steps. According to this amount of change, it is possible to record data of 8 stages (3 bits) from 0 to 7 for one edge.

FIG. 39 shows the principle of reproducing the signal thus recorded. The RF signal (FIG. 39 (A)) reproduced from the information recording medium is greatly amplified and binarized R
An F signal (FIG. 39 (B)) is obtained. Since a clock pit is formed on the disc on which information is recorded, a reference clock (FIG. 39 (C)) is generated with this as a reference, and a sawtooth wave signal (FIG. 39) is generated in synchronization with this reference clock.
(D)) is generated. Then, the position of the edge of the information pit is detected by detecting the timing at which the sawtooth wave signal and the binarized RF signal cross.

Furthermore, the present applicant has filed Japanese Patent Application No. 5-208.
No. 76 proposed a method of two-dimensionally decoding the data recorded as described above. That is, in this method, educational pits are formed in advance on the optical disc. The front edge M and the rear edge N of this educational pit
As the combination (M, N), 64 (= 8 × 8) combinations of (0, 0) to (7, 7) are prepared. This education pit is reproduced, and reference points are mapped on the RAM as shown in FIG. 40 corresponding to the reproduction level.

Then, the normal data pit is reproduced, and the reproduction R at two positions of the front edge and the rear edge is reproduced.
The level of the F signal is sampled, and the point on the RAM specified by the two levels is obtained. Then, the reference point closest to that point is obtained, and the edge of the same combination as the edge of the educational pit to which the reference point corresponds is included in the data pit to decode the data.

[0012]

However, as described above, the method of decoding the data by mapping the reference points corresponding to the educational pits on the memory and determining the closest reference point is effective in reducing the state of intersymbol interference. When there is a change, it is necessary to rewrite all the contents of the RAM, that is, the position of the reference point, according to the change. For example, when the optical disc has a skew, the intersymbol interference changes at high speed with the rotation of the optical disc, but it is impossible to rewrite the data on the RAM at high speed in response to the high-speed rotation of the optical disc. is there.

When the level of the sampling point of the data pit is represented by 8 bits, the information of 2 points can be mapped on the RAM having the 16-bit address space. It is preferable to increase the number of sampling points as much as possible, but if the number of sampling points is set to three or more, the scale of the RAM becomes unrealizable. For example, in the case of three points, a 24-bit address space is required, and the RAM capacity in this case is 16
It becomes M bits. If the number of sampling points is four, the scale of RAM further requires 256 times the capacity. It is practically almost impossible to use such a large capacity RAM.

Furthermore, in the case of the above-mentioned method, an educational pit is required, but it is preferable to record as many educational pits as possible on the entire disc.
Furthermore, to learn the intersymbol interference that changes at high speed,
Frequent recording of educational pits is required. However, if a large number of educational pits are recorded in this way, the recording area of the data pits that should originally be recorded / reproduced decreases, and the capacity of the disc decreases.

The present invention has been made in view of such a situation, and can accurately decode data without reducing the recording capacity of the disk even if the state of intersymbol interference changes at high speed. It enables you to do it.

[0016]

The information reproducing apparatus of the present invention is a reproduction signal transient determined according to the transfer characteristics of an optical detection system (for example, the pickup 3 in FIG. 5) that scans a light beam along an information pit train. Period (for example, the rising period t in FIG. 2)
r, falling period tf) within a range corresponding to a predetermined shift period (eg, shift period Ts in FIG. 2) smaller than the predetermined reference position corresponding to the code to be recorded. In a information reproducing apparatus that reproduces recorded information from a disk medium (for example, the optical disk 1 in FIG. 1) in which digital data is recorded by shifting in a stepwise manner from a reference position based on a reproduction signal obtained from an optical detection system. Clock generating means (for example, the PLL circuit 7 in FIG. 14) that generates a phase-synchronized clock, and level detecting means (for example, FIG. 14 in FIG. 14) that detects the reproduction level in the transition period of the reproduction signal at the timing defined by the clock. A / D conversion circuit 9) and the reproduction level,
First decoding means (for example, the decoding circuits 84, 85, 86 in FIG. 14) for decoding the recording data corresponding to the shift amount of the edge position of the information pit, and a predetermined correction for correcting an error at the time of decoding A correction value generation unit (for example, the memory 87 in FIG. 14) that stores the value and outputs the correction value corresponding to the data decoded by the first decoding unit, and the correction value to the reproduction level of the code to be decoded. Adding means for adding (eg, FIG. 1
4) and second decoding means (for example, the decoding circuit 8 in FIG. 14) for decoding the record data corresponding to the shift amount of the edge position of the information pit based on the output of the adding means.
9) and are provided.

The correction value generating means can generate a correction value for correcting inter-code interference from a code adjacent to the code to be decoded.

The correction value generating means generates a correction value in advance by using a reproduction level of an educational pit (for example, an educational pit P6 in FIG. 1) provided as an information pit for obtaining decoded values of all edge patterns. , Can be stored.

At least 64 educational pits can be provided on the disk medium.

The correction value generating means includes a first memory (for example, memory 87A in FIG. 29) for storing a first correction value for correcting inter-code interference from adjacent codes before and after the code to be decoded. , A second memory (for example, the memory 87 in FIG. 29) that stores a second correction value for correcting inter-code interference from a code two codes away from the code to be decoded.
B) is provided, and the adding unit can add the first correction value and the second correction value to the reproduction level.

A set of the first decoding means, the correction value generating means and the adding means (for example, the set of the decoding circuits 84 to 86, the memory 87 and the adding circuit 88 in FIG. 17, the decoding circuits 104 to 106 and the memory 107). And adder circuit 10
8 sets) can be cascaded in a plurality of stages.

In all stages, the signal to be corrected can be a reproduction signal obtained from the optical detection system.

In this case, the code to be decoded supplied to the adding means of all the stages (for example, the adding circuits 88 and 108 of FIG. 17) is added to the adding means of any stage (for example, the adding circuit 88 or 108 of FIG. 17). According to the above, substantially the same code (for example, the code input to the decoding circuit 85 in FIG. 17) in which the correction value is not added can be used.

The number of stages in a cascade connection can be an even number.

A changing means (for example, the learning function circuit 121 in FIG. 22) for feeding back the output result of the second decoding means and changing the correction value of the correction value generating means can be further provided.

The changing means includes an ideal value calculating means for calculating an ideal reproduction level from the output of the second decoding means (for example, the arithmetic circuit 131 in FIG. 22) and a difference between the ideal reproduction level and the actual reproduction level. Difference means for obtaining the value
, And the correction value of the correction value generating means can be changed according to the difference value.

The changing means includes multiplying means for multiplying the difference value by a constant (for example, α) for preventing the correction value of the correction value generating means from oscillating (for example, the multiplying circuit 13 in FIG. 22).
3) and limiter means for limiting the output of the multiplication means within a predetermined range (for example, the limiter 134 in FIG. 22) can be further provided.

Error detection / correction means (for example, the error detection / correction circuit 13 in FIG. 31) that detects the presence or absence of an error in the output of the second decoding means and corrects the error, and corrects it according to the decoded value after error correction. A changing unit (for example, the learning function circuit 121 in FIG. 31) for changing the correction value of the value generating unit can be further provided.

The changing means calculates the ideal reproduction level from the output of the correcting means (for example, the arithmetic circuit 131 in FIG. 31) and the difference value between the ideal reproduction level and the actual reproduction level. Providing difference means (for example, the adder circuit 132 in FIG. 31) and selection means (for example, switch 183 in FIG. 31) for selecting either the difference value of the difference means or a predetermined constant according to the result of the error detection and correction means. You can

As the selecting means, the difference value of the difference means is selected when the error is not detected by the error detecting and correcting means, and a predetermined constant (for example, 0) is selected when the error is detected.
Can be selected.

The correction value generating means has a predetermined number (for example, FIG. 3).
Different correction values can be generated corresponding to the rotational position of the disk medium divided into eight (as shown in 2).

It is possible to collectively record pits that give the initial value of the correction value generating means in a predetermined range of the disk medium (for example, the initial value setting data area 1B in FIG. 35).

Further, in the information recording medium of the present invention, the initial value when the correction value of the correction value generating means (for example, the memory 87 of FIG. 17) is changed is within a predetermined range (for example, the initial value setting data area of FIG. 35). 1B) is recorded collectively.

[0034]

In the information reproducing apparatus having the above structure, the reproduced signals are decoded by the decoding circuits 84 to 86. Then, the correction value is read from the memory 87 using the decoded data as an address. The adder circuit 88 adds the correction value read from the memory 87 to the code to be decoded and outputs it to the decoding circuit 89. The decoding circuit 89 decodes this signal.

Incidentally, what is input as the address of the memory 87 is the decoded data. Since the decoded data is represented by a smaller number of bits than the data before being decoded, the number of addresses in the memory 87 can be small (for example, each edge can be changed in 8 steps). If the data is decoded, the data is 3 bits for each edge.
It is represented by. On the other hand, the data before decoding is 8 bits for each edge). As a result, the size of the memory 87 can be made sufficiently realizable with the current LSI technology.

In the information recording medium having the above structure, initial values are collectively recorded in the initial value setting data area 1B. Therefore, the correct correction value can be surely stored.

[0037]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of a basic format of an optical disc reproduced by the information reproducing apparatus of the present invention.

In this embodiment, a reflection type optical disk 1 having a diameter of 120 mm (pits are formed by physical concaves or convexes on the reflecting surface of the light beam), a CLV mode, a track pitch of 1.6 μm, The pit row is recorded. All the information is recorded as eight levels of shift amounts of the edge positions of the front end (rising edge) and the rear end (falling edge) of the pits arranged at regular intervals of 1.67 μm.
The unit shift amount Δ, which is one unit of this shift amount, is 0.0
It is set to 5 μm.

Since the 3-bit digital information can be recorded in each of the eight-step shift amounts of the edge positions of the pits thus arranged, the linear recording information density in the pit row direction is 0.28 μm / bit. That is more than double the current CD system.

In the CD system, even when the linear velocity is set to the upper limit of 1.2 m / s, the EFM (Eigh
t to Fourteen Modulation) 8 to record by modulation
A data bit of a bit is converted into a total of 17 channel bits of 14 bits of information bits and 3 bits of margin bits and recorded in pits on the disk. Therefore, in consideration of this EFM modulation, the linear recording information density Is about 0.6 μm / bit. That is, since the shortest pit of about 0.9 μm corresponds to 3 channel bits, (0.9 ÷ 3) × (17 ÷ 8) = about 0.6 μm / bit.

Here, as shown in FIG. 2, the optical disc 1
The edge position of the pit recorded in the step is shifted stepwise from the reference position at the center of the pit according to the digital information to be recorded.
X7) is longer than the rising period tr or the falling period tf, which is the transient period (a period other than the steady state in which the level is 0 or the saturation level) of the RF signal (reproduction signal) determined according to the transfer characteristic of the optical detection system. It is set within the range corresponding to the smaller period.

The RF signal is output from the pickup 3 of the reproducing apparatus described later, and the transfer characteristic of the pickup 3 determines the transient period. Generally, the transfer characteristic of an optical system is determined by its transfer function (OTF: Optical Tr
MTF (Modulation), which is the absolute value of ansfer function
Transfer Function), this MTF
Is determined depending on the numerical aperture NA of the lens and the wavelength λ of the laser.

If the unit shift amount Δ is shifted by a unit amount smaller than 0.05 μm in the shift period Ts, the recording density can be further increased.

The RF signal is A / D-converted to the reference position at the center of the pit thus recorded at the timing of the rising edge of the phase-synchronized sample clock SP to shift the pit edge position. It is possible to obtain reproduction levels L0 to L7 corresponding to 0 to 7. As described above, the reproduction level L is sampled only once during the transient period tr or tf of the RF signal.
The condition that can detect 0 to L7 is: shift period Ts ≦ transition period (rise period tr or fall period tf).

Here, as the sampling timing by the sample clock SP, the timing corresponding to the center of the shift period Ts is desirable, and with this timing, the reproduction level is detected over the entire range of the transient period of the RF signal. It becomes possible.

In this embodiment, the disk is a so-called reflection type optical disk in which pits are formed as physical recesses or projections on the reflection surface of the light beam, but the present invention is a magneto-optical film. Pits (marks) are formed by partially reversing the magnetization of the so-called MO (Magnet
It can also be applied to optical disks and the like.

The digital information recorded on the optical disc 1 is cut out in units of 3 bits and recorded in the n-th pit as recording data an and bn. FIG. 3 shows this state, where the front edge of the pit is the recorded data an.
Is set to any of eight shift positions 0 to 7. Similarly, the position of the trailing edge also corresponds to the recording data b.
It is set to any of eight shift positions 0 to 7 depending on n. The pitch Δ at each shift position is 0.05 μm as described above. As a result, the length of each pit LP
When the print data an and bn are both formed at the edge of the shift position 0, the shortest length LP is 0.5 μm.

Returning to FIG. 1 again, in the optical disc 1, six servo pits P1 for servo are provided between the data area consisting of 43 data pits formed corresponding to the recording data and another data area. A servo area consisting of P6 to P6 is inserted. 6 recorded in this servo area
Of the individual pits, pit P6 is an educational pit and pits P1 to P5 are reference pits. The position of the front edge on the left side of the educational pit P6 in the figure is 0 to 7
Is set to a position M of any of eight shift positions, and the rear end edge on the right side in the figure is also set to a position N of any of eight shift positions of 0 to 7.

The position M of the front end edge and the position N of the rear end edge of the education pit P6 are regularly set such that they are different in each servo area. That is, M and N are set to (0, 0) in the first servo area and (0, 1) in the next servo area. Similarly, (0, 2), (0,
3), ..., (7, 6), (7, 7) are regularly set as combinations. As a result, 64 (= 8 ×
8) Education pit P6 by reproducing servo areas
It is possible to detect all possible combinations of positions of the leading and trailing edges of the.

The reference pits P2 to P4 are pits for obtaining the data of the reference positions of (0,0) and (7,7). The reference position data can theoretically be formed at the edges of both ends of the pit P1 or P5, for example. However, in such a case, the ratio of interference from the adjacent data area changes depending on the recording data, so that dummy reference pits P1 and P5 (the data is always fixed) as in the embodiment. It is preferable to form the reference position data in the pits P2 to P4 between them.

If the edge as the clock generation reference is any of the edges between the reference pits P1 to P5, the clock can be accurately generated without being affected by the recording data.

FIG. 4 briefly describes the planar structure of the optical disc 1. Since the signal recorded at the track pitch of 1.6 μm is recorded in the CLV mode, the phase of the pit position does not match between adjacent tracks,
As shown in this figure, the data is recorded on the disc in different phases.

FIG. 5 is a block diagram showing the configuration of an embodiment of an optical disc reproducing apparatus to which the information reproducing apparatus of the present invention is applied. The optical disc 1 is adapted to be rotated by a spindle motor 2. In this optical disc 1,
Digital information is recorded based on the principle shown in FIGS. 1 and 2. That is, digital information is recorded by shifting at least one of the front edge and the rear edge of the pit in steps from a predetermined reference position. A servo area is formed on the optical disc 1 at a constant cycle, and reference pits P1 to P5 and an education pit P6 are formed therein. Naturally, data pits are formed in the data area.

The pickup 3 irradiates the optical disc 1 with laser light and reproduces the signal recorded on the optical disc 1 from the reflected light. The RF signal output by the pickup 3 is amplified by the head amplifier 4 and supplied to the focus tracking servo circuit 5, the APC circuit 6, the PLL circuit 7 and the spindle servo circuit 8.

The focus tracking servo circuit 5 is
A focus error signal and a tracking error signal are generated from the input signal, and corresponding to the error signal,
Execute focus control and tracking control. Further, the APC circuit 6 applies servo so that the power of the laser light with which the optical disc 1 is irradiated becomes constant.

The PLL circuit 7 extracts the clock component from the input signal. A PLL circuit used in a normal CD system or the like performs clock reproduction by using all RF signals, but in the case of this embodiment, RF in the servo area is used.
Clock recovery is performed using only the signal. That is, since the pits in the servo area are not modulated with the recorded data, stable clock reproduction can be performed without any influence of the recorded data.

The spindle servo circuit 8 controls the spindle motor 2 so that the optical disc 1 rotates at a constant linear velocity.

On the other hand, the RF signal output from the head amplifier 4 is input to the A / D conversion circuit 9 and the sample clock S
At the rising timing of P, A / D conversion is performed into digital data (reproduction level) indicating 8-bit levels of 256 levels. This 8-bit data is the bias removing circuit 10.
To the automatic gain control (AGC) circuit 11 after the bias component is removed by the bias removal circuit 10.
The gain is controlled by inputting to the. The output of the AGC circuit 11 is input to the error detection and correction (ECC) circuit 13 via the non-linear equalizer 12. Error detection / correction circuit 1
After detecting and correcting an error in the input data, 3 outputs to an analog audio amplifier via, for example, a D / A conversion circuit (not shown).

The controller 15 is a CP for performing various calculations.
It is composed of U and a program ROM or the like in which a program executed by this CPU is stored, and controls the operation of the spindle servo circuit 8 and other circuits.

FIG. 6 shows a configuration example of the bias removing circuit 10 and the AGC circuit 11. Bias removing circuit 10
Is a latch circuit 3 for latching the output of the A / D conversion circuit 9.
1, 32, 41 and 43, a subtraction circuit 42 for subtracting the output of the latch circuit 41 from the output of the latch circuit 31, and a subtraction circuit 44 for subtracting the output of the latch circuit 43 from the output of the latch circuit 32. There is.

Further, the AGC circuit 11 subtracts corresponding to the outputs of the latch circuit 61 for latching the output of the subtraction circuit 42, the subtraction circuit 62 for subtracting a predetermined target amplitude from the output of the latch circuit 61, and the output of the subtraction circuit 62. The variable gain amplifier 63 that controls the output level of the circuit 42, the latch circuit 64 that latches the output of the subtraction circuit 44, the subtraction circuit 65 that subtracts a predetermined target amplitude from the output of the latch circuit 64, the subtraction circuit 6
The variable gain amplifier 66 controls the level of the output of the subtraction circuit 44 in accordance with the output of No. 5.

The variable gain amplifiers 63 and 66 are
It can be configured by a ROM. In this case, this R
The outputs of the subtraction circuits 42 and 62 (44 and 65) are input to the OM as addresses, and the data corresponding to the addresses are read out.

Next, the operation of the embodiment shown in FIG. 6 will be described with reference to FIG.
The servo area pattern and the timing chart of FIG. 8 will be described. As shown in FIG. 7, the reference pit P
Reference position data 0 is recorded at the rear end of 2 and the front end of the reference pit P4. Further, reference position data 7 is recorded at the front end and the rear end of the reference pit P3, respectively.

By reproducing the data pits, reference pits, education pits, etc. shown in FIG. 7 (FIG. 8A), the RF signal as shown in FIG. 8B can be obtained. This RF signal is A / D
It is input to the conversion circuit 9 and is A / D converted at the timing of the clock shown in FIG. That is, the A / D conversion circuit 9
Will sample the levels corresponding to the leading and trailing edges of each pit.

The latch circuit 31 latches the output of the A / D conversion circuit 9 in response to the clock A shown in FIG. The clock A is generated at the timing of latching the data at the trailing edge of each pit. Therefore, the latch circuit 31 latches the data corresponding to the trailing edge of each pit. In addition, the latch circuit 41
Latches the output of the A / D conversion circuit 9 in response to the clock RA shown in FIG. Since this clock RA is generated at the timing of latching the reference position data 0 at the rear end of the reference pit P2, the latch circuit 41 latches the reference position data 0 at the rear end of the reference pit P2. The subtraction circuit 42 subtracts the reference position data 0 at the rear end latched by the latch circuit 41 from the data at the rear end edge of each pit latched by the latch circuit 31.

Similarly, the latch circuit 32 is provided with a circuit shown in FIG.
Data corresponding to the front edge of each pit is latched at the timing of the clock B shown in (E), and the latch circuit 43 is latched at the timing of the clock RB shown in FIG. 8 (G) at the front edge of the reference pit P4. The reference position data 0 is latched. Then, the subtraction circuit 44 uses the reference edge data 0 of the leading edge latched by the latch circuit 43 from the leading edge data of each pit latched by the latch circuit 32.
Subtract.

As described above, the DC component (bias component) of the reproduced signal can be removed by subtracting the data at the position 0 from the data corresponding to the edge position of each pit. As a result, even if the reproduction level (absolute level) corresponding to the shift position of the edge of each pit changes due to variations in the optical system of the optical disc 1 or the pickup 3, or the like, the correct shift position is accurately determined. It becomes possible.

The output of the subtraction circuit 42 is further latched in the latch circuit 61 at the timing of the clock KA in FIG. That is, the reference position data 7 recorded at the front edge of the reference pit P3 is latched in the latch circuit 61. A preset target amplitude is subtracted from the output of the latch circuit 61 in the subtraction circuit 62. Then, the difference is supplied to the variable gain amplifier 63.

The variable gain amplifier 63 adjusts the gain of the signal supplied from the subtraction circuit 42 in response to the signal supplied from the subtraction circuit 62. That is, as a result, the level of the reference position data 7 of the signal output from the variable gain amplifier 63 is set to the target amplitude.

Similarly, in the latch circuit 64, at the timing of the clock KB of FIG.
Output is latched. That is, the latch circuit 64 latches the reference position data 7 recorded at the trailing edge of the reference pit P3. The data latched by the latch circuit 64 is supplied to the variable gain amplifier 66 after the target amplitude is subtracted in the subtraction circuit 65.

The variable gain amplifier 66 adjusts the gain of the signal supplied from the subtraction circuit 44 in response to the signal supplied from the subtraction circuit 65. That is, as a result, the level of the reference position data 7 of the signal output from the variable gain amplifier 66 is adjusted to the preset target amplitude.

By adjusting the gain by the AGC circuit 11 as described above, it is possible to read the data accurately even when the optical disc 1 has local variations in characteristics.

FIG. 9 shows the relationship between the relative position of the read beam spot and the pit and the clock reproduced from the servo area. As shown in the figure, the clock generated in synchronization with the timing of the predetermined edge of the servo area has a rising edge when the spot of the reading laser beam reaches the front edge and the rear edge of the pit. It has been adjusted to occur. As described above, the reproduction level is sampled by the A / D conversion circuit 9 at this rising timing.

When the level of the reproduced signal obtained corresponding to the front edge of the pit is Va (n) and the level of the reproduced signal obtained corresponding to the rear edge of the pit is Vb (n), the code is In the ideal state where there is no inter-interference or transmission line non-linearity, the following equation holds. Va (n) = Δ _r · an + C (1) Vb (n) = Δ _r · bn + C (2) where an and bn are recording data, and Δ _r
Is the unit of change (shift) of the pit length on the optical disc 1 Δ
The amount is proportional to. C and Δ _r are constants determined by the bias removing circuit 10 and the AGC circuit 11.

The ideal reproduction signal as described above is shown in FIG.
Decoding can be easily performed using a decoding circuit having a staircase-like characteristic as shown in 0. That is, this decoding circuit outputs any value from 0 to 7 when the value of the reproduction signal Va (n) or Vb (n) is within the predetermined range.

For example, assuming that the bias removing circuit 10 and the AGC circuit 11 are adjusted so that Δ _r = 32 and C = 16, the reproduction signal Va (n) or Vb shown in FIG. 10 is obtained. The threshold value in the range (n) is as shown in FIG.

That is, the reproduction level Va (n) or Vb
0, 32 to 6 when (n) is a value between 0 and 32
A value between 4 is 1, a value between 64 and 96 is 2, a value between 96 and 128 is 3,128
To 160, a value between 160 and 192 is 5, a value between 192 and 224 is 6, a value between 224 and above is 7, and a decoding result of 7 is obtained. . The decoding circuit 70 having such characteristics can be configured as shown in FIG. 12, for example.

That is, in the case of this embodiment, the reproduction level Va
(N) or Vb (n) is 8-bit digital data of ID7 to ID0, and the decoding result is OD2 to OD.
It is output as 3-bit digital data of 0. ID
7 and ID6 are OD2 or OD1 as they are, respectively.
It is said that Then, the data obtained by inverting ID4, ID3, and ID2 by the inverters 71 to 73, ID6, and ID
The AND of 7 is calculated in the AND circuit 75, and the AND circuit 7
The output of 5 and the data obtained by inverting ID5 by the inverter 74 are NOR-operated by the NOR circuit 76 to obtain OD0.

Incidentally, in the case of this embodiment, the lowest 2 of the inputs are input.
Bits ID1 and ID0 become noise components and have no effect on the output, and are therefore ignored.

As described above, in the case where the ideal reproduction signal as shown in the equations (1) and (2) can be obtained, as shown in FIG.
As shown in FIG. 3, the output of the AGC circuit 11 can be easily decoded by the decoding circuit 70 configured as shown in FIG.

However, in practice, if data is recorded at high density and the distance between pits is shortened, intersymbol interference occurs, and correct decoding becomes difficult with the circuit having the configuration shown in FIG. . Therefore, for example, the applicant of the present invention can
As previously proposed as No. 300470, it is possible to predict the amount of intersymbol interference prior to recording and finely adjust the edge position of each pit so as to cancel it. However, if the manufacturing conditions of the disk change subtly, the size of the pit also changes subtly.
The state of intersymbol interference will also change. Therefore, again, it is difficult to accurately decode the data with the configuration shown in FIG.

Therefore, it is conceivable that the data is two-dimensionally decoded by mapping the sample signals at two points, as previously proposed in Japanese Patent Application No. 5-20876. However, as described above, it takes time to learn a reference point that is a prerequisite for mapping, and it is difficult to apply when intersymbol interference changes at high speed with rotation of an optical disk, such as when skew exists. Becomes Further, as described above, if it is attempted to remove intersymbol interference from distant pit edges, the circuit scale becomes large and it becomes impossible to realize.

Therefore, in the present invention, the non-linear equalizer 12 shown in FIG. 5 is constructed, for example, as shown in FIG.

In the embodiment of FIG. 14, the AGC circuit 1
The output of 1 is sequentially supplied to the three-stage flip-flops (registers) 81 to 83, and the flip-flops 81 to 83
The outputs of the above are supplied to the decoding circuits 84 to 86, respectively. The decoding circuits 84 to 86
Are configured as shown in FIG.

The outputs of the decoding circuits 84 to 86 are supplied to the memory (RAM) 87. Memory 8
7 outputs the data corresponding to the address designated by the outputs of the decoding circuits 84 to 86 to the adding circuit 88. The adder circuit 88 subtracts (adds with depolarization) the data read from the memory 87 from the output of the flip-flop 82, and outputs it to the decoding circuit 89. This decoding circuit 8
9 is also configured similarly to the decoding circuits 84 to 86. Then, the data decoded by the decoding circuit 89 is supplied to the error detection / correction circuit 13 shown in FIG. 5, and is output from there to a circuit (not shown).

A / D conversion circuit 9, bias removal circuit 1
0, the AGC circuit 11, and the flip-flops 81 to 83 are supplied with the clock generated by the PLL circuit 7.

Next, the operation will be described. Here, it is assumed that the inter-code interference occurs from each of the edges before and after the edge to be decoded. Intersymbol interference for the data an at the leading edge
When expressed by (bn, an, bn-1), the level Va of the reproduction signal
(N) is expressed by the following equation. _{Va (n) = (Δ r} · an) + Ha (bn, an, bn-1) + C ··· (3)

If the intersymbol interference with respect to the data bn at the trailing edge is represented by Hb (an + 1, bn, an), the level Vb (n) of the reproduced signal is represented by the following equation. Vb (n) = (Δ _r · bn) + Hb (an + 1, bn, an) + C (4)

Since the flip-flops 81 to 83 sequentially output the input data to the subsequent stage every time the clock is supplied, the flip-flop 83 is output at the timing when the flip-flop 82 outputs Va (n). Is
The reproduction level Vb (n-1) corresponding to the previous edge is output, and the flip-flop 81 outputs the reproduction signal Vb (n) of the subsequent edge.

The decoding circuits 84 to 86 decode the outputs of the flip-flops 81 to 83, respectively, in accordance with the characteristics shown in FIG. 10, and decode the decoded data b'n, a'n,
Output b'n-1. These decoding results will be correct if there is no non-linear intersymbol interference Ha (bn, an, bn-1), but in reality, since intersymbol interference exists, an error occurs. However, intersymbol interference Ha
Assuming that the value of (bn, an, bn-1) is not very large, the value b'n, obtained by the decoding circuits 84 to 86,
It can be considered that a'n and b'n-1 are separated from the correct decoded values bn, an and bn-1 by level ± 1 at most. That is, the following equation is established. b'n = bn ± 1 (5) a'n = an ± 1 (6) b'n-1 = bn-1 ± 1 (7)

By the way, since the amount of change in the shift position of the pit is extremely small, even if an error of ± 1 occurs in the decoding result, the amount of evaluation error of the position of the edge of the pit generated as a result is extremely small. Few. Therefore,
The actually generated intersymbol interference Ha (b
n, an, bn-1) and the error Ea between the intersymbol interference Ha (b'n, a'n, b'n-1) due to the data obtained as a result of decoding
(N) has an extremely small value. Ea (n) = Ha (bn, an, bn-1) -Ha (b'n, a'n, b'n-1) (8)

Therefore, nonlinear intersymbol interference Ha (bn,
The value of (an, bn-1) is obtained in advance (how to obtain it will be described later) and stored as a correction value in the memory (RAM) 87. Then, the data (estimated value) b′n, a′n, obtained by simply decoding by the decoding circuits 84 to 86,
If the value obtained at that time is referred to as a correction value (intersymbol interference) by referring to the memory 87 with b′n−1, this value is the intersymbol interference due to the actual data bn, an, bn−1. There is no big difference.

Therefore, based on the estimated values b'n, a'n, b'n-1 output from the decoding circuits 84 to 86, the intersymbol interference Ha (b'n, a ') read from the memory 87 is read. n, b'n-1)
Is added to the reproduction value Va (n) by the adder circuit 88, and a value V ′ (a) represented by the following equation is a reproduction value when there is almost no intersymbol interference. V '(a) = Va (n) -Ha (b'n, a'n, b'n-1) (9)

That is, as described above, the reproduction value Va (n) input to the adding circuit 88 from the flip-flop 82.
Is subjected to intersymbol interference, and is expressed by the following equation. _{Va (n) = (Δ r} · an) + Ha (bn, an, bn-1) + C ··· (10)

By subtracting the value Ha (b'n, a'n, b'n-1) supplied from the memory 87 from Va (n) in the equation (10), Ha (bn, an, bn-). 1) is Ha (b'n, a '
n, b'n-1), the output V '(a) of the adder circuit 88 is expressed by the following equation. _{V'a (n) = (Δ r} · an) + C ··· (11)

The equation (11) is equal to the equation (1) in the ideal case described above. Therefore, if this V'a (n) is decoded by the decoding circuit 89, a correct decoded value can be obtained.

In the above description, the level of the reproduction signal Va (n) corresponding to the front edge of the pit is sampled and decoded, but the reproduction signal Vb (n) corresponding to the rear edge of the pit is described. The same operation is performed when the level of is sampled and decoded.

FIG. 15 explains this case, and shows the case where the state changes by one clock from the state of FIG. In FIG. 14, the reproduction value Va (n) held in the flip-flop 82 is transferred to the next-stage flip-flop 83 in the state shown in FIG. Then, in the state shown in FIG. 14, the reproduction value Vb (n) held in the flip-flop 81.
However, in the state shown in FIG. 15, it is transferred to the flip-flop 82 at the next stage. Then, the next reproduction value Va (n + 1) is further held in the flip-flop 81.

Therefore, the circuit shown in FIG.
The reproduction value Vb (n) held in the flip-flop 82 is decoded in the same manner as in the case of. However, since the intersymbol interference at the front edge of the pit and the intersymbol interference at the rear edge of the pit are different, both correction values (the front edge correction value and the rear edge correction value) are stored in the memory 87. Is stored in advance. Then, the clock output from the PLL circuit 7 is divided into ½ by the divider circuit 91, the output is input to, for example, the most significant bit of the memory 87, and the correction value read from the memory 87 is supplied to the leading edge of the memory 87 by this signal. Or for the trailing edge.

Here, a method of obtaining the intersymbol interference Ha and Hb will be described.

As described above, in this system, the educational pit P6 (FIG. 1) is periodically recorded, and the position M of the front edge and the position N of the rear edge of this pit are as follows.
I know everything in advance. Of the signals obtained when the educational pit P6 is reproduced, the signal at the front edge is Va (M,
N) and the trailing edge one is Vb (M, N), the following equation holds. Va (M, N) = Δ r · M + Ha (N, M, 7) + C ··· (12) Vb (M, N) = Δ r · N + Hb (K, N, M) + C ··· (13)

In the equation (12), the constant "7" is included in the reference pit P5 immediately before the education pit P6.
This is because the data recorded at the edge of is 7 (FIG. 1). The variable K in the equation (13) represents the data (any value from 0 to 7) recorded immediately after the educational pit P6.

The signal from the educational pit P6 thus obtained and the reproduction levels Va (M, N) and Vb are obtained.
From (M, N), a value that is an approximate value but is stored in the memory as a correction value can be calculated by the following equation. Ha (N, M, i) = Va (M, N)-[Delta] _r * MC (i = 0,1,2, ..., 7) ... (14) Hb (j, N, M) ) = Vb (M, N) -Δ r · N-C (j = 0,1,2, ···, 7) ··· (15)

In equations (14) and (15), except for the intersymbol interference (i or j) between the two edges (M and N) of the same pit (education pit P6), it is ignored (that is,
Even if the value of i or j is any value from 0 to 7, the same correction value is used. However, when the intersymbol interference between the edges recorded in the same pit is the strongest, this can still be sufficiently used as the initial value of the correction value. Therefore, this initial value is stored in the memory 87 in advance.

As described above, if the reproduced signal from the front edge of the pit can be corrected, the reproduced signal from the rear edge can also be corrected by the same circuit. Therefore, in principle, only the case of decoding the reproduced signal of the front edge of the pit will be described below.

If the intersymbol interference can be corrected by the configuration as shown in FIG. 14, the intersymbol interference can be further reduced by connecting the intersymbol interference in a plurality of stages as shown in FIG. It may be removed. That is, in this embodiment, the flip-flops 81 to 83, the decoding circuits 84 to 86, the memory 87, and the adder circuit 88 are provided at the subsequent stage, and the flip-flops 10 corresponding to them are provided.
1 to 103, decoding circuits 104 to 106, and memory 1
A circuit having a similar configuration including 07 and the adder circuit 108 is connected. The output of the adder circuit 108 is supplied to the decoding circuit 89.

However, if the cascade connection is simply performed as shown in FIG. 16, for example, if the first-stage decoding circuits 84 to 86 perform incorrect decoding,
An erroneous intersymbol interference correction value is read out from the memory 87, and the correction due to this erroneous correction value cannot be corrected in the second and subsequent stages. As a result, it becomes difficult to accurately decode the data.

Furthermore, in the configuration shown in FIG. 16, the correction value of the intersymbol interference with respect to the reproduction value Va (n) is read out in the memory 87, but in the memory 107, it has already been read in the circuit of the first stage. Since the corrected reproduction value V′a (n) is corrected, the memory 107
The correction value to be stored in the memory must be different from the correction value to be stored in the first-stage memory 87. Therefore, considering that the correction values of the memories 87 and 107 are updated in real time, the calculation time required for the update becomes long. As a result, in the end, real-time updating becomes difficult.

Therefore, in the case of cascade connection, the connection can be made as shown in FIG. In this embodiment, the flip-flops 81 to 83 and the decoding circuit 8
4 to 86, the memory 87, and the adder circuit 88, the flip-flop 10 having the same configuration is provided at the subsequent stage of the first stage circuit.
1 to 103, decoding circuits 104 to 106, and memory 1
The connection of the second stage circuit composed of 07 and the adder circuit 108 is the same as in the case of FIG. However, the reproduction value supplied to the adder circuit 108 is not the output of the flip-flop 102 of the second stage but the output of the flip-flop 82 of the first stage. That is, the output of the flip-flop 82 is delayed by two clocks by the flip-flops 111 and 112,
The correction value and timing read from the memory 107 are adjusted and supplied to the addition circuit 108. Other configurations are similar to those in FIG.

With such a configuration, in the second stage, as in the case of the first stage, the uncorrected reproduction value is corrected, and the memory 1 in the second stage is corrected.
The correction value to be stored in 07 may be the same as the correction value to be stored in the memory 87 of the first stage.

That is, the reproduction value Va (n) held in the first-stage flip-flop 82 of FIG. 17 corresponds to the correction value stored in the first-stage memory 87, and is added by the adding circuit 88. Corrected, but 2 from the state shown in FIG.
When the time corresponding to the clock has elapsed, the state becomes as shown in FIG.

That is, the reproduction value V'a corrected in the first stage
(N) is held in the second-stage flip-flop 102. Then, at this time, the reproduction value Va (n) held in the flip-flop 82 by two clocks shown in FIG. 17 is supplied from the flip-flop 112 to the adder circuit 108.

From the decoded values (estimated values) b'n, a'n, b'n-1 supplied to the first-stage memory 87 in FIG.
Decoded values b ″ n, a ″ n, b ″ in the second stage shown in FIG. 18 that are decoded after the intersymbol interference is corrected in the circuit in the second stage.
The value of n-1 should be closer to the recorded data bn, an, bn-1. Therefore, intersymbol interference Ha (b ″ n, a ″ n, b ″ n−1) read from the memory 107.
Is the true intersymbol interference H from the intersymbol interference Ha (b'n, a'n, b'n-1) read in the memory 87 of FIG.
The value is closer to a (bn, an, bn-1). Therefore, the output V ″ a (n) of the adding circuit 108 becomes a value closer to the ideal reproduction value Va (n). Therefore, the decoded value a ′ ″ n obtained by decoding this in the decoding circuit 89 becomes a value closer to the recording data an.

FIG. 19 shows the first part in FIG. 17 (FIG. 18).
The reproduced values Va (n) and Vb (n) held in the flip-flops 82 and 81 of the second stage are input to the X-axis and Y-axis of the oscilloscope to show the observed state.
The positions of the front and rear edges of each pit are 0 to 7 (8).
Ideally, 64 (= 8 × 8) bright spots should appear at equal intervals because of the stepwise shift to the step position.

However, due to the non-linear intersymbol interference, the entire shape composed of 64 luminescent spots is not a square but is distorted into a rhombus, and each luminescent spot is not a dot but a spread. . This means that if the reproduced value is decoded as it is, many errors occur.

On the other hand, FIG. 20 corresponds to FIG.
As shown in FIG. 5), the reproduction value corrected by the first-stage correction circuit is input to the oscilloscope and observed (that is, the reproduction values held in the flip-flops 102 and 101 in FIG. 18 are represented). Is displayed). Of the playback values, the lower left part is off the ideal value,
It is erroneously identified as the data for the next shift position.
Therefore, it is observed that the correction value is slightly deviated from the correct value, and the corrected signal is also deviated from the ideal value.

On the other hand, FIG. 21 shows a state in which the reproduction value corrected by the second stage circuit is observed by an oscilloscope. From the figure, it can be seen that the distortion is reduced. Therefore, if this is decoded, the influence of inter-code interference can be reduced and more correct decoded data can be obtained.

FIG. 22 shows an example of the configuration in which the correction values stored in the memories 87 and 107 can be updated at high speed in real time. In this embodiment, from the decoded value a ′ ″ n−1 output from the decoding circuit 89,
The ideal value is calculated by the arithmetic circuit 131 of the learning function circuit 121 according to the following equation. The ideal value _{= Δ r · a '''} n-1 + C ··· (16) Δ r and C are the known, the ideal value can be easily obtained.

On the other hand, the adder circuit 132 is the adder circuit 108.
From the output V ″ a (n−1) of the above, the ideal value output from the arithmetic circuit 131 is added (subtracted) with the opposite polarity, and the error ε is output. This error .epsilon.
This corresponds to the difference from the correction value stored in Nos. 7 and 107. Therefore, this error ε is multiplied by the constant α in the multiplication circuit 133, and the result of the multiplication is limited by the limiter 134 to a value within a predetermined range.

Incidentally, the reason why the constant α is multiplied here is to prevent the correction values stored in the memories 87 and 107 from oscillating. Therefore, it is desirable that this constant α be smaller than 1. Further, the limit of the value updated by the limiter 134 is to prevent the correction value from being updated to an abnormal value due to the presence of a defect (defect) on the optical disc 1. To do.

The error ε output from the limiter 134 is
It can be considered that the correction values stored in the memories 87 and 107 are generated because they are deviated from correct values. Therefore, the error ε output from the limiter 134 is added to the correction value read from the memory 107 in the adder circuit 511. This allows
This means that the correction value has been adjusted to a more correct value.

Therefore, the adjusted new correction value is
Through the flip-flops 512, 513 and the three-state buffers 521, 522, the memories 87, 10
7 so that the stored value is updated.

By the way, in order to perform this updating process, the addresses of the memories 87 and 107 are required. In order to obtain this address, the data (pit edge position) recorded before and after the data an to be decoded is required. Therefore, the output of the decoding circuit 89 is sequentially supplied to and held by the flip-flops 531, 532, 533. Then, these flip-flops 531 to 53
3 is supplied to the memory 87 or the memory 107 via the switches 501 to 503 or the switches 504 to 506, respectively.

As described above, the address required for updating the correction value after reading the correction value from the memory 87 or 107 is delayed by 2 clocks after reading the correction value. Therefore, the correction value itself supplied to the memory 87 or 107 is also the flip-flop 5
After delaying 2 clocks by 12 and 513,
Via the three-state buffer 521 or 522,
The data is supplied to the memory 87 or the memory 107, respectively.

The address at which the correction value is read from the memories 87 and 107 and the address at which the new correction value is stored do not always match. That is, the decoding circuit 8
The data decoded by 4 to 86, and finally decoded by the decoding circuit 89, the flip-flop 531
Through 533 do not necessarily match the data held. Similarly, the decoding circuits 104 to 106 are also provided.
Data decoded by the flip-flop 531
Through 533 do not necessarily match the data held.

Therefore, in order to switch the address for reading the correction value from the memories 87 and 107 and the address for updating the new correction value,
Switches 501 to 503 are provided, and the memory 1
07, switches 504 to 506 are provided.

FIG. 23 shows the timing of reading and writing the correction value in the memory 87 (memory 107). 23 corresponds to the pit row shown in FIG.
The RF signal shown in (B) is supplied to the A / D conversion circuit 9 and the PLL circuit 7. The PLL circuit 7 generates the clock shown in FIG. 23C from the input RF signal and A / D
Output to the conversion circuit 9. As shown in FIGS. 23B and 23C, the rising edge of this clock is generated at the timing of the edges before and after each pit. Therefore, A
The / D conversion circuit 9 samples the level of the reproduction signal corresponding to the front and rear edges of each pit. Then, the sampled value is supplied to the circuit in the subsequent stage.

This clock is also frequency-divided by the frequency dividing circuit 91, and as shown in FIG. 23 (D), a signal having a cycle twice that of the clock shown in FIG. 23 (C) is generated. It is supplied to the memory 107 to switch between the correction value for the front edge and the correction value for the rear edge of each pit.

On the other hand, the memories 87 and 107 are shown in FIG.
The correction value is read at the timing of the rising edge of the clock shown in (C). Therefore, the PLL circuit 7 sets the FB signal shown in FIG. 23E to a low level, and switches the switches 501 to 503 and the switches 504 to 506 in FIG. 22 to the left side in the drawing. Also, FIG.
The OE signal shown in (G) (in the figure, an overline is added above the character OE) is brought to a low level.
As a result, in the memory 87, the correction values are read and output using the signals output from the decoding circuits 84 to 86 and input via the switches 501 to 503 as addresses.

Similarly, the signals output from the decoding circuits 104 to 106 are supplied as addresses via the switches 504 to 506, and the correction value corresponding to this address is read from the memory 107 and output.

At this time, the three-state buffer 5
21, 522 are F as a control signal supplied thereto.
Since the B signal is at a low level, it is in an open state.
Therefore, it is prevented that the data held in the flip-flop 513 is output onto the data lines of the memories 87 and 107 and mixed with the read data of the memories 87 and 107.

On the other hand, the PLL circuit 7 generates the WE (in the figure, an overline is added above the character WE) signal shown in FIG.
Is being supplied to. The memories 87 and 107 execute the write operation when the WE signal becomes low level. Figure 2
When the WE signal shown in FIG. 3 (F) momentarily becomes low level, the FB signal shown in FIG. 23 (E) becomes high level. Therefore, the switches 501 to 503 and the switches 504 to 506 are switched to the right side in FIG. As a result, the data held in the flip-flops 531 to 533 is supplied to the memory 87 or the memory 107 as an address through the switches 501 to 503 or the switches 504 to 506.

At this time, the three-state buffers 521 and 522 are turned on because the supplied FB signal becomes high level, and the new correction value held in the flip-flop 513 is set on the data lines of the memories 87 and 107. Supply to. As a result, the correction values of the addresses held in the flip-flops 531 to 533 are updated in the memories 87 and 107 by the new correction value held in the flip-flop 513 as shown by the following equation. In the following equation, δ is the output of the limiter 134. Ha (b '''n-2,a''' n-2, b '''n-3) = Ha (b''' n-2, a '''n-2,b''' n -3) + δ

Even if the initial values of the memories 87 and 107 are set to 0, an appropriate correction value is automatically generated and stored by repeating the updating operation.

FIG. 24 shows the memory 8 as described above.
The error rate (C1 error) of the decoded data when the stored values of 7, 107 are corrected in real time is shown.
As shown in the figure, when the correction values of the memories 87 and 107 are not updated in real time, the number of C1 errors per second is 400 to 500, but when updating in real time, the C1 error per second is C1. It can be seen that the number of errors is suppressed to about 30 to 50.

The learning function circuit 121 can be simply constituted by a logic circuit, and its feedback operation can be performed at high speed for each clock without requiring a particularly difficult logic circuit. Therefore, even when the optical disc 1 has a skew and the intersymbol interference changes at a high speed, the correction value can be updated at a high speed correspondingly.

As described above, by repeating the operation of updating the stored value in the memory, the correct correction value is always held in the memory. However, if the stored value becomes an incorrect value due to the influence of a defect, or the appearance probability of a pattern at a specific edge position is low, the correction value should be updated only for that pattern. It is possible that you cannot.

Such a state is, for example, only when the correct value of the correction value is Ha (bn, an, bn-1) and the recorded information has a value of (i, j, k). , It can be expressed that the correction value deviates to H'a (bn, an, bn-1). That is, it can be expressed by the following equation. H'a (bn, an, bn-1) = Ha (bn, an, bn-1) + e (when bn = i, an = j, bn-1 = k) = Ha (bn, an, bn- 1) (Other cases) (17)

In the above equation, e is the deviation of the correction value from the true value. Because of this deviation e, bn =
When an input pattern to be decoded with i, an = j, bn-1 = k occurs, only one is mistaken for the next edge position,
It is assumed that the decoding is bn = i, an = j + 1, bn-1 = k.

In such a case, the state of updating the correction value when the nonlinear equalizer 12 has a one-stage configuration will be considered with reference to FIG. In the embodiments after FIG. 25, the switches 501 to 506, the adder circuit 511, the flip-flops 512, 513, 531 to 533, and the three-state buffers 521 and 522 in FIG. 22 are omitted in order to simplify the drawing. Then
The output of the limiter 134 is shown as it is supplied to the memories 87, 107 and the like.

The recorded data is bn = i, an =
Let j, bn-1 = k. Decoding by the decoding circuits 84 to 86 is performed correctly. However, the memory 87
Since the stored value (correction value) of is incorrect, the correction value has an error of e, and its output is Ha (i, j, k) + e. As a result, based on this correction value, the reproduction value Va
The data obtained as a result of decoding the reproduction value V′a (n) obtained by correcting (n) by the decoding circuit 89 is a ″ n =
It is j + 1.

When such a decoding result is obtained, the arithmetic circuit 131 calculates an update value based on this erroneous decoding result, so that among the correction values stored in the memory 87, bn = I, an = j + 1, bn-1 = k correction values are updated. However, the correction values corresponding to the error correction values bn = i, an = j, bn-1 = k are not updated. That is, once an incorrect correction value is input, even if correct data is continuously input thereafter, the incorrect correction value will not be corrected.

Next, as shown in FIG. 26, consider a case where the nonlinear equalizer 12 has a two-stage configuration (even-stage configuration). In this figure, there is originally a time difference of two clocks between the first stage and the second stage.
For convenience of explanation, the data in each stage is entered by ignoring this time difference.

As in the case shown in FIG. 25, the stored value of the memory 87 of the first stage is the correction value Ha (i,
j, k) + e are output, the decoding results b ″ n = i, a ″ n = j + 1,
b ″ n−1 = k is obtained. As a result, the output of the memory 107 is not the correction value Ha (i, j, k) + e, but
Ha (i, j + 1, k) is obtained. That is, this correction value does not include the error e. As described above, since this Ha (i, j + 1, k) is almost the same value as Ha (i, j, k), it is not perfect, but the memory 87
The correction value Ha (i, j, k) + e stored in is approximately correct correction value Ha (i, j + 1, k) ≈Ha (i,
j, k). Therefore, the correction value in the memory 87 is updated so that the error e becomes smaller.

Although the case where the number of correction stages is one and two has been described above, the same explanation can be made when the number of stages connected in cascade is increased beyond that. That is,
Even if an error occurs in the correction storage value, if the number of correction steps is set to an even number instead of an odd number, the error is gradually corrected. If the number of stages is odd,
This error cannot be corrected.

FIG. 27 shows the result of an experiment conducted to confirm the above. That is, a device in which a disturbance is intentionally given to the optical disc 1 to create a state in which an error is extremely large and the number of cascaded stages of the nonlinear equalizer 12 is set to one stage, two stages, three stages or four stages at this time. In, the error rate of the output signal which changes with time is examined.

As in this experiment, when the correction value of the memory is updated in a high error rate state, the stored value often deviates from the correct value, but even-numbered stages are connected in cascade. In the case of, the error rate does not increase so much and is stable. That is, even if an erroneous value is stored as the correction value, the data that follows is correctly decoded, and thus there is a restoring force to return to the original correct state. On the other hand, in the case of the cascade connection configuration with an odd number of stages, once an incorrect value is stored in the correction value, the error is not removed, and the error rate increases with the passage of time. Become.

In the above embodiments, the intersymbol interference is
From the edge of the pit to be decoded, it is assumed that it occurs only from two pits adjacent to the front and back, and the correction is performed. However, in reality, intersymbol interference also occurs from the edges of pits further apart in the time axis direction. In particular, when a tangential skew occurs on the optical disc 1, the diameter of the reading spot extends in the front-rear direction, and the influence from the edge of the pit far away becomes large. Thus, in order to remove intersymbol interference from distant edges, as shown in FIG. 28, for example,
The elements to be input to the memories 87 and 107 may be expanded forward or backward by that amount.

That is, the RF in which intersymbol interference has occurred so far.
As the signal model, the model represented by the following equation has been considered. _{Va (n) = (Δ r} · an) + Ha (bn, an, bn-1) + C ··· (18)

However, in the embodiment of FIG. 28, the following model is considered. _{Va (n) = (Δ r} · an) + Ha (an + 1, bn, an, bn-1, an-1) + C ··· (19)

That is, in this case, the correction values considering the inter-code interference from two edges before and after the edge to be decoded are stored in the memories 87 and 107. Although this embodiment has an advantage that the circuit configuration is simple, it is necessary to increase the capacity of the memories 87 and 107.

Therefore, for example, as shown in FIG. 29, the memories 87 and 107 can be divided into two, A and B, respectively.

That is, in this embodiment, intersymbol interference is divided into two and corrected as shown by the following model. _{Va (n) = (Δ r} · an) + Ha1 (bn, an, bn-1) + Ha2 (an + 1, an, an-1) + C ··· (20)

In the memories 87A and 107A, for example, as in the case of the embodiment shown in FIG. 22, a correction value H for correcting intersymbol interference from two edges adjacent to each other in the front and rear is provided.
Remember a1. On the other hand, the memories 87B, 10
In 7B, a correction value Ha2 for correcting intersymbol interference from two edges that are separated by two from the edge to be decoded is stored. Strictly speaking, it is not correct to distinguish intersymbol interference in this way, but intersymbol interference from distant edges has a small value. It is possible to sufficiently suppress the interference.

Therefore, in this embodiment, the output of the flip-flop 82 is decoded by the decoding circuit 85 and then supplied to the memory 87B, and a flip-flop 141 is further provided at the subsequent stage of the flip-flop 83. The stored value is decoded by the decoding circuit 152 and supplied to the memory 87B. Further, the data input to the flip-flop 81 is also decoded by the decoding circuit 151 and then supplied to the memory 87B.

Similarly, in the second stage as well, the output of the flip-flop 102 is decoded by the decoding circuit 105 and then supplied to the memory 107B. 16
1 is provided, and the stored value is decoded by the decoding circuit 172 and supplied to the memory 107B. Further, the data in the input stage of the flip-flop 101 is decoded by the decoding circuit 171 and supplied to the memory 107B.

In this embodiment, the memory 8
The outputs of 7A and 87B are supplied to the adder circuit 88. Also in the second stage, the memories 107A and 10A
The output of 7B is supplied to the adding circuit 108. The stored values of the memories 87A and 107A are the learning function circuit 121A.
It will be updated corresponding to the output of
The values stored in the memories 87B and 107B are stored in the learning function circuit 12
It is adapted to be updated corresponding to the output of 1B.

The learning function circuit 121B is the learning function circuit 1
21A, the learning function circuit 121 in FIG.

FIG. 30 shows a nonlinear equalizer in the case where the number of edges considering intersymbol interference is changed by measuring the error rate using the same error correction (CIRC) as used in CD. Represents the results of an experiment examining the ability of the. As in the embodiment shown in FIG. 17, the memory 87,
If the stored value of 107 is not updated (without learning),
As in the embodiment shown in FIG. 22, when the intersymbol interference of three edges is considered and learned (in the case of three positions), and in the embodiment of FIG.
Comparing the case of learning inter-symbol interference of one edge and learning (in the case of 5 positions), increasing the number of edges considering inter-symbol interference causes C1 error even if the skew becomes large. It can be seen that is suppressed. Incidentally, in FIG. 30, C1 error is 7 per second.
The case of 350 pieces is set as 100%.

FIG. 31 shows still another embodiment. In this embodiment, the data decoded by the decoding circuit 89 is input to the error detection / correction (ECC) circuit 13, the error is detected and corrected, and then output to a circuit (not shown). Has been done. The error-corrected data is supplied to the arithmetic circuit 131, and after the ideal value is calculated, the data is supplied to the adder circuit 132. Since a delay occurs due to the processing time in the error detection / correction circuit 13, the output of the adder circuit 108 is delayed by the FIFO 181 by the amount corresponding to this delay time, and then supplied to the adder circuit 132 to be supplied to the arithmetic circuit 131. Is added to the output of. The output of the adder circuit 132 is the switch 18
3 is supplied to the multiplication circuit 133 and the limiter 134, and further supplied to the memories 87 and 107. Therefore,
It is possible to prevent the stored values in the memories 87 and 107 from being updated in response to erroneous data.

Furthermore, in this embodiment, when the error detection / correction circuit 13 detects an error, the switch 18
3 is switched to the lower side in the figure, and the 0 level generated by the generation circuit 182 is output as an updated value. As a result, even if there is an uncorrectable error in the reproduced signal due to a defect on the optical disc 1 or the like, the stored values in the memories 87 and 107 are prevented from being updated to erroneous values.

By the way, since the optical disk 1 is manufactured by using plastic as a main raw material, its flatness changes depending on the temperature and humidity. The waveform distortion of the reproduction signal from the optical disc 1 changes according to the rotation angle because the skew changes according to the rotation position. Although it is possible to update the storage value of the memory at high speed as in the above-described embodiment, for example, as shown in FIG. 32, a predetermined number of optical disks 1 (8 in this embodiment are used).
The correction value of intersymbol interference can be learned for each area.

That is, as shown in FIG. 33, the rotary encoder 191 is connected to the spindle motor 2 and the output thereof is shaped by the waveform shaping circuit 192.
The output of 2 is counted by the 3-bit counter 193. As shown in FIG. 32, the count value of the 3-bit counter 193 is incremented by 1 when the optical disc 1 rotates 1/8. Therefore, the count value is as shown in FIG.
2 corresponds to eight regions shown by K = 0 to K = 7. In this embodiment, the memories 87, 107
For this purpose, eight memories 87 _{1 to} 87 ₈ and memories 107 _{1 to} 107 ₈ are prepared. Memory 87 ₁ to 87 ₈ and the memory 107 ₁ to 107 _8, stores a correction value for intersymbol interference corresponding to eight rotational angle range respectively, in FIG 32, in correspondence with the rotational position, the The banks are switched and the update is performed for each area.

Since the optical disk 1 rotates at a predetermined cycle, even if there is a skew, the change amount of intersymbol interference due to the skew changes at a constant cycle. Therefore, if bank switching is performed in accordance with the rotational position as in this embodiment, the change in intersymbol interference within each rotational position becomes small, and it becomes unnecessary to change the stored value at high speed. It becomes possible to perform learning (update of stored value) with respect to the disturbance of at high speed. In this embodiment, the optical disc 1 is set at a constant angular velocity (CA
V) has a particular advantage when rotationally driven, but is also effective when constant linear velocity (CLV).

FIG. 34 shows still another embodiment. In this embodiment, the output of the AGC circuit 11 is input to the non-linear equalizer 12 via the linear equalizer 301. Other configurations are shown in FIG.
It is similar to the case in 2.

In this embodiment, the linear equalizer 3
01 is an FIR including flip-flops 311 to 313, multiplication circuits 314 and 315, and an addition circuit 316.
It is composed of filters. Flip-flop 31
The data is sequentially transmitted to the subsequent stage by 1 clock by 1 to 313. And flip-flops 311 and 3
The data stored by the multiplier 13 is stored in the multiplier 314, respectively.
And 315, the coefficient −k is multiplied, and the data stored by the flip-flop 312 is added by the adder 316.

The period of the unit clock in this circuit is τ
Then, the impulse response h (t) can be expressed by the following equation. h (t) = δ (t) −k (δ (t + τ) + δ (t−τ)) (21)

Therefore, the frequency response H (f) of the linear equalizer 301 can be expressed by the following equation. H (f) = 1-2 kcos (2πfτ) (22)

By thus inserting the linear equalizer 301 in the preceding stage of the non-linear equalizer 12, intersymbol interference can be removed to some extent in advance. As a result, the intersymbol interference to be removed by the non-linear equalizer 12 is smaller than that in the case where the linear equalizer 301 is not inserted,
Overall, it is possible to further suppress intersymbol interference.

In the case of the embodiment in which the correction values stored in the memories 87 and 107 are automatically updated, the stored values are gradually corrected to correct values by the feedback operation, as described above. However, when the feedback operation is started, if the initial values stored in the memories 87 and 107 are values that deviate significantly from the ideal values, it is possible that the correction is not performed correctly.

For example, when the correction values shown in the above equations (14) and (15) are used as initial values, it is considered that intersymbol interference from the edges of adjacent pits is large and cannot be ignored (i or If the correction values are the same regardless of the value of j, the deviation from the ideal value may be too large.

In such a case, as shown in FIG. 35, for example, in at least one of the inner lead-in area and the outer lead-out area of the user data area 1B of the optical disc 1 (both in the case of the embodiment), The initial value setting data area 1B can be formed and pits for giving these initial values can be recorded in advance.

That is, in the initial value setting data area 1B, like the user data area 1A, servo areas are periodically provided, from which clocks are reproduced and the bias and gain are adjusted. There is. Then, in the data area between the servo areas, initial value data calculated as follows is recorded in advance.

That is, regarding the pits of the initial value setting data area recorded in this way, the position M of the leading edge and the position N of the trailing edge of each pit and the position I of the trailing edge of the immediately preceding pit are set. The position J of the front edge of the pit immediately after is already known. Therefore, of the signals obtained when this pit is reproduced, the signal at the leading edge is Va (N, M, I) and the signal at the trailing edge is Vb (J,
N, When M), Va (N, M , I) = Δ r · M + Ha (N, M, I) + C ··· (23) Vb (J, N, M) = Δ r · N + Hb (J, N, M) + C (24) Therefore, the value to be stored as a correction value in the memory, Ha (N, M, I ) = Va (N, M, I) -Δ r · M-C ··· (25) Hb (J, N, M) = Vb (J, N , can be computed as _{M) -Δ r · N-C} ··· (26).

FIG. 36 shows an example of pits that give such initial values. In this embodiment, two pits form one group. The data of each group constitutes one of the combinations (bn-1, an, bn). The 512 groups can form all patterns for correcting intersymbol interference at the leading edge of the pit. This 51
Following the two groups, 512 patterns for correcting edge intersymbol interference at the rear end of the pit are formed.

As described above, if the initial value is recorded in advance at a predetermined position of the optical disc 1, the initial value is reproduced as necessary (for example, immediately after starting), and the memories 87 and 10 are reproduced.
If this initial value is taken in 7, the correction value can be sequentially updated (corrected) to a correct value thereafter.

Finally, an embodiment of the recording apparatus for the above-described high recording density optical disc 1 will be described. In FIG. 37, the information source 201 digitizes and outputs an audio signal as a signal to be recorded. The ECC circuit 202 is
An error correction code is added to the digital audio data supplied from the information source 201 and output to the conversion circuit 203.
The conversion circuit 203 converts the input data into data in units of 3 bits. That is, in this embodiment, the edge position of each pit is set to any of eight levels from 0 to 7. Therefore, 3-bit data is required to specify the position of each edge. The conversion circuit 203 generates this 3-bit data.

The clock information generation circuit 205 generates the data necessary for generating the clock necessary for reading the data recorded on the optical disc 1 (for example, the data corresponding to the trailing edge of the reference pit P2 in FIG. 7). "0",
Data "7" corresponding to the front edge of the reference pit P3)
To occur. The bias gain information generation circuit 206 outputs data indicating a bias point (data “0” corresponding to the rear end of the reference pit P2 and data “0” corresponding to the front end of the reference pit P4 or reference pit P2 in FIG. 7). like,
Data indicating that the positions of both the front edge and the rear edge are 0) and data for setting the gain (as in the case of the reference pit P3 in FIG. 7, both the positions of the front edge and the rear edge are 7). Data indicating that there is).

The PLL pull-in signal generation circuit 207 is
Of the synchronization data (for example, data for setting the respective edges of the reference pits P1 to P5 in FIG. 7 as shown in FIG. 7) for causing the drawing. Educational data generation circuit 208
Generates data (0,0) to (7,7) as edge position data (M, N) at the front and rear ends of the education pit P6 in FIG. These clock information generation circuits 20
5, the data output from the bias gain information generation circuit 206, the PLL pull-in signal generation circuit 207, and the education data generation circuit 208 are all supplied to the adder 204,
The data supplied from the conversion circuit 203 is added (time division multiplexed).

The output of the adder 204 is supplied to the recording edge position calculation circuit 209, and the output of this recording edge position calculation circuit 209 is output to the edge modulation circuit 210. Then, the output of the edge modulation circuit 210 is supplied to the mastering device 211, and the optical disc 1 is produced through processes such as cutting, development, plating, transfer, aluminum vapor deposition, and protective film coating.

In the above configuration, the edge modulation circuit 21
0 generates a timing signal at a timing corresponding to the data output from the recording edge position calculation circuit 209,
This is output to the mastering device 211.

Here, the edge modulation circuit 210, as shown in FIG. 2, determines the edge positions of the front end and the rear end of each pit from the reference position at the center of these pits according to the digital information to be recorded. It is configured to generate a timing signal for shifting each of eight stages, but the shift period Ts of the edge position of each pit is
It is set to fall within a range corresponding to a period shorter than the transient period (rising period tr or falling period tf) of the RF signal determined according to the transfer characteristic of the optical detection system (pickup 3) on the reproducing device side. There is.

The mastering device 211 cuts the photosensitive film coated on the recording master with laser light in synchronization with the timing signal supplied from the edge modulation circuit 210. The cut master is developed and plated to form a stamper. Then, the pits formed on the stamper are transferred to a replica, the replica is subjected to aluminum vapor deposition, and a protective film is applied, whereby the optical disc 1 is manufactured.

In the above, the case where the present invention is applied to the optical disk and the reproducing apparatus thereof has been described as an example, but the present invention can be applied to the magneto-optical disk and other information recording media and the reproducing apparatus thereof. is there.

[0186]

As described above, according to the information reproducing apparatus of the first aspect, the correction value corresponding to the data obtained by decoding the reproduction signal is generated, and the signal obtained by adding the correction value to the transmission signal is further decoded. Since this is done, even when the intersymbol interference changes at high speed, it is possible to quickly reduce this. Further, the capacity of the correction value generating means can be reduced.

According to the information reproducing apparatus of the second aspect,
Since the correction value for correcting the inter-code interference from the code adjacent to the code to be decoded is generated, the largest inter-code interference can be surely suppressed.

According to the information reproducing apparatus of the third aspect,
Since the correction value is generated using the reproduction level of the education pit, it is possible to prevent the correction value from being set to an abnormal value.

According to the information reproducing apparatus of the fourth aspect,
Since at least 64 educational pits are provided, it is possible to set the correction value with certainty.

According to the information reproducing apparatus of the fifth aspect,
Since the interference from the closer code and the interference from the farther code are individually corrected, it is possible to reduce the memory capacity as a whole.

According to the information reproducing apparatus of the sixth aspect,
Since the configuration has a plurality of stages, it is possible to more reliably suppress intersymbol interference.

According to the information reproducing apparatus of the seventh aspect,
Since the signal to be corrected is the reproduced signal from the optical detection system in all stages, intersymbol interference can be surely suppressed.

According to the information reproducing apparatus of the eighth aspect,
Since the decoding target code supplied to the adding means of each stage is substantially the same code that is not corrected in any stage, it is possible to reliably suppress inter-code interference.

According to the information reproducing apparatus of the ninth aspect,
Since the number of stages in the cascade connection is an even number, it is possible to prevent the correction value from becoming an abnormal value.

According to the information reproducing apparatus of the tenth aspect, by feeding back the output result of the second decoding means,
Since the correction value is changed, intersymbol interference can be suppressed quickly, reliably and automatically.

According to the information reproducing apparatus of the eleventh aspect, from the difference between the ideal reproducing level and the actual reproducing level,
Since the correction value is changed, the correction value can be changed automatically and surely.

According to the information reproducing apparatus of the twelfth aspect, since the correction value is multiplied by a predetermined constant and is limited, it is possible to prevent the correction value from being set to an abnormal value. It will be possible.

According to the information reproducing apparatus of the thirteenth aspect, since the correction value is changed in accordance with the decoded value after the error correction, the correction value is surely set to a value closer to the correct value. It becomes possible to do.

According to the information reproducing apparatus of the fourteenth aspect, the difference between the ideal reproducing level and the actual reproducing level or a predetermined constant is selected to change the correction value. Therefore, it is possible to reduce the influence of a defect of the recording medium.

According to the information reproducing apparatus of the fifteenth aspect, a predetermined constant is selected when an error is detected. Therefore, when a defect exists on the recording medium, the correction value is It is prevented from being set to an abnormal value.

According to the sixteenth aspect of the information reproducing apparatus, since the correction value is generated corresponding to the rotational position of the disk medium, the correction value corresponding to the skew of the disk medium can be generated quickly. Is possible.

According to the information reproducing apparatus of the seventeenth aspect, since the pits giving the initial value are collectively recorded in the predetermined range of the disc medium, the initial value can be surely set before the disc medium is reproduced. Can be set.

According to the information recording medium of the eighteenth aspect, since the initial values for changing the correction values are collectively recorded in a predetermined range, which information reproducing apparatus is used for reproduction. Also, it becomes possible to reliably suppress intersymbol interference.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a format of a servo area of an optical disc.

FIG. 2 is a diagram illustrating a principle of reproducing data.

3 is an enlarged view showing how the pit edge of the optical disc of FIG. 1 is changed stepwise.

FIG. 4 is a diagram showing an arrangement state of pits of adjacent tracks when the optical disc of FIG. 1 is a CLV disc.

FIG. 5 is a block diagram showing a configuration of an embodiment of an optical disc reproducing apparatus to which the information reproducing apparatus of the present invention is applied.

6 is a bias removal circuit 10 and an AGC circuit 11 of FIG.
3 is a block diagram showing a configuration example of FIG.

7 is an enlarged view showing pits in a servo area recorded on the optical disc of FIG. 1. FIG.

FIG. 8 is a timing chart explaining the operation of the embodiment of FIG.

FIG. 9 is a diagram illustrating a phase relationship between a reading beam and a clock.

FIG. 10 is a diagram showing input / output characteristics of a decoding circuit.

FIG. 11 is a diagram illustrating input / output characteristics of a decoding circuit.

12 is a diagram showing a configuration example of a decoding circuit that realizes the characteristics shown in FIG.

FIG. 13 is a block diagram showing a configuration of a decoding device when there is no non-linear intersymbol interference.

14 is a block diagram showing a configuration example of a non-linear equalizer 12 of FIG.

FIG. 15 is a block diagram showing a configuration example of a non-linear equalizer 12 that decodes a signal corresponding to a trailing edge of a pit.

16 is a diagram for explaining the principle of cascade connection of the embodiment shown in FIG.

FIG. 17 is a block diagram showing a configuration in which the embodiment shown in FIG. 15 is cascade-connected.

FIG. 18 is a diagram showing a state two clocks after the state shown in FIG. 17;

FIG. 19 is a diagram showing a state where a reproduced signal at the input stage of the nonlinear equalizer is observed with an oscilloscope.

20 is a diagram showing a state where the output of the embodiment shown in FIG. 14 is observed with an oscilloscope.

21 is a diagram showing a state in which the output of the embodiment of FIG. 17 is observed with an oscilloscope.

FIG. 22 is a block diagram showing another configuration example of the non-linear equalizer 12.

23 is a timing chart illustrating the operation of the embodiment of FIG.

FIG. 24 is a diagram showing characteristics of the example of FIG. 22.

FIG. 25 is a diagram illustrating an operation of updating a stored value in a one-stage configuration memory.

FIG. 26 is a diagram illustrating an operation of updating a stored value in a memory having a two-stage structure.

FIG. 27 is a diagram illustrating a decoding result when the number of stages for correction is changed.

FIG. 28 is a block diagram illustrating another configuration example of the non-linear equalizer.

FIG. 29 is a block diagram showing a configuration example of still another embodiment of the nonlinear equalizer.

FIG. 30 is a diagram illustrating a decoding result when the number of edges considering inter-code interference is changed.

FIG. 31 is a block diagram showing the configuration of still another embodiment of the nonlinear equalizer.

FIG. 32 is a diagram illustrating a rotational position of a disc.

FIG. 33 is a block diagram showing the configuration of another embodiment of the non-linear equalizer.

FIG. 34 is a block diagram showing the configuration of still another embodiment of the nonlinear equalizer.

FIG. 35 is a diagram illustrating an initial value setting data area of the optical disc 1.

36 is a diagram illustrating pits recorded in the initial value setting data area of the optical disc 1 of FIG. 35.

FIG. 37 is a diagram showing a configuration of an example of an optical disc manufacturing apparatus.

FIG. 38 is a diagram illustrating the principle of recording data by changing the edge position of a pit corresponding to recording data.

FIG. 39 is a diagram illustrating the principle of reproducing a pit in which the edge position of the pit is changed stepwise.

FIG. 40 is a diagram for explaining the principle of mapping and decoding the reproduction signal shown in FIG. 39.

[Explanation of symbols]

 1 Optical Disc 2 Spindle Motor 3 Pickup 7 PLL Circuit 8 Spindle Servo Circuit 9 A / D Conversion Circuit 10 Bias Removal Circuit 11 AGC Circuit 12 Non-Linear Equalizer 13 Error Detection and Correction Circuit 70 Decoding Circuit 81 to 83 Flip Flop 84 to 86 Decoding Circuit 87 memory 88 adder circuit 89 decoding circuit

Claims (18)

[Claims] 1. An edge of an information pit within a range corresponding to a predetermined shift period which is shorter than a transient period of a reproduction signal determined according to a transfer characteristic of an optical detection system which scans an information pit row with a light beam. An information reproducing apparatus for reproducing recorded information from a disc medium on which digital data is recorded by shifting a position in a stepwise manner from a predetermined reference position corresponding to a code to be recorded, and a reproduction signal obtained from the optical detection system. A clock generation means for generating a clock phase-synchronized with the reference position based on the above, and a level detection means for detecting a reproduction level in a transition period of the reproduction signal at a timing defined by the clock, First decoding means for decoding the record data corresponding to the shift amount of the edge position of the information pit based on the reproduction level; Correction value generating means for storing a predetermined correction value for correcting an error at the time of outputting and outputting the correction value corresponding to the data decoded by the first decoding means; An addition means for adding to the reproduction level of the target code; and a second decoding means for decoding the record data corresponding to the shift amount of the edge position of the information pit based on the output of the addition means. Information playback device. 2. The information reproducing apparatus according to claim 1, wherein the correction value generating means generates a correction value for correcting inter-code interference from a code adjacent to a code to be decoded. 3. The correction value generation means generates and stores the correction value in advance using a reproduction level of an educational pit provided as an information pit for obtaining decoded values of all edge patterns. The information reproducing apparatus according to claim 2, wherein: 4. The information reproducing apparatus according to claim 3, wherein at least 64 educational pits are provided on the disk medium. 5. The first correction value generating means stores a first correction value for correcting inter-code interference from adjacent codes before and after the code to be decoded, and the first memory to be decoded. A second memory for storing a second correction value for correcting intersymbol interference from a code two codes away from the code before or after the code; and the adding means includes the first correction value and the second correction value. 4. The information reproducing apparatus according to claim 3, wherein the correction value of 1 is added to the reproduction level. 6. The information reproducing apparatus according to claim 3, wherein a set including the first decoding means, the correction value generating means, and the adding means is cascaded in a plurality of stages. 7. The information reproducing apparatus according to claim 6, wherein the signal to be corrected is a reproduced signal obtained from the optical detection system in all stages. 8. The code to be decoded supplied to the adding means of all stages is substantially the same code which is not corrected by the adding means of any stage. The information reproducing device according to claim 7. 9. The information reproducing apparatus according to claim 8, wherein the number of stages of the groups connected in cascade is an even number. 10. The information reproducing apparatus according to claim 1, further comprising a changing unit that feeds back an output result of the second decoding unit and changes a correction value of the correction value generating unit. apparatus. 11. The changing means is an ideal value calculating means for calculating an ideal reproduction level from an output of the second decoding means, and a difference means for obtaining a difference value between the ideal reproduction level and an actual reproduction level. 11. The information reproducing apparatus according to claim 10, further comprising: changing the correction value of the correction value generating means in accordance with the difference value. 12. The changing means multiplies the difference value by a constant for preventing the correction value of the correction value generating means from oscillating, and the output of the multiplying means falls within a predetermined range. The information reproducing apparatus according to claim 11, further comprising limiter means for limiting. 13. An error detection / correction unit that detects the presence or absence of an error in the output of the second decoding unit and corrects the error, and a correction value of the correction value generation unit according to the decoded value after the error correction. 10. The information reproducing apparatus according to claim 9, further comprising changing means for changing the. 14. The changing means, an ideal value calculating means for calculating an ideal reproduction level from an output of the correcting means, a difference means for obtaining a difference value between the ideal reproduction level and an actual reproduction level, 14. The information reproducing apparatus according to claim 13, further comprising selection means for selecting one of a difference value of the difference means and a predetermined constant according to the result of the error detection / correction means. 15. The selecting means selects the difference value of the difference means when no error is detected by the error detecting and correcting means, and selects the predetermined constant when an error is detected. The information reproducing apparatus according to claim 14, characterized in that. 16. The correction value generating means generates different correction values corresponding to rotational positions of the disk medium divided into a predetermined number, according to any one of claims 1 to 15. Information reproduction device. 17. The information reproducing apparatus according to claim 16, wherein pits for giving an initial value of the correction value generating means are collectively recorded in a predetermined range of the disk medium. 18. An information recording medium reproduced by the information reproducing apparatus according to claim 17, wherein an initial value when the correction value of the correction value generating means is changed,
An information recording medium characterized by being collectively recorded in a predetermined range.