JPH0773211A - Delay inspecting system of logical circuit - Google Patents

Abstract

PURPOSE:To perform a delay inspection by detecting a path generating a designated signal value to be an object on a logical circuit at high speed. CONSTITUTION:A circuit 1 to be inspected which is provided with an input gate 10, an output gate 12 and logical gate 11 being arranged between the input gate 10 and the output gate 12 and performing a logical operation is provided with an inverse circuit 2 composed of logical gates 20 to 22 corresponding to each gate. When the generation of a preliminarily designated signal value is detected from the output gate 12 when one of signal values having plural waveforms is selected, respectively, and is inputted in each input gate 10 by changing the combination of the signal values for the circuit 1 to be inspected, each logical gate 20 to 22 of the inverse circuit 2 is driven by the event from the poststage, generates an event when the corresponded gate of the circuit 1 to be inspected is the designated signal value and supplies the event to the logical gate of the preceding stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay fault inspection system for logic circuits. In recent years, as LSIs and VLSIs have increased in size, there has been a demand for speeding up logic simulation, test generation, and failure simulation. For this reason,
The method of propagating on the path by giving information other than the original signal value to the signal value of the gate is often used, but it is confirmed that all the gates on the target circuit have the corresponding signal value. Must be done, and it takes a huge amount of time.
In order to speed up the entire system, it is necessary to speed up this part.

[0002]

2. Description of the Related Art FIG. 12 is an explanatory diagram of a logic circuit. LC
Is a logic circuit, and this logic circuit LC has a plurality of inputs I
1 to In and outputs O1 to Om, and various gates (OR logic, AND logic, NOT logic, buffer, etc.) G1, G2, G3, ... Are provided between them.
When such a logic circuit LC is designed, it is necessary to inspect a delay time until a signal corresponding to the input signal appears on the output side when a signal is applied to the input. That is, the paths of the respective input and output are individually different, and there are cases in which the input signal passes through a large number of gates before it reaches the output, and cases in which it passes through a short path. Therefore, if it is detected that the delay time exceeds a predetermined range (which may be too long or too short), the delay time may fall within a certain sync range of the clock signal.
This is because the output signal is not generated and the logic circuit LC may not operate normally.

It is necessary to change the clock frequency (cycle) for driving the logic circuit or change the configuration of the logic circuit to shorten the path (signal propagation path).

For this reason, although a delay fault in a logic circuit has been conventionally tested, a signal propagation delay time is usually obtained if the number of gate stages included in a signal path between each input and output is known. Basically, the number of gate stages passing from the input terminal to the output terminal is calculated for each output.

However, even if there is an output terminal passing through a large number of gate stages, the output signal rises or falls in response to a change in an input signal (a plurality of signals are related) related to the output terminal. There may be no significant change in the output signal. A logically redundant signal is transmitted to such an output signal, for example, a signal in which the output state is indefinite for a certain period of time, or the output is "L" (low level) even if any signal is given as an input signal. The signal is fixed at "H" (high level).

The delay time of the long path connected to the output terminal for generating such an output signal does not affect the actual operation (not affected by the clock signal), and therefore is related to the change of the input signal. It is necessary to detect whether it has a significant effect on the output.

Conventionally, in order to detect a path having a large number of gate stages in which a significant change in output signal occurs during simulation of a logic circuit, one input vector (a plurality of input signal patterns input in parallel) is input. Each time it was applied, the signal value of each gate up to the output was observed to check if a significant signal was generated, and it was necessary to verify all the patterns of the input signal.

An input signal that can take an arbitrary value (a method of propagating on a path by providing information other than the original signal value) with respect to a large number of input signals related to outputs passing through a path having a large number of stages A method is used in which the output signal is identified by changing the combination of the above and performing simulation with all signal patterns.

As a result of this discrimination, when it is found that a significant signal does not occur at the output terminal, the delay time of that path does not matter and there is no need to change the clock cycle, but a significant signal is output by that path. When it occurs, the delay time of the path is to be improved by changing the clock cycle or changing the circuit to shorten the delay time.

[0010]

When a path satisfying the conditions is searched by the above conventional method, when the circuit scale of LSI, VLSI, etc. is large, the total number of paths on the circuit is enormous, and in general, the circuit is large. If the scale is large, the number of input patterns will be huge and the processing time will be too long. Therefore, in order to finish the processing for the target logic circuit in a relatively short time, it is necessary to extremely reduce the input pattern or divide the target circuit into smaller scales.

When the input pattern is extremely reduced, the search is performed within the limited conditions, and a sufficient result cannot be obtained.
If the circuit scale is divided, there is a problem that it takes time and effort.

An object of the present invention is to provide a delay inspection method for a logic circuit, which can detect a path generating a specific signal value of interest on the logic circuit at high speed.
Another object of the present invention is to provide a delay inspection method for a logic circuit that can detect a gate that generates the signal value on the detected path at high speed.

[0013]

FIG. 1 is a block diagram of the principle of the present invention, and FIG. 2 is a diagram showing patterns of various signal values. In FIG. 1, reference numeral 1 is a circuit under test composed of a plurality of input pins, a plurality of gates (logic circuits) and output pins, and reference numeral 2 is a gate provided corresponding to each gate of the circuit under test. An inverse circuit that follows the movement of a specified signal from the output side to the input side in the opposite direction to the inspection circuit, and detects a path consisting of a set of gates with arbitrarily specified signal values, 3 is a fan-in gate mark circuit Yes Reverse circuit 2
It is a circuit that holds the occurrence of a change in the designated signal on the path detected in step 1 along with the type of the signal.

The circuit 10 to be inspected 10 has input gates (corresponding to input pins) of i1, i2, ... To which an input signal represented by i [n] is supplied, and 11 represents by g [n]. Logic gates g1, g2 ... That perform the logic operation represented by 12, and 12 are output gates (corresponding to the output pins) o1, o2 ... That generate the output signals respectively represented by o [n]. . Note that i [n], g [n], o [n]
N of each gate type represents the number of 1, 2, ...
Are not necessarily the same.

Inverter circuit 20 is represented by I [n] provided corresponding to input gate i [n] of the circuit to be inspected, I1, I2 ... Im. G [n] provided corresponding to the logic gate g [n] of the circuit
, Gm, ..., Gm ..., And 22 is represented by O [n] provided corresponding to the output gate o [n] of the circuit under test.
An Om gate 23 is a clock source supplied to the final stage of each output gate O [n].

Each gate of the inverse circuit 2 has its own output as a fan-in and the corresponding gate output of the circuit under test 1, and its fan-out is the fan-in of the gate on the circuit under test corresponding to itself. The fan-in gate mark circuit 3 is connected to the gate of the preceding stage on the corresponding reverse circuit, and at the same time.
Connected to the corresponding gate of.

In the fan-in gate mark circuit 3, reference numeral 30 denotes G [n] f provided corresponding to the fan-in (input) of each logic gate g [n] of the circuit under test 1.
A gate mark circuit represented by [n], 31 is a gate mark circuit represented by O [n] f provided corresponding to the output gate o [n] of the circuit under test 1, and each circuit generates a signal change. It has a function of storing what has been done together with the type of change.

According to the present invention, one of a plurality of waveform signals is supplied to each input of the circuit under test in a different combination, and when a specified waveform signal is generated from the output gate, the corresponding inverse circuit is used. Detects a path consisting of a set of gates with a specified signal.

Further, according to the present invention, when a specified waveform signal is detected even once with respect to various signal inputs to the circuit under test, each gate (including output) corresponding to each path is detected by the fan-in gate mark circuit. To hold the detection output including the specified signal value type.

[0020]

FIG. 2 shows the types of signal (input / output) patterns that can be generated by the present invention. 0s, 0p, 0-, 1
It is divided into seven patterns of s, 1p, 1-, and x. The meaning and waveform of each signal value are as shown in FIG. 2, and each signal is represented by a 3-bit code. In the pattern of these seven signals, 0p is a fall (falling from 1 to 0) signal, 1p is a rise (rising from 0 to 1) signal, and these two signals are called pulse signals. There are cases. In the case of other signals, 0s and 1s show no change, x is indefinite, the initial value is unknown, and 0- and 1- are indefinite within a certain time and finally become 0 or 1.
These are not treated as pulse signals.

When an inspection (simulation) is performed, when the combination of various signals shown in FIG. 2 is sequentially changed and supplied as the input signal of each gate i [n] of the circuit under test 1, the output side gate o [ When a signal designated in advance as the output of [n] is generated, the inverse circuit 2 is driven to detect the path of the signal.

In the 0 delay simulation, when the input vector IP (0) is given to the circuit under test 1 at time T (0), the signal propagates to the output during time T (0). At the next time T (1), when the clock source 23 is given to the gate 22 corresponding to the output gate 12 on the circuit under test 1 on the inverse circuit 2, the gate corresponding to the output gate on the inverse circuit 2 becomes Refer to the signal value of the gate on the inspected circuit 1, and if that value is the specified value, invert its own value and send an event to the fan-out destination (generation of change information)
To notify.

Among the gates of the fan-out destination, the gate mark circuit 30 or 3 on the fan-in gate mark circuit 3
When 1 receives an event, it refers to the signal value of the corresponding gate on the circuit under test 1 and its own signal value, and that signal value has not yet been taken among the previously specified signal values. When it is a value, it inverts its own signal value and outputs it.

The gate on the inverse circuit 2 which is another fan-out destination refers to the signal value of the gate on the corresponding circuit under test 1 and its own signal value, and if the gate on the corresponding circuit under test is checked, If the signal value is a value specified in advance, it inverts its own signal value and outputs it. The above operation is performed at time T
By sequentially executing toward the input side during (1), a path consisting of a set of gates having a pre-specified signal value is detected, and the gates on the detected paths are detected for the first time on the detection path. You can extract the gate you got on.

The configuration of FIG. 1 will be described in detail.
For example, when a signal value designated in advance occurs at om in the output gates o [n] of the circuit under test 1, the change signal (pulse signal) is input to the corresponding gate Om of the inverse circuit 2. The output signal from the corresponding gate of the circuit under test 1 and its own output signal are input to the respective gates of the inverse circuit 2, and the signal value specified in advance from the gate om of the circuit under test 1 (for example, 0p and 1p). Occurs, the state of the corresponding gate Om on the inverse circuit 2 changes (inverts) in synchronization with the clock of the clock source 23. The output signal does not change unless the specified signal value is input from the gate om on the circuit under test 1. When an inverted signal is generated in the gate Om of the inverse circuit 2, this is supplied as an event to the gate Gm in the preceding stage of the inverse circuit 2 to drive it. Further, this event corresponds to the corresponding gate mark circuit G [n] f of the fan-in gate mark circuit 3.
It is also supplied to [n].

Therefore, when the inspection circuit 1 performs inspection and a change signal is generated from o [n] of the inspection circuit 1, each gate I [n], G [n], O [n of the inverse circuit 2 is generated. ] By detecting the state of the output signal of [], it is possible to sequentially follow the path through which the change signal is transmitted from the output side to the input side.

The fan-in gate mark circuit 3 of FIG. 1 has a number corresponding to all the fan-in gates of the output gate o [n] and the logic operation gate g [n] of the circuit under test 1. Gate mark circuit G [n] f [n]
And O [n] f (the circuit corresponding to the input gate i [n] is not provided), each gate mark circuit is a fan-in of the corresponding gate of the circuit under test 1 as a signal from the fan-in gate. The gate signal (fan-in f1 in the case of the gate mark circuit Gmf1 in FIG. 1) and its own output signal are supplied, and the corresponding gate G [n] of the inverse circuit 2 is supplied.
Alternatively, it is driven when an event (inversion of the output signal) from O [n] occurs, and when the specified signal value is generated in the fan-in gate of the corresponding circuit under test, the state is stored and held. At this time, the type of the generated designated signal value can also be stored and held.

The contents of the respective gate mark circuits G [n] f [n] and O [n] f of the fan-in gate mark circuit 3 change on the route through each gate depending on the fan-in of the gate of the circuit under test. Whether or not a signal is generated and when it is generated are held together with the type thereof, so that the detailed change path can be known by checking the contents of each after the inspection.

[0029]

FIG. 3 is a block diagram of the embodiment. In this embodiment, an inverse circuit 2 and a fan-in gate mark circuit 3 are provided for a configuration example of a logic circuit as shown as the circuit under test 1.
The configuration is shown and only one output gate is shown.

The circuit to be inspected 1 and the inverse circuit 2 are
The fan-in gate mark circuit 3 and the fan-in gate mark circuit 3 can all be configured as hardware by combining the circuits, but can also be configured as software for simulation.

In the circuit under test 1, 10-1 to 10-
3 is an input gate corresponding to an input pin (in1 to in
3), 11-1 to 11-4 are logic gates (g1 to g4)
G1 is a buffer, g2 is an AND circuit, g3 is a NAND circuit, and g4 is an OR circuit. Reference numeral 12 is an output gate (out1) corresponding to the output pin.

In the reverse circuit 2, 20-1 to 20-3 are reverse input gates (I1 to I3) corresponding to the input gates in1 to in3 of the circuit under test 1, and 21-1 to 21-4 are the circuit under test 1. Inverse logic gates (G1 to G4) and 22 corresponding to the logic gates g1 to g4 in FIG. 2 are inverse output gates (O1) corresponding to out1 of the circuit under test 1.

In the fan-in gate mark circuit 3,
31 is a fan-in (i) of the logic gate g1 of the circuit under test 1.
n1) gate mark circuits (G1f1), 3
2 and 33 are gate mark circuits (G2f1, G2) corresponding to two fan-ins to the logic gate g2 of the circuit under test 1.
2f2), 34, and 35 are logic gates g3 of the circuit under test 1.
Fan-in (output of logic gate g3, input gate i
n3 output) corresponding to the gate mark circuit (G3f1,
G3f2, 36, 37 are logic gates g4 of the circuit under test 1.
2 fan-ins (outputs of logic gates g2 and g3)
Corresponding to each gate mark circuit (G4f1, G4f
2) and 38 are gate mark circuits (O1f1) corresponding to the fan-in (output of the logic gate g4) of the output gate 12 of the circuit under test.

FIG. 4 is a diagram showing a truth table of the logic gate for each signal, and the logic gate of the circuit under test 1 of FIG. 3 operates according to this truth table. In FIG. Is a truth table of AND logic, and the gate g of FIG.
2 and g3 perform this logical operation. A. The signal of each waveform in the column direction at the left end of (in FIG. 2, 7 of Os, Op ...
Seed signal) is supplied as one input signal and A. When the signals of the respective waveforms shown in the row direction at the top are supplied, the output signals of the AND logic become the signals of the types shown at the positions where they intersect. For example, signal 0p
When (fall) and 1p (rise) are input, a signal 0- is generated as an AND logic output.

B. of FIG. Is a truth table of OR logic, and A. Similarly, the output of each OR logic corresponding to a combination of seven signals is shown. C. Is a truth table of the inverter (INV) and the buffer (BUF), and generates an output (output) for each input (input) as shown in the figure. Although the inverter is not included in the circuit shown in the example of the circuit under test 1 in FIG. 3, it is normally used. In the case of NAND gate,
It is obtained by passing the AND output through an inverter.

Next, FIG. 5 is a diagram showing a truth table of the gate of the inverse circuit. Each gate G1 to G4, O of the inverse circuit 2 of FIG.
1 operates basically the same as an inverter. However, the difference from a general inverter is that the output is inverted only when the corresponding gate on the circuit under test takes the specified signal value, and in the case of the truth table shown in FIG. In this example, 0p (fall) and 1p (rise) are designated as the input signal. When either of these two signals is input, the current output value (as a) of this gate itself in the inverse circuit is inverted (-a), and when other signals are generated, the current output value of itself is Do not change (a).

The circuit configuration for performing such a logical operation receives the output of itself and the output of the corresponding gate of the circuit to be inspected as an input and is driven by a change signal (an inverted signal from output a to -a) from the subsequent stage. It can be configured by combining the logic circuits so as to invert the output signal when it is (enabled) and the output signal of the corresponding gate of the circuit under test is 0p or 1p. Each output signal is supplied as a signal for driving the next preceding stage (input side stage) on the reverse circuit.

It should be noted that only the gate O1 on the output side of the inverse circuit 2 is driven by the clock of the clock (CLOCK) source 23 as shown in FIG. 3, and the signal (out) of the output gate of the circuit under test 1 is shown. A logical operation such as 5 is performed.

FIG. 6 is a diagram showing the truth value of the gate on the fan-in gate mark circuit. Each of the gate mark circuits 31 to 38 of the fan-in gate mark circuit 3 of FIG.
Shows an example in which two signals of 0p (fall) and 1p (rise) are designated as the designated signal waveform.

As shown in FIG. 3, the gate mark circuits 31 to 38 of the fan-in gate mark circuit 3 receive the signals output from the corresponding gates G1 to O1 of the inverse circuit 2, respectively, but the change signals It is driven (enabled) only when it is input, and if the signal value of each fan-in of the circuit under test 1 at that time is 0p (fall) or 1p (rise), that Keep memory,
In a series of simulation operations, signals 0p, 1p
When occurs even once, when the state is stored for the first time, the stored state does not change even if the same signal occurs.

Each gate mark circuit 3 of the embodiment shown in FIG.
Each of 1 to 38 is provided with 2 bits to store whether the fan-in signal value is 0p or 1p and its type, but if the type does not matter, 0p and 1p are set. Only one bit is required to store that any one has occurred.

In this example in which two bits are provided, the first bit represents the generation state of the signal 1p (rise), the latter bit represents the state of the signal 0p (fall), and the state of the two bits is two flip-flops. It can be configured by a circuit, and its storage state is configured to change according to the truth table of FIG. That is, when the 2-bit output of the current gate mark circuit itself is "00" and the fan-in gate signal of the gate of the corresponding circuit under test is 0p, "0" is output.
It is set to "1", and if it is 1p, it is set to "10". When the current output is “10”, the fan-in gate signal is set to “11” if it is 0p and “10” if it is 1p.
It remains unchanged.

Therefore, when a signal of 0p or 1p is generated as each fan-in gate signal in a series of simulation operations for the circuit under test, the generated state is held in the gate mark circuit. The status of each gate mark circuit is not output to other gate mark circuits,
By reading the state of each gate mark circuit after the inspection, the path through which the 0p or 1p signal propagates can be analyzed.

In the configuration of the embodiment of FIG. 3 described above, the circuit to be inspected, the inverse circuit and the fan-in gate mark circuit can be configured by hardware, but the configuration of each circuit is configured by software and logically simulated. The operation flow of the reverse circuit and the fan-in gate mark circuit in that case will be described with reference to FIGS.

FIG. 7 shows the operation flow of the inverse circuit in the logical simulation. To explain this, the logical simulation is performed on the circuit under test (S1 in FIG. 7).
It is determined whether or not the processing has been completed for all the gates of the reverse circuit corresponding to the output of the circuit under test (S2 in FIG. 7). If not, the signal value of the gate on the target circuit under test is the expected value. (It is determined whether or not it is equal to, for example, 0p, 1p with a previously designated signal value) (at step S3), and if it is equal, the signal value of the gate on the reverse circuit is inverted (at step S4).

Next, it is judged whether or not there is a fan-out gate (previous stage gate) of the gate of the reverse circuit in which this signal value is inverted (S5 in FIG. 7), and if not, the tracking for that gate is ended and the process proceeds to step S2. Returning to this, the process is started for the gate of the reverse circuit corresponding to the output of another circuit under test. If there is a fan-out gate, take out the fan-out gate of the gate on the reverse circuit (S in FIG. 7).
6) Return to step S3, determine whether the signal value of the gate on the circuit under test corresponding to that gate is equal to the expected value,
The same processing as above is continued.

In this way, for each gate of the inverse circuit corresponding to the output of the circuit under test, when the expected value is sequentially generated, the signal value of the gate is inverted and the process of going up to the fan-out gate is performed, and the inverse circuit is executed. When the processing is completed for all the gates (gates corresponding to the output of the circuit under test), the operation flow of the reverse circuit ends.

Next, FIG. 8 is an operation flow of the fan-in gate mark circuit. Since this fan-in gate mark circuit receives the output of each gate of the reverse circuit and performs a logical operation, it has a content that cooperates with the operation flow of FIG. 7, and performs the processing of S5 to S7 indicated by the bold frame. Features points.

S1 to S4 in FIG. 8 are the operations in the circuit under test and the reverse circuit, and are the same as S1 to S4 in FIG. When the signal value of the gate on the reverse circuit in step S4 is determined, the gate on the fan-in gate mark circuit (the same as the gate mark circuit) corresponding to this signal value or the inverted gate on the reverse circuit is extracted (FIG. 8). S5). Next, the signal value of the gate on the circuit under test corresponding to the gate of the extracted fan-in gate mark circuit is referred to (S in FIG. 8).
6), the signal value of the gate of the fan-in gate mark circuit is updated according to the reference result (S7 in FIG. 8).

The update of the signal value of the gate of the fan-in gate mark circuit is as described with reference to FIG. 6, and the signal value corresponding to the occurrence of 0p and 1p is generated and held. Thereafter, the operation of the above-mentioned reverse circuit relating to the fan-out gate of S8 and S9 of FIG. 8 (S5 and S of FIG. 7) is performed.
6) is executed, and the processing from S3 onward is executed for each gate in the fan-in gate mark circuit corresponding to each fan-out gate in the reverse circuit. When the processing is completed for all the gates of the inverse circuit corresponding to the output of the circuit under test, the operation of the fan-in gate mark circuit is completed.

FIG. 9 shows the state of each gate when an input pattern is given to the circuit under test, and FIG. 11 shows the states of the reverse circuit and the fan-in gate mark circuit when the input pattern of FIG. The state of the reverse circuit and the fan-in gate mark circuit when the input pattern is given is shown.

FIG. 9A. As shown in, the input pattern at time 1, in1, in2, in3 is {1s, 0p, 0
If you input s}, according to the truth table shown in FIG.
For each logic gate and output gate The signal shown in is generated. It is assumed that the input / output pin and each gate are initialized to the value X at time 1 for convenience. In the following description, it is assumed that 0p (fall) and 1p (rise), which are pulse-like signal values, are specified as the prespecified signal values to be detected among the signal values propagating through the path.
The delay check is performed by knowing the path including the gate where these two signal values are generated on the logic circuit.

At time 2 (the event for the input pin at time 1 is transmitted to the output pin side), when the clock source 23 is supplied to the inverse circuit O1 as shown in FIG. 10, the gate O1 is supplied. Since the output gate o1 on the inspected circuit 1 corresponding to 1 generates the signal value 0p, the gate O1 inverts its own signal value and reverses the event (information indicating that the signal value has changed). It is transmitted to the gate G4 in the previous stage above 2. Since the signal value of the logic gate g4 from the circuit under test 1 corresponding to the gate G4 is 0p, the gate G4 inverts its own signal value and transmits the event to the gates G2 and G3. Since the signal of the logic gate g2 on the circuit under test 1 corresponding to the gate G2 is 0p at this time, the gate G2 inverts its own signal value and transmits the event to the gates I1 and I2.

On the other hand, the circuit under test 1 corresponding to the gate G3
Since the signal value of the upper logic gate g3 is 0 s, the signal value of the gate G3 does not change. Therefore, the gate G1 on the inverse circuit 3 corresponding to the output signal of the logic gate g1 and the signal in3 of the input pin, which is the fan-in of the logic gate g3.
The event is not transmitted corresponding to I3. Of the gates I1 and I2 that have received the event from the gate G2, the gate I1 does not change the signal value because the signal value of the corresponding input gate in1 on the circuit under test 1 is 1s.

The gate I2 inverts the signal value of the corresponding input gate in2 on the circuit under test 1 because the signal value is 0p. Up to this point, the gate on the circuit under test 1 corresponding to the gate on the reverse circuit whose signal value has changed is the input gate in
Signal values 0p, 1p on the path from 2 to the output gate o1
It is a set of gates with. That is, the gates I2, G2, G4, which are hatched in the inverse circuit 2 shown in FIG.
Input gate in of the circuit under test 1 corresponding to the path of O1
2, a path of the logic gates g2 and g4 and the output gate out1.

FIG. 9A. The operation of the fan-in gate mark circuit when the reverse circuit operates as described above when an input pattern such as the above is supplied will be described with reference to FIG. An event (information indicating that the signal value has changed) is sent from the gate whose signal value is inverted in the inverse circuit 2 to the gate mark circuit on the fan-in gate mark circuit 3 corresponding to the gate. The corresponding gate mark circuit of the fan-in gate mark circuit 3 to which the event is sent changes the value only at this time if it has not been inverted. If the gate mark circuit on the fan-in gate mark circuit to which the event was sent had previously changed the value, no further change occurs. Whether or not the signal value has changed before can be known by identifying whether or not the signal has an initial value.

In the example of FIG. 10, assuming that the signals of the gates on the fan-in gate mark circuit are all initial values, the gates on which the signal values on the inverse circuit 2 have changed and the corresponding gate mark circuits on the gate mark circuit are changed. The gates whose signal values have changed are indicated by diagonal lines. That is, the gate mark circuit O1f
1, G4f1, G2f2.

In the example of FIG. 10, the single path is detected, but it is also possible to detect the multipath.
FIG. 11 shows B.C. of FIG. The state of the reverse circuit and the fan-in gate mark circuit when the input pattern is given is shown.

The example of FIG. 11 corresponds to A. The operation of the fan-in gate mark circuit is made easier to understand by assuming that after the input vector of is given. That is, as the input pattern, B. As shown in {0p, 1s, 0p}
, The path from the input in1 to the output out1 and the path from the input in3 to the output out1 are signal values {0
p, 1p}, and the corresponding gates on the inverse circuit invert the values. The gates on the inverse circuit for inverting the values are the gates O1, G4, G2, G3, I1 and I3 that are shaded on the inverse circuit 2 in FIG.

The gate whose signal value has changed on the reverse circuit sends an event to the gate on the corresponding fan-in gate mark circuit of FIG. 11, but the fan whose signal value has changed in the example of FIG. 10 above. The gate of the in-gate mark circuit does not change its value this time (in FIG. 11, O1f1, G4f1, shaded on the fan-in gate mark circuit).
Each gate of G2f2). Among the gates to which the event is sent, only the gates that have not changed the signal value so far are changed in value. This circuit is each gate of G3f2 and G4f2 surrounded by a bold frame on the fan-in gate mark circuit in FIG.

[0061]

According to the present invention, a path consisting of a set of gates having a certain signal value can be directly detected without searching the gate signal value on the path. Also,
At the same time, the gate that first generates the specified signal value can be detected from the gates on the path, and the performance of the logic circuit simulation device and the delay fault inspection can be improved.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an explanatory diagram of patterns of signal values.

FIG. 3 is a configuration diagram of an embodiment.

FIG. 4 is a diagram showing a truth table of a logic gate.

FIG. 5 is a diagram showing a truth table of gates of an inverse circuit.

FIG. 6 is a diagram showing a truth value of a gate on a fan-in gate mark circuit.

FIG. 7 is a diagram showing an operation flow of an inverse circuit.

FIG. 8 is a diagram showing an operation flow of a fan-in gate mark circuit.

FIG. 9 is a diagram showing a state of each gate when an input pattern is given to a circuit under test.

FIG. 10A. FIG. 3 is a diagram showing states of an inverse circuit and a fan-in gate mark circuit when the input pattern of FIG.

FIG. 11B. FIG. 3 is a diagram showing states of an inverse circuit and a fan-in gate mark circuit when the input pattern of FIG.

FIG. 12 is an explanatory diagram of a logic circuit.

[Explanation of symbols]

 1 circuit under test 10 input gate (i [n]) 11 logic gate (g [n]) 12 output gate (o [n]) 2 reverse circuit 20 logic gate (I [n]) 21 logic gate (G [n ] 22 logic gate (O [n]) 23 clock source 3 fan-in gate mark circuit 30 gate mark circuit

 ─────────────────────────────────────────────────── --Continued front page (72) Inventor Keiji Kuma 1-6-4 Osaki, Shinagawa-ku, Tokyo Inside Fujitsu Social Science Laboratory, Inc.

Claims (5)

[Claims] 1. An input gate (10) to which an input signal is supplied,
In the delay test method of the circuit under test (1), which comprises an output gate (12) for generating an output signal and a logic gate (11) arranged between the input gate and the output gate to perform a logical operation, Logic gates (20 to 2) are provided corresponding to the input gates, logic gates and output gates on the circuit, and input at least the output signals of the respective gates.
An inverse circuit (2) that consists of 2) and propagates an event in the opposite direction to the signal of the circuit under test is provided, and one of the signal values having multiple waveforms as an input signal is input to the circuit under test. When a predetermined signal value is generated from the output gate when the combination of the signal values is input to the plurality of input gates by changing the combination of the signal values, in the reverse circuit, from the logic gate corresponding to the output gate of the circuit under test. When an event occurs and the preceding logic gate is driven, the preceding logic gate generates an event when a predetermined signal value is generated from the corresponding logic gate of the circuit under test, and sequentially drives the preceding logic gate. , A delay inspection method of a logic circuit characterized by identifying a path through which a signal specified by each logic gate of an inverse circuit passes. 2. The logic gate of claim 1, wherein each logic gate of the reverse circuit inverts its own output signal only when the output signal of the corresponding gate on the circuit under test is a designated waveform signal, A delay inspection method for a logic circuit, characterized in that an event is generated and a logic gate in a preceding stage is driven by the inverted signal. 3. The delay inspection method for a logic circuit according to claim 2, wherein the logic gate corresponding to the output gate of the circuit under test on the inverse circuit is driven by a clock signal to perform a logical operation. 4. The fan-in gate mark circuit according to claim 1, further comprising a gate mark circuit having a total fan-in number of logic gates and output gates of the circuit to be inspected, wherein each gate mark circuit is to be inspected. A means for holding the occurrence of the designated waveform signal by being driven by the generation of the designated waveform signal from the corresponding logic gate on the inverse circuit, with the input of the gate on the circuit and the output of itself as fan-in. A delay inspection method for a logic circuit characterized by being provided. 5. The delay inspection method for a logic circuit according to claim 4, wherein each of the gate mark circuits includes means for storing and holding a type of a waveform signal as well as generation of a designated waveform signal.