JPH0772204A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the number of output data signals wherein a signal level is concurrently changed in an operation test and decrease the malfunction and errors of judgement of an semiconductor integrated circuit intended for the operation test. CONSTITUTION:Data signals output from an LSI internal circuit 2 is given to output buffers 31, 32, 33 in LSI 1. The output buffers 31, 32, 33 output data signals in response to the given data signals respectively. Test control circuits 310, 320, 330 are provided in response to the output buffers 31, 32, 33 respectively. At the time of an operation test, a reset signal (tr) and a test clock signal (tc) are input from a test reset input pin 91 and a test clock input pin 92. After the test control circuits 310-330 have made the output state of the output buffers 31-33 high inpedance on the basis of these signals once, the control wherein the output buffers 31-33 make a through state successively is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which an operation test is performed based on the determination of an external output signal in response to an external input signal.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional semiconductor integrated circuit (hereinafter referred to as L
It is a schematic circuit diagram showing an example of a basic configuration of (SI). Referring to FIG. 8, LSI 102 includes an LSI internal circuit 2 and output buffers 31, 32, 33. LS
The I102 is provided with a power supply pin 4, a clock input pin 5, data input pins 6, 6, 6, output pins 71, 72, 73, and a ground pin 8.

Power supply pin 4 receives a power supply potential, and ground pin 8 receives a ground potential. Clock input pin 5 receives a clock signal which is an external clock signal. Each of the data input pins 6, 6, 6 receives an input data signal which is an external input data signal. Output pins 71, 72, 73
An output data signal, which is an external output data signal, is output from each of the above to the outside of the LSI 102.

An LSI internal circuit 2 which is a data processing means
Receives a power supply potential from power supply pin 4 and a ground potential from ground pin 8. Further, the LSI internal circuit 2 receives a clock signal from the clock input pin 5 and an input data signal from each of the data input pins 6, 6 and 6.

In operation, the LSI internal circuit 2 takes in an input data signal each time a clock signal is input. Then, the LSI internal circuit 2 performs a predetermined signal processing and gives a data signal as the processing result to each of the output buffers 31, 32, 33.

Each of output buffers 31, 32 and 33 operates by receiving a power supply potential from power supply pin 4 and a ground potential from ground pin 8. In the operation, each of the output buffers 31, 32 and 33 amplifies the current drive capability of the applied data signal and supplies the resulting output data signal to the output pins 71, 72 and 73.

As a result, the output data signal from the output buffer 31 is output to the outside via the output pin 71.
The output data signal from the output pin 32 is output to the outside via the output pin 72. The output data signal from the output buffer 33 is output to the outside via the output pin 73.

In such an LSI 102, the LS
An operation test using the I tester is performed. In the operation test, a clock signal for testing is input from the clock input pin 4, an input data signal for testing is input from the data input pins 6, 6 and 6, and in response to these input signals. Output pins 71, 72,
The LSI tester determines whether or not the output data signals output from the respective 73 are normal.

The operation test will be described in detail below. First, the environment during the operation test will be described.
The operation test is performed by a device in which an LSI tester and an LSI to be tested are connected via a test board.
FIG. 9 is a schematic circuit diagram of an apparatus for performing a test using an LSI tester.

Referring to FIG. 9, the LSI tester includes a power supply unit 15, a ground unit 16 and a comparator 170. The power supply unit 15 generates a power supply potential for testing. The ground unit 16 generates a test ground potential. The comparator 170 is an LSI
1 is a circuit for determining whether or not the output data signal output from 1 is normal. In FIG.
The capacitances 17, 17, 17 formed by 0 are shown.

The test board 11 includes a power supply wiring 12, a ground wiring 13, and signal wirings 14, 14, 14.
One end of the power supply wiring 12 is connected to the power supply unit 15. One end of the ground wiring 13 is the ground unit 16
Connected to. One end of each of the signal wirings 14, 14, 14 is connected to each of the capacitances 17, 17, 17.

The LSI 102 to be tested is mounted on the test board 11. In this case, the power supply pin 4 is connected to the power supply wiring 12, and the ground pin 8 is connected to the ground wiring 13
And the output pins 71, 72, 73 are connected to the signal wiring 1
4, 14, 14 are connected.

With this configuration, the LS to be tested is
In I102, the power supply pin 41 receives the power supply potential from the power supply unit 15 via the power supply wiring 12, and the ground pin 8 receives the ground potential from the ground unit 16 via the ground wiring 13. Then, in response to the clock signal input from the clock input pin 5 and the input data signal input from the data input pins 6, 6, 6, the output data signal is output from the output pins 71, 72, 73 to the signal wiring 14, 1
It is supplied to the electrostatic capacitances 17, 17, 17 via 4, 14.

Next, the LSI 102 during the operation test
The operation of will be described. FIG. 10 shows L at the time of operation test.
6 is a timing chart of a clock signal and an output data signal in SI.

In FIG. 10, the clock signal C input from the clock input pin 4 and the output pins 71, 72, 7 are shown.
3 output data signal, that is, the output data signal O output from the output buffers 31, 32, 33.
71, O72, O73 are shown.

Referring to FIG. 10, one cycle of clock signal C is test cycles 0, 1, 2, ... (n-1), n,
It is represented as one cycle of (n + 1), ....

In the operation test, output data signals O71, O72, O are output in a predetermined test cycle n.
The respective signal levels of 73 are simultaneously changed from the logic level "0" to the logic level "1".

In this case, the plurality of data signals output from the LSI internal circuit 2 simultaneously change from the logic level "0" to the logic level "1", whereby the output buffer 3
The output data signals O71, O72, and O73 output from 1, 32, and 33 change from the logic level "0" to the logic level "1".

However, the output buffer 31,
When the logical levels of the output data signals output from 32 and 33 simultaneously change from "0" to "1", the voltage at the power supply pin 4 drops.
The problem will be described in detail below.

FIG. 11 shows the output buffer 31 when the output data signal of the LSI 102 is at the logic level "0".
It is a schematic diagram which modeled the state of 32,33. Figure 11
With reference to, the output buffer 3, which is representative of one of the output buffers 31, 32, and 33, is a kind of switching element. Therefore, the output buffer 3 can be represented as a changeover switch having the movable contact 3a and the two fixed contacts 3b and 3c.

The first fixed contact 3b of the output buffer 3 is
It is connected to the power supply unit 15 via the power supply pin 4 and the resistor R12. The resistance R12 is a resistance component formed by the power supply wiring 12. The second fixed contact 3c is connected to the ground unit 16. The movable contact 3 a is connected to the electrostatic capacitance 17.

In the model having such a structure, when the logic level of the output buffer 3 is "0", the movable contact 3a is connected to the second fixed contact 3c. in this case,
No current flows from the power supply unit 15 toward the capacitance 17. Therefore, the voltage V1 at the power supply pin 4 is equal to the voltage V2 at the power supply unit 15. That is, the voltage generated by the power supply unit 15 is directly applied to the power supply pin 4.

On the other hand, when the output data signal of the LSI 102 is at the logic level "1", the state of the output buffer 3 is as follows. FIG. 12 shows the output buffer 3 when the output data signal of the LSI 102 is at the logic level "1".
It is a schematic diagram which modeled the state of 1, 32, 33. 12, the same parts as those in FIG. 11 are designated by the same reference numerals, and the description thereof will be omitted.

Referring to FIG. 12, when the logic level of output buffer 3 is "1", movable contact 3a is connected to first fixed contact 3b. In this case, the power supply unit 15
The charging current I (t) flows from the electrostatic capacity 17 to the electrostatic capacity 17.

This charging current I (t) is the capacitance 17
However, as shown in FIG. 11, the output buffer 3 is connected to the ground unit 16 for discharging, and the electrostatic capacitance voltage is 0 V. This is because the voltage is increased by being connected to the unit 15.

As described above, when the charging current I (t) flows, the current flows through the resistor R12.
There is a voltage difference between the voltage V2 at the voltage V2 and the voltage V1 at the power pin 4. The voltage difference (V2-V1) is expressed by the following equation (1), where R is the resistance value of the resistor R12.

V2−V1 = R · I (t) (1) That is, when the logic level of the output data signal output from the output buffer 3 changes from “0” to “1”, the voltage V1 at the power supply pin 4 Is lower than the voltage V2 at the power supply unit 15. Such a decrease in the voltage V1 increases as the number of output data signals whose logic level changes from "0" to "1" at the same time increases. This is because multiple output buffers operate simultaneously.

[0028]

As described above, the voltage V1
Is lower than the voltage V2, the LSI 10 to be tested is
The electrical characteristics of the LSI 102 under test change, such as an increase in the delay time of the output signal with respect to the input signal in 2.

Such a change in the electrical characteristics of the LSI 102 to be tested causes a malfunction of the LSI in the operation test and causes an error in the pass / fail judgment of the operation test of the LSI.

Then, the decrease of the voltage V1 of the power supply pin 4 is
It increases as the number of output data signals whose logic levels change simultaneously increases, so the LSI to be tested
There is a problem that the malfunction and the error in the pass / fail judgment are more likely to occur as the number of output data signals whose logic levels change simultaneously increases.

The present invention has been made to solve such a problem, and in the operation test, the number of output data signals whose logic levels change at the same time is reduced, and the malfunction of the test object and the error of the pass / fail judgment are made. It is an object of the present invention to provide a semiconductor integrated circuit capable of reducing the power consumption.

[0032]

The present invention is a semiconductor integrated circuit in which an operation test is performed based on the determination of an external output signal in response to an external input signal, which includes a power supply node, a clock input node, a data input node, and a plurality of nodes. Output node, data processing means, output buffer means including an output buffer, and test control means.

The power supply node receives a power supply voltage. An external clock signal is input to the clock input node. An external input data signal is input to the data input node. External output data signals are output to the plurality of output nodes.

The data processing means generates a plurality of data signals in response to the external clock signal and the input data signal.

A plurality of output buffer means are provided between the data processing means and each of the plurality of output nodes, operate by receiving the power supply voltage, receive each of the plurality of data signals, and receive the data. An external output data signal responsive to the signal is provided to each of the plurality of output nodes.

The three-state output buffer included in each of the output buffer means is in one of the first state for outputting the external output data signal in response to the received data signal and the second state of high impedance. Controlled.

The test control means controls the operation state of each of the plurality of output buffer means to switch from the second state to the first state in the operation test.

[0038]

According to the present invention, when an operation test is performed, the test control means sequentially controls the respective operation states of the output buffer means from the second state to the first state, whereby the received data signal is received. The number of output buffer means for simultaneously outputting the external output data signal in response to is reduced.

Therefore, in the operation test, the number of external output data signals whose signal levels are simultaneously changed is reduced.

Therefore, in the operation test, the change in the voltage at the power supply node due to the change in the signal level of the external output data signal is suppressed.

[0041]

Embodiments of the present invention will now be described in detail with reference to the drawings. First Embodiment FIG. 1 is a schematic circuit diagram of an LSI according to the first embodiment. Referring to FIG. 1, the LSI 102 of FIG.
The difference from I102 is that the test control circuits 310, 32
0, 330 are provided, and a test reset t
Test reset input pin 91 that receives the r signal from the outside
Are provided and the test clock signal tc
That is, a test clock input pin 92 for receiving the signal from the outside is provided.

The test control circuit 310 includes a D flip-flop 311 and an exclusive NOR circuit 312. The test control circuit 320 includes a D flip-flop 321 and an exclusive NOR circuit 322. The test control circuit 330 includes the D flip-flop 3
31 and an exclusive NOR circuit 332.

D flip-flops 311, 321, 33
1 receives the test clock signal tc from the test clock input pin 92 to the clock input terminal T,
The reset input terminal R receives the test reset signal tr from the test reset input pin 91.

D flip-flop 311 receives the power supply potential at its data input terminal D. D flip-flop 3
21 is a D flip-flop 3 at its data input terminal D.
An output signal from the output terminal O of 11 is received. The D flip-flop 331 receives the output signal from the output terminal O of the D flip-flop 321 at its data input terminal D.

Exclusive NOR circuit circuit 312,
Each of 322 and 333 has a test reset signal tr from the test reset input pin 91 to one input terminal.
Receive. The exclusive NOR circuit 312 is
The other input terminal receives the output signal from the output terminal O of the D flip-flop 311. The exclusive NOR circuit 322 has a D flip-flop 32 at its other input terminal.
1 receives the output signal from the output terminal O. The exclusive NOR circuit 332 receives the output signal from the output terminal O of the D flip-flop 332 at the other input terminal.

The output signal of the exclusive NOR circuit 312 is applied to the output buffer 31. The output signal of the exclusive NOR circuit 322 is output to the output buffer 32.
Given to. The output signal of the exclusive NOR circuit 332 is given to the output buffer 33.

Next, the structure of each of the output buffers 31, 32 and 33 will be described in detail. Output buffer 31,
Since the configurations of 32 and 33 are all the same, the configuration of the output buffer 31 will be described as a representative example. FIG. 2 is a circuit diagram showing a detailed configuration of the output buffer 31.

Referring to FIG. 2, output buffer 31 has P
It includes MOS transistors T1 and T3 and NMOS transistors T2, T4 and T5. This output buffer 31 is
It is a 3-state output buffer. Transistors T1 and T2 are connected in series between power supply node N1 receiving the power supply potential and ground node N2 receiving the ground potential. A transistor T is provided between the power supply node N1 and the ground node N2.
3 and T4 are also connected in series.

The node between transistors T1 and T2 is connected to the respective gates of transistors T3 and T4. Transistor T5 is connected between the node between transistors T3 and T4 and data output node N4. Each of the transistors T1 and T2 is
The data signal output from the LSI internal circuit 2 is received from the data input node N3. Transistor T5 receives the output signal of exclusive NOR circuit 322 from control signal input node N5.

In the output buffer 31 having such a configuration,
A data signal having the same logic level as that of the data signal input from the data input node N3 is output from the data output node N4. The data signal output from the data output node N4 has a higher current drive capability than the data signal input from the data input node N3.

In this output buffer 31, the transistor T5 turns on when the logic level of the output signal of the exclusive NOR circuit 322 input from the control signal input node N5 is "1", and the through state (input data signal The data signal in response to is output). On the other hand, when the logic level of the output signal of the exclusive NOR circuit 322 input from the control signal input node N5 is "0", the transistor T5 is turned off and the high impedance state is set.

As described above, in the LSI 1, each of the output buffers 31, 32 and 33 is in the through state when the logical level of the output signal of each of the exclusive NOR circuits 312, 322 and 332 becomes "1". Become. On the other hand, when the logic level of the output signal becomes “0”, each of the output buffers 31, 32, 33 becomes
High impedance state.

Next, the operation of the LSI 1 during the operation test will be described. The operation test of the LSI 1 is performed by the device shown in FIG.

FIG. 3 is a timing chart of input signals and output signals at the time of testing the LSI 1 according to the first embodiment. In FIG. 3, a clock signal C, a test clock signal tc, a test reset signal tr, and output data signals O71, O72, O73 are shown.

Referring to FIG. 3, one cycle of clock signal C is test cycle 0, 1, 2, ... (n-1), P1,
It is represented as one cycle of n, S1, S2, S3, (n + 1) ... In each of the test cycles T1, S1, S2, and S3 of this test cycle, the pulse of the clock signal C is not input.

Test cycle 0 to test cycle (n
During the period up to -1), the test clock signal t
The logic levels of c and the test reset signal tr are held at "0". As a result, each of the D flip-flops 311, 321, 331 is reset. Therefore, the D flip-flops 311 and 3
The logical level of each output signal of 21, 331 becomes "0".

As a result, the exclusive NOR circuit 3
The logic level of each output signal of 12, 322 and 332 becomes "1". Therefore, the output buffers 31, 3
Each of 2 and 33 is in a through state. As a result, L
The logic levels of the data signals supplied from the SI internal circuit 2 to the output buffers 31, 32 and 33 appear on the output pins 71, 72 and 73 as they are.

Then, in the test cycle P1, the logic level of the test reset signal tr is "0" to "1".
Changes to. As a result, the logical level of each output signal of the exclusive NOR circuits 312, 322, 332 changes from "0" to "1". As a result, the output signals of the output buffers 31, 32 and 33 are in a high impedance state (hatched portion in FIG. 3).

Then, in the test cycle n, one pulse of the clock signal C is input. This allows the LSI
The logic level of the data signal supplied from the internal circuit 2 to each of the output buffers 31, 32, 33 changes from "0" to "1".

In this case, the output buffers 31, 32, 33
The output of each is already in a high impedance state. Therefore, even if the logic level of the data signal supplied from the LSI internal circuit 2 to the output buffers 31, 32, 33 changes, the logic level of each output signal of the output buffers 31, 32, 33 does not change.

During the test cycles S1 to S3, the clock pulse of the test clock signal tc is input. In this case, the D flip-flop 311
The data input terminal D of is always receiving the signal of the logic level "1". Then, the D flip-flops 311 and 32
Since 1 and 331 form a shift register, the logical level of each output signal of the D flip-flops 311, 321, and 331 is sequentially "1" every time one clock pulse of the test clock signal tc is input. Becomes

When the logical level of the output signal of the D flip-flop 311 becomes "1", the logical level of the output signal of the exclusive NOR circuit 312 becomes "1". As a result, the output buffer 31 goes into the through state.

When the logical level of the output signal of the D flip-flop 321 becomes "1", the logical level of the output signal of the exclusive NOR circuit 322 becomes "1". As a result, the output buffer 32 goes into the through state.

When the logical level of the output signal of the D flip-flop 331 becomes "1", the logical level of the output signal of the exclusive NOR circuit 332 becomes "1". As a result, the output buffer 33 goes into the through state.

That is, each time the clock pulse of the test clock signal tc is input, the output buffers 31 and 3 are output.
2, 33 are sequentially in the through state.

Therefore, in the LSI 1, the LSI internal circuit 2 to the output buffers 31,
The change in the logic level of each output data signal of the output buffers 31, 32, 33 in response to the change in the logic level of the data signal applied to 32, 33 is divided into three test cycles S1, S2, S3. Occurs.

Therefore, the number of output data signals whose logic levels change simultaneously during the operation test is reduced. That is, the number of output buffers that simultaneously output the output data signal during the operation test is reduced. As a result, the charging current I (t) as shown in FIG. 12 becomes smaller than in the conventional case. As a result, the decrease in the voltage V1 of the power supply pin 4 due to the charging current I (t) at the time of the operation test is suppressed as compared with the conventional case.

In the LSI 1, the test cycle S3
At, the logic level of the test reset signal tr is changed from "1" to "0". The clock signal is supplied after the test cycle (n + 1). As a result, in the test cycle (n + 1) and later,
Similar to the period from the test cycle 0 to (n-1), the normal test operation state in which the output states of the output buffers 31, 32 and 33 are not controlled is restored. Second Example Next, a second example will be described. L shown in FIG.
SI1 is provided with test control circuits 310, 320, and 330 corresponding to the output buffers 31, 32, and 33, and control is performed for each output buffer.
However, as long as the malfunction of the LSI 1 does not occur,
A plurality of output buffers 31, 32, 33 may be collectively controlled. In the second embodiment, the output buffer 3
An example of collectively controlling a plurality of 1, 32, and 33 will be described.

FIG. 4 is a schematic circuit diagram of an LSI according to the second embodiment. The LSI 100 of FIG. 4 is different from the LSI 1 of FIG. 1 in that the test control circuit 320 is not provided.

With reference to FIG. 4, description will be given of a part of the configuration of LSI 100 which is different from LSI 1 in FIG. D
The flip-flop 331 is the D flip-flop 311.
The data input terminal D receives the output signal from the output terminal O. The output signal of the exclusive NOR circuit 312 is
It is given to the output buffer 31 and the output buffer 3
Also given to 2.

Next, the operation of the LSI 100 of FIG. 4 during the operation test will be described. FIG. 5 shows L according to the second embodiment.
6 is a timing chart of an input signal and an output signal during an SI100 operation test.

Referring to FIG. 5, the timing chart of FIG. 5 differs from the timing chart of FIG. 3 in that there is no test cycle S3.

That is, since the LSI 100 has two test control circuits, the clock pulse of the test clock signal tc required at the time of the operation test can be two pulses.

Then, by inputting the test clock signal tc in the test cycle S1, exclusive
The logic level of the signal supplied from the NOR circuit 312 to the output buffers 31 and 32 changes from "0" to "1". As a result, in the test cycle S1, the output buffer 3
Both 1 and 32 are in the through state.

In the subsequent test cycle S2, the logic level of the signal supplied from the exclusive NOR circuit 332 to the output buffer 33 changes from "0" to "1" by the input of the test clock signal tc.
As a result, in the test cycle S2, the output buffer 33 becomes the through state.

Therefore, the logic level of the output data signal at the time of the operation test changes in two periods of the test cycles S1 and S2. If two output data signals change at the same time, the LSI 1
The decrease in the voltage V1 of the power supply pin 4 of 00 is within the range in which the malfunction of the LSI 100 does not occur.

In such an LSI 100, the number of output data signals whose logic levels change simultaneously during an operation test is reduced as compared with the conventional one. This makes power pin 4
Of the voltage V1 is suppressed more than before. In addition, the number of test control circuits is smaller than that of the LSI 1 shown in FIG.
It can be reduced more than the LSI1. Third Example Next, a third example will be described. L shown in FIG.
SI1 and the LSI 100 shown in FIG. 4 require two signals, a test clock signal tc and a test reset signal tr, as test input signals.
An example in which the test input signal is one signal is shown in the third embodiment.

FIG. 6 is a schematic circuit diagram of an LSI according to the third embodiment. The LSI 101 of FIG. 6 differs from the LSI 1 of FIG. 1 in that AND circuits 34, 35, 36, 37 and an inverter 38 are provided and the test clock input pin 92 is not provided.

Referring to FIG. 6, the configuration of LSI 101 will be described by focusing on differences from LSI 1 of FIG. A
The ND gate 34 receives the clock signal C input from the clock input pin 5 and the inverted signal of the test reset signal tr provided from the test reset input pin 91 via the inverter 38. AND circuit 34 gives an output signal to LSI internal circuit 2 in response to the received signal.

Each of the AND circuits 35, 36 and 37 receives the clock signal C input from the clock input pin 5.
And a test reset signal tr input from the test reset input pin 91.

The AND circuit 35 gives an output signal in response to the received signal to the clock input terminal T of the D flip-flop 311. The AND circuit 36 gives an output signal in response to the received signal to the clock input terminal T of the D flip-flop 321. The AND circuit 37 gives an output signal in response to the received signal to the clock input terminal T of the D flip-flop 331.

In addition, the test reset signal tr input from the test reset input pin 91 is the LS of FIG.
D flip-flops 311, 321, 33 similar to I1
1 to each of the reset input terminals R and exclusive NOR circuits 312, 322, 332
Is given to each input terminal of.

Next, the operation of the LSI 101 of FIG. 6 during the operation test will be described. FIG. 7 shows L according to the third embodiment.
7 is a timing chart of each signal during an SI 101 operation test.

In FIG. 7, the clock signal C, AND
Output signal O34 of circuit 34, AND circuits 35, 36, 3
7 output signals O35, O36, O37, a test reset signal tr, and output data signals O71, O72, O7.
3 are shown respectively.

The test cycle is 0, 1, 2, ..., (n
-2), (n-1), n, S1, S2, S3, (n +
1) and (n + 2). One cycle of this test cycle corresponds to one cycle of the clock signal C. In this test cycle, the clock pulse of the clock signal C is always input.

During the period from test cycle 0 to (n-1), the logic level of the test reset signal tr is held at "0". As a result, the AND circuit 34 receives the clock signal C from the clock input pin 5 and the inverted signal (logical level “1”) of the test reset signal tr from the test reset input terminal 91 via the inverter 38. To be done. Therefore, the AND circuit 34
The output signal O34 of is a clock signal having the same cycle as the clock signal C. This output signal O34 is given to the LSI internal circuit 2.

Further, this test cycle 0 to (n-1)
During the period, the logical level of the test reset signal tr is held at "0", and therefore the AND circuits 35, 3
Output signals O35, O36 and O37 of 6 and 37, respectively.
The respective logic levels of are 0. Therefore, the same signal as the clock signal C input from the clock input pin 5 is not supplied to the D flip-flops 311, 321, 331.

Further, during the period from test cycle 0 to (n-1), since the logic level of the test reset signal tr is held at "0", each of the D flip-flops 311, 321, 331 is reset. It becomes a state. Therefore, the exclusive NOR circuits 312, 3
The logical level of the output signal given from 22, 332 to the output buffers 31, 32, 33 becomes "1". Therefore, in the test cycle 0 to (n-1),
Each of the output buffers 31, 32, 33 is in the through state.

Then, in the test cycle n, the logic level of the data signal supplied from the LSI internal circuit 2 to each of the output buffers 31, 32, 33 due to the rising of the clock signal C changes from "0" to "1". Change.
At that time, those data signals are output to the output buffers 31 and 3.
2 and 33 before being output to the test reset signal tr
The logic level of is changed from "0" to "1".

As a result, the logical level of each output signal of the exclusive NOR circuits 312, 322, 332 changes from "1" to "0". Therefore, in the test cycle n, the output signals O71, O72, O73 of the output buffers 31, 32, 33 are in the high impedance state (hatched portion in FIG. 7).

Further, when the logic level of the test reset signal changes from "0" to "1", the AND circuit 34
The output signal O34 has a logic level of "0". As a result, L from the clock input pin 5 via the AND circuit 34
The clock signal supplied to the SI internal circuit 2 is cut off and L
The operation of the SI internal circuit 2 stops.

At the same time, AND circuits 35, 36, 3
A clock signal is supplied from 7 to the D flip-flops 311, 321, 331. Therefore, by the action of the D flip-flops 311, 321, 331 forming the shift register, in the test cycles S1, S2, S3, as in the LSI 1 of FIG.
33 sequentially becomes the through state.

Therefore, in the LSI 101, the LSI internal circuit 2 to the output buffer 3 in the test cycle n are
The change in the logic level of the output data signal of each of the output buffers 31, 32, 33 in response to the change in the logic level of the data signal given to 1, 32, 33 is caused by three test cycles S1, S2, S3. It occurs in two parts.

Therefore, the number of output data signals whose logic levels change simultaneously during the operation test is reduced. That is, the number of output buffers that simultaneously output the output data signal during the operation test is reduced. As a result, the charging current I (t) as shown in FIG. 12 becomes smaller than in the conventional case. As a result, the power supply pin 4 caused by the charging current I (t)
Of the voltage V1 is suppressed more than before.

Further, in the LSI 101, since the test input signal is one signal, the number of pins dedicated to the test is the LSI 1 shown in FIG. 1 and FIG.
And the LSI 100 can be reduced.

In the LSI 101, the logic level of the test reset signal tr is changed from "1" to "0" in the test cycle S3. As a result, after the test cycle (n + 1), the test cycles 0 to (n
Similar to the period of -1), the normal test operation state in which the output states of the output buffers 31, 32 and 33 are not controlled is restored.

[0097]

According to the present invention, the output buffer means for outputting the external output data signal in response to the received data signal during the operation test by controlling the respective operating states of the output buffer means by the test control means. Can be reduced. As a result, the number of external output data signals whose signal levels change simultaneously during the operation test can be reduced. Therefore, the change in the voltage at the power supply node due to the change in the level of the external output data signal can be suppressed. As a result, a malfunction of the semiconductor integrated circuit in the operation test can be prevented, and an error in the operation test can be prevented.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram of an LSI according to a first embodiment.

FIG. 2 is a circuit diagram showing a detailed configuration of an output buffer.

FIG. 3 is a timing chart of an input signal and an output signal during an operation test of the LSI according to the first embodiment.

FIG. 4 is a schematic circuit diagram of an LSI according to a second embodiment.

FIG. 5 is a timing chart of an input signal and an output signal during an operation test of the LSI according to the second embodiment.

FIG. 6 is a schematic circuit diagram of an LSI according to a third embodiment.

FIG. 7 is a timing chart of each signal during an operation test of an LSI according to the third embodiment.

FIG. 8 is a schematic circuit diagram showing a basic configuration of a conventional LSI.

FIG. 9 is a schematic circuit diagram of an apparatus for performing an operation test using an LSI tester.

FIG. 10 is a timing chart of a clock signal and an output data signal during an operation test.

FIG. 11: The output data signal of the LSI is a logical level “0”
It is a schematic diagram modeling the state of the output buffer in the case of.

FIG. 12: The output data signal of the LSI is a logical level “1”
It is a schematic diagram modeling the state of the output buffer in the case of.

[Explanation of symbols]

 1, 100, 101 LSI 2 LSI internal circuit 4 power supply pin 5 clock input pin 6 data input pin 31, 32, 33 output buffer 71, 72, 73 output pin 310, 320, 330 test control circuit

Claims (1)

[Claims] 1. A semiconductor integrated circuit in which an operation test is performed based on determination of an external output signal in response to an external input signal, the power supply node receiving a power supply voltage, a clock input node to which an external clock signal is input, A data input node to which an external input data signal is input, a plurality of output nodes to which an external output data signal is output, and a data processing for generating a plurality of data signals in response to the external clock signal and the external input data signal. An external unit that is provided between the data processing unit and each of the plurality of output nodes, operates by receiving the power supply voltage, receives each of the plurality of data signals, and responds to each of the data signals. A plurality of output buffer means for giving an output signal to each of the plurality of output nodes; Each include an output buffer controlled to be in an operating state of either a first state or a second state of high impedance for outputting an external output data signal in response to the received data signal. A semiconductor integrated circuit, comprising: a control unit for testing, which controls to sequentially switch the operating states of a plurality of output buffer units from the second state to the first state.