JPH0770605B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The impurity concentration of a well of opposite conductivity type in which a transistor is formed is set to be higher than usual to increase latch-up resistance, and an upper layer portion of the well is entirely covered in the well. The included low-concentration region is formed by counter-doping one conductivity type impurity, and the source and drain are formed therein to reduce the junction capacitance of the source and drain, and the channel formation region is ion-implanted with the opposite conductivity type impurity. A method for manufacturing a CMOS semiconductor device in which a threshold voltage is adjusted by injection.

[Industrial application field]

The present invention relates to an improvement in a method for manufacturing a CMOS semiconductor device, and more particularly to a method for manufacturing a CMOS semiconductor device for improving latch-up resistance and speeding up.

In a highly integrated semiconductor IC such as an LSI, the operating speed tends to decrease due to an increase in parasitic capacitance and wiring resistance, etc., as the integration becomes higher, and there is an increasing demand for higher speed.

On the other hand, in CMOS ICs, the nMOS that constitutes the inverter circuit
There is a problem that the thyristor, which is parasitic between the transistor and the pMOS transistor via the inside of the substrate, is turned on by the large current noise flowing from the external circuit to the inverter circuit, causing the element to be destroyed by the latch-up phenomenon. There is a demand for a CMOS semiconductor device that has high latch-up resistance and requires a high operating speed.

[Conventional technology]

FIG. 4 is a schematic side sectional view including the equivalent circuit showing the configuration of the CMOS inverter, in which n _sub is an n ⁻ type semiconductor substrate and p _well is p
^- type well, p-Tr is pMOS transistor, n-Tr is nMOS
Transistor, S _p , D _p , G _p are source and drain of p-Tr
Gate, S _n , D _n , and G _n are n-Tr source, drain, and gate, + V _DD is a power supply terminal, V _ss is a ground terminal, and OUT is an output terminal.

Many such inverters are formed in a CMOS circuit. In this case, S _p , n _sub, and p _{well form a} parasitic pnp transistor (pnpTr), and S _n , p _well, and n _{sub form a} parasitic npn transistor (npnTr ) Is formed, and parasitic resistances R ₁ , R ₂ , and R ₃ exist between the terminals.

As is clear from the power supply path shown in the figure, the parasitic element constitutes a thyristor, and an abnormal phenomenon called latch-up is caused by this thyristor operation.

That is, for example, a noise current flows from D _n connected to an external circuit, and when this current is large, the npnTr is in the [ON] state and a current flows from the + V _DD terminal to the V _ss terminal via R ₂ and R _3. Flowing. Here, if the voltage across R ₂ becomes higher than the base voltage of pnpTr, pnpTr will be in the [ON] state.

Then, at this time, a current flows through the base of the npnTr through the pnpTr to turn the pnpTr into the [ON] state, and as a result, the npnTr and pnpTr
Positive feedback is applied to the loop consisting of, and the thyristor enters a resistance state.

Therefore, once a large noise current is injected, a steady large current flows between the power terminals even if this noise current disappears.
If the power is left uninterrupted, the wiring may be broken or the device may be destroyed.

Such a phenomenon is referred to as latch-up, which is disadvantageous as the base resistance of npnTr, that is, the value of R ₁ increases.

Therefore, as a means for forming a CMOS semiconductor device having a high latch-up resistance, the well concentration is increased and counter-dose is performed to selectively lower the carrier concentration in the channel region of the transistor in the well to control its threshold voltage. Manufacturing methods have been proposed.

FIG. 5 is a schematic side sectional view of a CMOS semiconductor device formed by the above conventional method.

In the figure, 1 is an n ^- type silicon substrate, 2 is a p-type well, 3 is a threshold adjusting p ^- type counter dose region, 4 is a gate SiO ₂ film, 5 is a gate electrode, 6 is an n ⁺ type source region, 7 is
n ⁺ type drain region, 8 p ⁺ type source region, 7 p ⁺ type drain region, 10 n ⁺ type substrate contact region, 11 p ⁺ type well contact region, 12 field SiO ₂ film, 13 n-type channel stopper, 14 is p-type channel stopper, n-Tr
Is an nMOS transistor, and p-Tr is a pMOS transistor.

[Problems to be solved by the invention]

However, in such a CMOS semiconductor device manufactured by the conventional manufacturing method, the carrier concentration of the p-type well 2 that forms a junction with the source / drain regions 6 and 7 of the nMOS transistor n-Tr can be increased to nearly double that of the conventional method. Therefore, there is a problem that the junction capacitance increases and the operating speed of the nMOS transistor n-Tr decreases.

[Means for solving problems]

FIG. 1 is a schematic side sectional view showing an embodiment of a CMOS semiconductor device manufactured by the method of the present invention.

The above-mentioned problem is that in forming the structure shown in the same figure, the step of forming the opposite conductivity type well (15) in the one conductivity type semiconductor substrate (1), and the impurity of one conductivity type in the opposite conductivity type well (15). A first carrier having a carrier concentration lower than that of the well (15) of the opposite conductivity type is formed by selectively counter-doping using ion implantation means.
Forming the opposite conductivity type region (16) of the first opposite conductivity type region (16) by ion-implanting the opposite conductivity type impurity to the surface portion of the first opposite conductivity type region (16) higher than the first opposite conductivity type region (16). Forming a second opposite conductivity type region (17) having a carrier concentration and a carrier concentration lower than that of the opposite conductivity type well (15), the first opposite surface region having the second opposite conductivity type region (17); Forming a gate electrode (5) on the opposite conductivity type region (16) through the gate insulating film (4), and using the gate electrode (5) as a mask, one conductivity type impurity is ion-implanted. Of the first and second conductivity type regions (6) facing each other in the first opposite conductivity type region (16) having the opposite conductivity type region (17) of
This is solved by the method for manufacturing a semiconductor device according to the present invention, which includes the steps of forming n) and (7n).

[Work]

That is, in the present invention, the well is made to have a high carrier concentration to reduce its resistance to enhance the resistance to latch-up, and the upper layer of the well is counter-doped by the ion implantation means so that the first low carrier which is deeper than the source and drain regions is formed. A concentration region is formed to reduce the junction capacitance between the source and drain regions, and a second low carrier concentration region having a higher concentration than the first low carrier concentration region and a lower concentration than the well is formed in the channel forming portion. It is formed by injection means to adjust the threshold voltage, whereby a CMOS semiconductor device that is resistant to external noise and operates at high speed is formed.

〔Example〕

 Hereinafter, the present invention will be specifically described with reference to illustrated embodiments.

FIG. 1 is a schematic side sectional view of a first embodiment of a CMOS semiconductor device formed by using the method of the present invention, FIG. 2 is a profile diagram of carrier concentration in a well in the first embodiment, and FIG.
The drawing is a schematic side sectional view of a second embodiment of a CMOS semiconductor device formed by using the method of the present invention.

The same object is denoted by the same symbol throughout the drawings.

In the method of manufacturing a semiconductor device according to the present invention, for example,
As shown in FIG. 1 showing an embodiment in a CMOS inverter, for example, n ⁻ having a carrier concentration of about 5 × 10 ¹⁴ cm ^−3.
In order to increase the latch-up resistance, a p-type well 15 having a carrier concentration of about 1 × 10 ¹⁷ cm ⁻³ and a depth of about 5 μm is formed on the main surface of the type silicon substrate 1. It is formed by using an implanting means, and is formed in the upper layer portion of the p-type well 15 in the vicinity of the depths of the source and drain regions without considering the latch-up resistance.
A p ^-- type first impurity introduction region having a depth of 0.7 to 1 μm, which has a carrier concentration lower than the well concentration of about ¹⁶ cm ⁻³ and contributes to the reduction of the junction capacitance between the source and drain regions. Are formed by counter doping with impurities of opposite conductivity type by ion implantation means.

The n ⁺ type source region 6 and the n ⁺ type drain region 7 having a carrier concentration of about 10 ²⁰ cm ^-3 and a depth of about 3000 Å are formed on the surface of the p ⁻ type first impurity introduction region 16 as usual. For example, about 6 × 10 ¹⁶ cm ⁻³ for adjusting the threshold voltage is formed on the surface layer portion of the channel formation region, that is, the separation region between the n ⁺ type source region 6 and the n ⁺ type drain region 7 by using the ion implantation means. Depth with carrier concentration of
A p ⁻ -type second impurity introduction region 17 of about 1000 Å is formed by using an ion implantation means.

When the same potential as the well 15 is applied to the source region 6, no junction capacitance is generated in the source region 6,
A part of the source region 6, that is, a part of the region close to the drain region 7 is the p ^-- type first impurity introduction region 16 for adjusting the threshold value.
It has only to be included in.

The manufacturing method and structure other than the above are the same as those of a normal CMOS inverter. In the figure, 4 is a gate SiO ₂ film, 5 is a gate electrode made of, for example, polycrystalline silicon, 8 is a p ⁺ -type source region, and 9 is
p ⁺ type drain region, 10 is n ⁺ type substrate contact region, 11 is
p ⁺ type well contact region, 12 is field SiO ₂ film,
13 is an n-type channel stopper having a carrier concentration of about 10 ¹⁷ cm ^-3 , and 14 is p having a carrier concentration of about 10 ¹⁷ cm ^-3.
Mold channel stopper, 18 is SiO ₂ film for impurity broking, 19
Is a PSG interlayer insulating film, 20a to 20f are electrode wirings made of, for example, aluminum, n-Tr is an nMOS transistor, and p-Tr is
7 shows a pMOS transistor.

As described above, when the CMOS semiconductor device is formed by the method of the present invention, the p-type well 15 in the nMOS transistor n-Tr region is mask-bonded to the surface of the substrate 1 with boron (B), for example, at a dose of 2.0 × 10 ^13. cm ^-2 , acceleration energy
Nitrogen (N ₂ ) is selectively ion-implanted under the conditions of about 160 KeV.
It is formed by heat-treating at about 1200 ° C. for about 180 minutes.

In addition, the p ^-- type first impurity introduction region 16 covers the pMOS transistor p-Tr formation region with a mask after forming the channel stoppers 13 and 14 and the field SiO ₂ film 12, and the p-type carrier 15 surface is covered with the p-type carrier. Counter-doping is carried out by selectively ion-implanting phosphorus (P), which is an n-type impurity for compensating C., with a dose amount of 1.5 × 10 ¹² cm ^-2 and an acceleration energy of about 180 KeV, and the temperature is 1100 ° C. in N _2. It is formed by heat-treating for about 60 minutes.

And also, p for the threshold voltage adjustment ^- immediately after the type second impurity ion implantation in the first impurity regions 16 to form the impurity introducing region 17 is completed, the p ^- type first impurity regions 16 It is formed by further ion-implanting boron (B) on the surface of the.

At this time, the implantation energy is about 30 KeV and the dose is
For example, when the thickness of the gate SiO ₂ film 4 is 300 Å and the threshold voltage is 0.7 V, it is about 5 × 10 ¹¹ cm ^-2 .

The activation of the B-implanted region is performed later simultaneously with the activation of the source / drain regions.

When the well is formed by the above method, as shown in the carrier concentration profile diagram in FIG.
The concentration profile of 15 shows a curve (b), and the concentration is moving in a considerably higher direction than the profile (a) of a normal well in which latch-up resistance is not considered.

Then, by the formation of the p ^-- type first impurity introduction region 16,
As shown in the curve (c), the concentration of the surface layer decreases, and the concentration of the depth S / D near the bottom of the source and drain 6, 7 can be understood by comparing points (a) and (b). Lower than usual.

However, the concentration of the bulk region BU with a depth of 1 μm or more, which contributes to the latch-up resistance, does not decrease so much, and it is clear that comparing the points (c) and (d), the concentration is significantly higher than that of the normal structure. Becomes

The above shows that the latch-up resistance increases and the junction capacitance between the source and drain 6 and 7 decreases.

The curve (d) indicated by the dotted line in the figure shows that the p ⁻ -type second impurity introduction region 17 is formed by ion-implanting p-type impurities into the surface of the p ⁻ -type first impurity introduction region 16. 3 is a final density profile of the above-described embodiment after the threshold adjustment is performed.

Next, a case where the present invention is applied to a short-channel CMOS semiconductor device will be described.

Source channel 6 and drain channel 7 are formed into short channels
In the CMOS semiconductor device in which the interval between the second impurity introduction region 17 and the second impurity introduction region 17 is extremely narrow as in the first embodiment.
Is formed shallowly, in the first impurity introduction region 16 having a low carrier concentration below the second impurity introduction region 17,
A depletion layer extending from the drain region 7 reaches the source region 6 to cause punch-through, resulting in a phenomenon that the device does not function.

The structure for preventing such short channel effect is the second embodiment shown in FIG.

In this structure, as shown in the figure, the p ⁻ -type first layer is selectively formed between the source region 6 and the drain region 7 at least deeper than the source and drain regions 6 and 7, and also serves to adjust the threshold voltage. The second impurity introduction region 117 is formed.

By doing so, the carrier concentration in the lower part of the channel region is higher than that in the above-mentioned embodiment, and punch-through is prevented even when the channel is made short.

The second impurity introduction region 117 in this embodiment is
It is formed by selectively and deeply ion-implanting B into a channel forming region, that is, a region corresponding to a space between the source region 6 and the drain region 7.

At this time, when the same threshold voltage as that described above is desired, the dose amount needs to be slightly higher than that in the first embodiment, and the acceleration energy is 3000 Å when the depth of the source / drain regions 6 and 7 is 3000.
In the case of about 100 to 120 KeV is suitable.

Although the present invention has been described with respect to the p-type well, it goes without saying that the present invention is also applied to the n-type well in the twin tub structure. However, in this case, the conductivity types of the first and second impurity introduction regions are opposite to those in the above embodiment.

〔The invention's effect〕

As described above, according to the present invention, a CMOS semiconductor device having a high threshold voltage, a small junction capacitance between the source and drain, and a predetermined threshold voltage is formed.
A high-speed CMOS IC that is resistant to external noise is provided.

[Brief description of drawings]

FIG. 1 is a schematic side sectional view of a first embodiment of a CMOS semiconductor device according to the present invention, FIG. 2 is a profile diagram of carrier concentration in well in the first embodiment, and FIG. 3 is a second view of the present invention. FIG. 4 is a schematic side sectional view including an equivalent circuit showing a configuration of a CMOS inverter, and FIG. 5 is a schematic side sectional view of a CMOS semiconductor device formed by a conventional method. In the figure, 1 is an n ^- type silicon substrate, 2 is a p-type well, 3 is a threshold adjustment p ^- type counter dose region, 4 is a gate SiO ₂ film, 5 is a gate electrode, 6 is an n ⁺ type source region, 7 Is an n ⁺ type drain region, 8 is a p ⁺ type source region, 9 is a p ⁺ type drain region, 10 is an n ⁺ type substrate contact region, 11 is a p ⁺ type well contact region, 12 is a field SiO ₂ film, 13 Is an n-type channel stopper, 14 is a p-type channel stopper, 15 is a p-type well, 16 is a p ^-- type first impurity introduction region, 17,117 is a p ^-- type second impurity introduction region, and 18 is an impurity block SiO. _Two films, 19 is a PSG interlayer insulating film, and 20a, 20b, 20c, 20d, 20e, 20f are electrode wirings.

Claims (1)

[Claims] 1. A step of forming an opposite conductivity type well (15) in a semiconductor substrate (1) of one conductivity type, wherein a impurity of one conductivity type is selectively countered in the opposite conductivity type well (15) by using ion implantation means. A step of doping to form a first opposite conductivity type region (16) having a carrier concentration lower than that of the opposite conductivity type well (15), ion-implanting opposite conductivity type impurities to form the first opposite conductivity type region ( A second opposite conductivity type region (17) having a higher carrier concentration than the first opposite conductivity type region (16) and a lower carrier concentration than the opposite conductivity type well (15) is formed on the surface portion of 16). Forming a gate electrode (5) via a gate insulating film (4) on the first opposite conductivity type region (16) having the second opposite conductivity type region 17 on the surface thereof; Using the electrode (5) as a mask, impurities of one conductivity type are ion-implanted and the second opposite conductivity is obtained. First opposite the first opposite conductivity type region (16) in having a region (17) in the surface portion,
A method of manufacturing a semiconductor device, comprising the step of forming second one-conductivity type regions (6n) and (7n).