JPH077000U - IC memory card - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain a memory card for a computer that is downsized and saves power. [Configuration] A bufferless memory card of 5.12 cm × 8.56 cm. The memory array is divided into a plurality of banks, one bank is operated by RAS selection, and the other bank is in a standby mode. The pin arrangement of the connector is
It is a two-row staggered array. A computer or the like equipped with this memory card reads the state of the memory card from a predetermined detection pin to determine the number of banks and the refresh mode.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a computer memory card designed to reduce half-height or height, which is used in applications where full-height memory cards can be used and where space is more limited.

[0002]

Detailed Description of Preferred Embodiments

 A preferred embodiment of the present invention is an IC DRAM card, which is configured into word-accessible bits by pin arrangement. The preferred embodiment is a 4 megabit, 8 megabit and 16 megabit IC DRAM card, each configured as a 1 mega x 32, 2 mega x 32, 4 mega x 32 bit memory array. The present invention is a bufferless version with a length of 5.12 cm, JEDEC standard 8.56 cm, and an 88-pin x 32 IC DRAM card. Since no buffer is included on the card, timing delays on the board must be eliminated, and redrive circuitry must be mounted on the system board as needed. The card is also manufactured as a memory array of 2Mx16, 4Mx16, 8Mx16bit, DQ on the host system is made common, and memory bank control means is installed. A separate CAS input allows byte access. The card is also made as a buffer version.

The present invention is designed for low power operation using 3.3V or 5.0V, 1M × 4 low power extended refresh DRAM. These devices support the BBU refresh cycle as a very low current data retention mode. A standard configuration DRAM refresh mode is also supported.

Multiple RAS inputs maintain power by allowing independent bank selection. In the x32 configuration, the memory array is divided into 2 banks by dividing every 4 bytes. In the × 16 configuration, up to 4 banks are divided into 2 bytes and selected independently. One bank operates by each RAS selection, the others remain in standby mode and are not selected, resulting in minimal power consumption.

Each of the sense pins of the present invention is read by the host to determine the configuration, number of banks, access time and refresh mode of the present invention. These extensive detection features of the present invention allow the system to take advantage of improved power savings.

[0006]

【Characteristic】

 5 cm long bufferless IC DRAM card, JEDEC standard 88 pin IC DRAM pin output, polarized receptacle connector, industry standard DRAM function and timing, high performance CMOS silicon gate process, all outputs TTL compatible, Multiple RAS input selectivity for x16 or x32, refresh mode, RAS only, CAS before RAS (CBR), hidden and battery backup (BBU), fast page mode access cycle, 2.3V version, single + 3.3V ± 5% power supply, standby 3.2mW low power consumption, operation 1.4W (standard value), 5.0V version, single 5.0V ± 5% power supply, standby 8mW low Power consumption, 2.2W during operation (standard value).

The pin arrangement is in two staggered rows, with the first row having 44 pins and the second row having 44 pins, as follows.

[0008] Pin Signal Name Pin Signal Name _{1 V ss 45 V ss 2 DQ0} 46 DQ16 3 DQ1 47 DQ17 4 DQ2 48 DQ18 5 DQ3 49 DQ19 6 DQ4 50 DQ20 7 DQ5 51 DQ21 8 DQ6 52 DQ22 9 NC (V cc 5.0v) 53 DQ23 10 DQ7 54 NC 11 V _cc (3.3v) 55 NC 12 NC 56 V _ss 13 A0 57 A1 14 A2 58 A3 15 NC (V _cc 5.0v) 59 A5 16 A17 60A _cc (3.3v) 61 A9 18 A6 62 NC 19 A8 63 V _ss 20 NC 64 NC 21 21 NC 65 NC 22 RASO 66 CAS2 23 CASO 67 V _ss 24 24 CAS 1 68 CAS3 25 S CC 3 25 V _cc. 70 WE 27 NC (V _cc 5.0v) 71 PD1 (V _ss ) 28 PD2 (NC) 72 PD3 (V _ss ) 29 PD4 (V _ss ) 73 V _ss 30 PD6 (TBD) 74 PD ₅ (NC) 31 NC 75 PD7 (TBD) 32 NC 76 PD8 (NC) 33 NC 77 77 NC 34 DQ8 78 NC 35 V _cc (3.3v) 79 NC 36 DQ9 80 DQ24 37 37 NC (V _cc 5.0v) 81 DQ25 38 38 DQ10 82Q DQ26 83D DQ28 41 DQ13 85 DQ29 42 DQ14 86 DQ30 43 DQ15 87 DQ31 44 V _ss 88 V _ss

[Brief description of drawings]

FIG. 1 is an isometric view of a chip card showing an electrical connector and body shell at one end.

FIG. 2 is a front view of the isometric view of the chip card from a different direction than FIG. 1, showing the body shell.

FIG. 3 is a plan view of a chip card.

FIG. 4 is a side view of the chip card.

FIG. 5 is a cross-sectional view of a chip card.

FIG. 6 is a bottom view of the chip card.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Van Tsukada, War Bonnet 7568, Boyes, Idaho, 83709 USA 7568

Claims (3)

[Scope of utility model registration request] 1. An outer box comprising an outer box, a circuit element in the outer box, and a connector at one end of the outer box. When the computer is equipped with the outer box, the computer can address the data, and the computer stores data. It is an outer box that reduces the length from one end of the box to the opposite end, and applications where a full-height memory card can be used,
A memory card for computers, which can be used in applications where a full-height memory card cannot be used because the space is limited. 2. The memory card according to claim 1, wherein the memory card is a circuit element addressable by a plurality of bits of at least 1 byte, and a single address addresses a plurality of bits. 3. An outer box, a circuit element in the outer box, at least 1.
Multiple bits of a byte, where a single address consists of addressable circuit elements that address each of the multiple bits and a connector at one end of the outer box, which when installed in a computer makes it addressable by the computer and stores the data in the computer. An array addressable card for a computer, which can be used in applications where a full height array addressable card can be used, and in applications where a full height array addressable card cannot be used due to limited space.