JPH0769877B2 - Channel device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a channel device in a data processing system, data is buffered for the purpose of preventing more than the number of bytes indicated by a channel command word from being taken in by incorrect prediction control. The data buffer control unit for controlling the data buffer storage device is provided with correction data generating means for generating data for correcting the prediction data from the condition of the control signal when the chain data flag of the next channel command word connected by the chain data flag is OFF. In addition, the input / output interface control unit for controlling the bus register for the input / output interface is provided with a prediction correction unit for correcting the prediction data with the correction data generated by the correction data generation unit, and the next channel connected by the chain data flag. Command command When Ji, the prediction correction means, configured to forcibly correct the predictive control data.

[Industrial application field]

The present invention relates to a channel device in an information processing system.

In the data exchange between the channel device and the input / output control device, the transfer speed between them is increasing year by year. However, the system clock cycle on the channel side is not necessarily improved in proportion to it. This is because, for example, the circuit element is changed from TTL to CMOS in consideration of the degree of integration.

Therefore, an efficient transfer method is required for data transfer between the channel device and the input / output control device.

[Conventional technology]

Predictive control has become necessary and is actually being performed as one of the methods for improving the efficiency of the communication between the channel device and the input / output control device.

This is to control whether to receive the next data of the data sent byte by byte from the input / output control device or to give a stop instruction in the data reading operation from the input / output control device by several bytes ahead. To predict and give instructions.

FIG. 5 is a diagram showing a configuration example of the channel device.

In the figure, 1 is a channel device, 2 is a central processing unit (hereinafter abbreviated as CPU), 3 is a main memory (hereinafter abbreviated as MSU), 4 is a main memory access control device (hereinafter abbreviated as MAC) Reference numeral 5 denotes an input / output control device (hereinafter abbreviated as IOC).

Reference numeral 11 is a data buffer storage device (hereinafter abbreviated as DBS), which is a buffer storage of data between IOC5 and MSU3.
Is the DBS controller.

Reference numeral 13 is a bus register for interfacing with the IOC, and 14 is an IO interface control unit.

Reference numeral 15 is an aligned data storage (hereinafter abbreviated as ALDS) that organizes data between MSU3 and DBS11 according to addresses, and 16 is a system bus control unit.

FIG. 6 is a diagram showing a configuration example of a prediction control relationship in the channel device.

In the figure, the signal SVI is the data from the IOC to the data bus (BU
It is a tag signal sent when it is sent on top of SI).

The signal ACCOK is a signal indicating that there is a space to store data in DBS, and CMRSP is the number of data indicated by the byte count in the channel command word (abbreviated below as CCW).
It is a signal indicating that it cannot receive the subsequent data because it was captured in. ACCOK has four of ACCOK0-3, CMR
SP has 4 of CMRSP0-3, DBS NOW, DBS NEX
T, ISWITCH are used as pointers in order.

DBS NOW is a value that indicates ACCOK and CMRSP currently in use (0
~ 3) and DBS NEXT is ACCOK and C to be predicted next
A value (0 to 3) indicating MRSP, which is generated by the counter. The difference between DBS NEXT and DBS NOW represents the amount of advance payment. ISWITCH
Is a counter indicating which of ACCOK and CMRSP is used to generate a response signal to the input / output control device.

Signal Service In (SVI) is a tag signal sent from the IOC when data is sent on the data bus (BUSI). When the SVI arrives, the DRQ1 flip-flop (FF) is set and the signal DRQ1 becomes "1". Signal DRQ1
Is "1" when there is a write request to the DBS and "0" when it is written.

The signal SVI is delayed by the delay circuit DL, and the signals ACCOK0-
When 3 and 3, the AND circuit A1 is entered, and if there is a match, the flip-flop SVOFF is set. Signal SVO is sent when SVOFF is set. Signal SVO (service out) IO
It is a response signal of the channel device in response to the reception of the data sent from C by the channel device.

Similarly, the signal SVI delayed by the delay circuit DL is the signal CMR.
The AND circuit 42 is entered together with SP0 to SP3, and if a match is found, the flip-flop CMOFF is set. The signal CMO is sent out when CMOFF is set. Signal CMO (command out)
Is a signal to which the channel device responds when the channel device cannot receive the data sent from the IOC.

Service out (SVO) signal, ACCOK is on and CMRS
Issued on condition that P is off.

By "1" of the signal DRQ1, the IBA which is a pointer for writing the data sent from the IOC to the DBS is advanced. When data is written to MSU from DBS, MB which is a pointer for reading the data of DBS to MSU
A is advanced by one.

IEBA which is the end pointer in DBS indicated by the byte count indicated by CCW, CDFLG which indicates that the flag indicated by CCW is a chain data flag, CCW which is concatenated by chain data flag is fetched and the flag related to that CCW Is turned on at the timing of setting, and is reset at the next timing when IEBA for that CCW is set. Each data of signal CDCMP and MBA,
A as the response of the next prediction above depending on the value of the IBA data
Either CCOK or CMRSP is set. Thus, based on the forecast, the next data can be accepted (ACCOK)
Whether to turn on or not accept (CMRSP) is the prediction data.

FIG. 7 shows an example of a time chart of each signal in the channel device under the predictive control. The time chart example shown in FIG. 7 shows the situation when the reading operation is performed by the CCW configuration as shown in FIG.

In FIG. 8 (a), the first CCW is read (READ).
It is a command, the byte count (BC) is 1, and the chain data flag (CD) is "1", that is, the data is chained. The second CCW is a CCW linked by a chain data flag, has a byte count (BC) of 1 byte, and has a chain data flag (C
D) is "0", which means that the command is finished. Such CCW is used for reading when the data on the input / output device side is divided into two blocks of 1 byte and 1 byte with a gap therebetween as shown in FIG.

The operation will be described below with reference to the time chart of FIG. The description of the initial conditions of cycles 0 and 1 is omitted.

(1) When SVI rises from the I / O controller in cycle 2, DRQ1 is turned on and a 1-byte store request is issued to DBS, then the read (READ) flag is turned on and SV
I on, ISWITCH is “0”, ACCOK0 is “1”, CMRSP0
Is 0, service out (SVO) is turned on. When SVO turns on, the prediction needs to move to the next
Advance SWITCH to "1". In the figure, the small circles on the vertical lines indicate the conditions, and the small arrows indicate the resulting signal set. In the figure, DBS NEXT-DBS NOW = 2 and the two destinations are predictively controlled and already ACCOK0, ACCOK1, ACCOK2
Is “1”.

(2) Next, CDFLG is ON, IEBA-IBA = "1", MB
Since A is “0”, DRQ1 is on, and DBS NEXT is “2”, ACC
OK3 is turned on.

(3) Next, READ is on, DBS NOW is “0”, and ACCOK
Since 0 is on and CMRSP0 is off, writing to DBS is done, DRQ1 is dropped, IBA is “1”, DBS NOW is “1”,
DBS NEXT is advanced to "3".

(4) When writing to MSU, MBA is advanced to "1".

(5) In cycle 6, the next CCW is fetched and its C
Since the chain data flag of CW is "0", CDFL
G is turned off and CD CMP is turned on. Next, since the byte count of this CCW is "1", IEBA is "2" (current
IEBA + byte count) is set. CD CMP is turned off at the next timing.

(6) When SVI is raised in cycle 10, DVO1 is turned on, ISWITCH is "1", ACCOK1 is on, and CMRSP1 is off, so SVO is turned on. With SVO on,
ISWITCH is advanced to "2".

(7) CDFLG is off, but IEBA-IBA = "1",
Since MBA is “1” and DRQ1 is on, ACCOK0 is continuously turned on. Then READ is on, DBS NOW is “1”, A
Since CCOK1 is on and CMRSP1 is off, DBS is written, DRQ1 is dropped, IBA is “2”, DBS NOW is “2”.
Then, DBS NEXT is advanced to "0".

(8) When SVI is raised in cycle 12, DVO1 is turned on, ISWITCH is "2", ACCOK2 is on, and CMRSP2 is off, so SVO is turned on. With SVO on,
ISWITCH is advanced to "3". CDFLG is off and IEBA
-IBA = "0", MBA is "2", DRQ1 is on
ACCOK1 is reset. Then READ is on, DBS NOW
Is "2", ACCOK2 is on, CMRSP2 is off
DBS is written, DRQ1 is dropped, IBA is "3"
Then, DBS NOW is advanced to "2" and DBS NEXT is advanced to "1".

As a result, the byte count specified by the second CCW is 1
However, since 2 bytes ahead ACCOK and CMRSP are set, 2 bytes will be written to DBS.

[Problems to be solved by the invention]

As explained above, in predictive control in a channel device, when the current CCW chain data flag is on, the prediction is done before the next CCW fetch and the byte incorrectly indicated in the CCW. Occasionally, more than the count of data was taken into the channel device, an error condition called chaining check occurred, and the system sometimes stopped.

The present invention is intended to provide a channel device that solves the above-mentioned conventional problems.

[Means for solving problems]

 FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, reference numerals 1 to 5 represent the same objects as those shown in FIG.

Reference numeral 121 is a correction data generating means, which generates data for correcting the prediction data from the condition of the control signal.

Reference numeral 141 denotes a prediction correction means, which corrects the prediction data with the correction data generated by the correction data generation means 121.

[Work]

Channel device 1 uses predictive control to ACCOK 2 bytes ahead
And CMRSP are set to respond to the I / O controller and write to the DBS.

After reading the number of bytes indicated to the current CCW, the next CCW linked to this CCW by the chain data flag is fetched. When the chain data flag indicated by the new CCW is "0" and it is the end of this command, the correction data generation means 121 uses the byte count indicated by the CCW to calculate the predicted data from the current state of each signal. Generate modified data.

The prediction correction means 141 uses the correction data generated by the correction data generation means 121 to set the CMRS set by prediction.
Force P to be fixed. This allows command out (C
MO) is issued, and the operation is completed by fetching the data of the byte count indicated by CCW.

〔Example〕

The present invention will be described more specifically with reference to the examples shown in FIGS. 2 to 4.

FIG. 2 is a time chart showing the operation according to the embodiment of the present invention. It is created under the same conditions as the time chart of the conventional example shown in FIG.

In FIG. 2, the operation sequence up to cycle 7 is exactly the same as in FIG.

(11) In cycle 8, CDFLG is off and IEBA
-IBA = 1, DRQ1 off, CDCMP off, DBS NEXT
-CMRSP2 is set to "1" under the condition that DBS NOW = 2. Setting CMRSP2 to "1" is the correction of the prediction data, which is executed by the correction data generation unit and the prediction correction unit described later.

(12) In cycle 10, SV from the input / output set device side
When I is raised, SVO is turned on because DRQ1 is turned on, ISWITCH is “1”, ACCOK1 is on, and CMRSP1 is off. With SVO on, ISWITCH is advanced to "2".

(13) CDFLG is off, but IEBA-IBA = "1",
Since MBA is “1” and DRQ1 is on, ACCOK0 is continuously turned on. Then READ is on, DBS NOW is “1”, A
Since CCOK1 is on and CMRSP1 is off, DBS is written, DRQ1 is dropped, IBA is “2”, DBS NOW is “2”.
Then, DBS NEXT is advanced to "0".

(14) In cycle 12, when SVI is raised, DRQ1
Is turned on, ISWITCH is “2” and ACCOK2 is turned on, but CMRSP2 is “on”, so the conditions for issuing SVO are not satisfied as described in the section of the prior art and SVO is issued. Instead, a command out (CMO) is issued. ACCOK1 is reset because CDFLG is off, IEBA-IBA = "0", MBA is "2" and DRQ1 is on. Then READ is on, DBS NOW is “2” and ACCOK2 is on, but CMR
Since SP2 is ON, DBS is not written, DRQ1 is not dropped, IBA and DBS NOW are not updated, and DBS NEXT is advanced to "1".

As described above, CMRSP2 is modified, command out (CMO) is issued, and the second byte is not captured by the new CCW.

FIG. 3 is a circuit diagram of an essential part of a correction data generating section in an embodiment of the present invention.

The OR gate OR1 calculates the OR of the signals READ, -CDCMP (inverted output of CDCMP), DRQ1, and DBS NEXT-NOW = 2. The condition of DBS NOW = 2 and the condition of CD FLG off and IEBA-IBA = 2 by AND gate A1 ((▲ ▼) IEBA-I
Take the AND of BA = 1) and use the AND gate A2 to DBS NOW = 3
And the condition that CD FLG is off and IEBA-IBA = 1 ((▲ ▼) IEBA-IBA = 1) are ANDed, and NOR of the outputs of AND gates A1 and A2 is obtained by NOR gate OR2. NOR
The output obtained by obtaining the NOR of the outputs of the OR gates OR1 and OR2 by the gate OR6 becomes SET-CMO0 (* 0).

Similarly, under the conditions of DBS NOW, IEBA, IBA shown in the figure, SET-CMO1 (*
1), SET-CMO2 (* 2), and SET-CMO3 (* 3) are required. This SET-CMO0 (* 0), SET-CMO1 (* 1), SE
The corrected data is T-CMO2 (* 2) and SET-CMO3 (* 3). Signals not directly related to the present invention are omitted.

FIG. 4 is a circuit diagram of a main part of the prediction correction unit in the embodiment of the present invention. Also in this figure, signals not directly related to the present invention are omitted.

Three AND gates A8, A9, and A10 are used to obtain the AND of the conditions of the difference between the values of DBS NEXT and NOW and the difference between the values of IEBA and IBA.
The gate OR10 determines the OR of those outputs. NAND
NAND of the output of OR gate OR10 and the condition of CD off with gate A11
Is taken. The output of the NAND gate A11 becomes the set input of the flip-flop FF1 via the NOR gates OR11 and OR12. The output of the flip-flop FF1 becomes the signal CMO0.

Similarly, the flip-flops FF2 and FF are
3, FF4 is set, and signals CMO1, CMO2, CMO3 are generated.

Signals CMO0, CMO1, CMO2, CMO3 are AND gates A20, A21, A22, A2
Entered in 3, ANDed with the value of DBS NOW, NOR gate OR
NOR is taken at 21 and a set signal CMRSP-NOW of CMRSP for outputting a command-out signal (CMO) is generated.

Similarly, the signals CMO0, CMO1, CMO2, CMO3 are connected to AND gates A24, A2.
Input to 4, A26, A27, AND with the value of DBS NEXT, NO
NOR is taken by the R gate OR22 and the set signal CMRSP− of CMRSP−
NEXT is generated.

Similarly, the signals CMO0, CMO1, CMO2, CMO3 are AND gates A28, A2.
Input to 9, A30, A31, ANDed with ISWITCH value, NOR
NOR is taken by the gate OR23 and CMRSP set signal CMRSP−
i is generated.

Modified data SET-CMO0 (* 0), SET-CMO shown in Fig. 3
1 (* 1), SET-CMO2 (* 2), SET-CMO3 (* 3)
It is put into the other input of each NOR gate OR11, OR14, OR17, OR19, and each flip-flop FF1, FF2, FF3, FF
Set 4 forcibly.

〔The invention's effect〕

As described above, according to the present invention, when the chain data flag is turned off in the next CCW connected by the chain data flag, the chaining flag is prevented from being erroneously caused by the predictive control, and the data processing efficiency is improved. The effect of contributing to is great.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a time chart of each signal according to one embodiment of the present invention, FIG. 3 is a circuit diagram of a correction data generation unit in one embodiment of the present invention, and FIG. FIG. 5 is a circuit diagram of a prediction correction unit in one embodiment of the present invention, FIG. 5 is a diagram showing a configuration example of a channel device, FIG. 6 is a diagram showing a configuration example of prediction control relation in the channel device, and FIG. A time chart of each signal according to an example, FIG. 8 is a diagram showing a configuration example of CCW. In the drawing, 1 is a channel device, 2 is a central processing unit (CPU), 3 is a main memory unit (MSU), 4 is a main memory access control unit (MAC), 5 is an input / output control unit (IOC), and 11 is a data buffer. Storage device (DBS), 12 DBS control unit, 13 bus register, 14 IO interface control unit, 15 align data storage (ALDS), 16 system bus control unit, 121 correction data generating means (unit), 141 is a prediction correction means (part), A1 to A31 are AND gates or NAND gates, OR1 to OR23 are OR gates or NOR gates, and FF1 to FF4 are flip-flops.

Claims (1)

[Claims] 1. A data buffer storage device (11) is provided for controlling data transfer between a main storage device (3) and an input / output control device (5), and in the read operation, 1 byte from the input / output control device (5). In the channel device (1) that predicts and controls a few bytes ahead of whether to receive the next data of the data sent each time or to instruct the stop, the next channel command linked by the chain data flag Correction data generating means (121) for generating data for correcting the prediction data from the current state of the control signal based on the byte count indicated by the channel command word when the word chain data flag is off; And a prediction correction means (141) for correcting the prediction data by the correction data generated by the means (121). When fetched the concatenated next channel command word Ri, the prediction correction means (14
A channel device characterized by being configured to forcibly correct predicted data according to 1).