JPH0769764B2 - Tablet - Google Patents

Description

TECHNICAL FIELD The present invention relates to a tablet suitable for application to a display-integrated tablet in which a tablet for inputting coordinates is integrated with a display.

[Prior Art] Conventionally, in a display-integrated tablet, as shown in FIG. 9, a display 51 and a tablet 52 are formed separately and independently, and they are integrally formed by bringing them into close contact with each other. Here, for example, an EL (electroluminescence) display element is used as the display 51, and a capacitive coupling type is used as the tablet 52. In FIG. 9, 53 is a pen for detecting a scanning pulse.

[Problems to be Solved by the Invention] By the way, according to such a configuration, for example, by pressing the tip of the pen 53 against the glass surface of the tablet 52, a mechanical switch built in the pen 53 is turned on to detect coordinates. However, the operation is troublesome, and the number of parts is large, so the cost is high, and there are also moving parts, and there is a fear of failure.

Therefore, it is an object of the present invention to provide a tablet which has good operability, is made inexpensive by reducing the number of parts, and has no moving parts so that there is no fear of failure.

[Means for Solving the Problems] The present invention includes a matrix panel, a row electrode driver, a column electrode driver, a row coordinate detection unit, a column coordinate detection unit, and a detection conductor, The scanning pulse sequentially supplied to the row electrodes of the panel is detected by the detection conductor and is supplied to the row coordinate detection unit to detect the row coordinates, and the column electrodes are sequentially supplied to the column electrodes of the panel. A tablet in which the column coordinates are detected by the scanning pulse being detected by the detection conductor and being supplied to the column coordinate detection unit, wherein at least one of the row electrode and the column electrode of the panel is provided by a corresponding electrode driver, The scanning pulse having the same pulse width is sequentially delayed by a phase shorter than the pulse width.

[Operation] In the above-described configuration, at least one of the row electrode and the column electrode of the panel is supplied with the scanning pulse having the same pulse width sequentially delayed by a phase shorter than the pulse width, that is, to adjacent electrodes. On the other hand, since the scanning pulses are supplied while partially overlapping with each other, the level of the detection signal of the detection conductor increases.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG.

In the figure, 1 is a thin film EL matrix panel,
y1, y2, ..., Yn are row electrodes, and x1, x2, ..., Xm are column electrodes.

A row electrode driver 2 has a plurality of output terminals connected to the row electrodes y1, y2, ..., Yn of the panel 1, respectively. Further, 3 is a column electrode driver, and the plurality of output terminals thereof are the column electrodes x1, x2, ..., x of the panel 1, respectively.
connected to m.

The operations of the row electrode driver 2 and the column electrode driver 3 are controlled by the timing generation circuit 4.

As shown in FIG. 2, in the display mode, the row electrode driver 2 sequentially supplies the scan electrodes P1, y2, ..., Yn to the row electrodes y1, y2, ... The voltage VSD corresponding to the display data SD is simultaneously supplied to the electrodes x1, x2, ..., Xm for each scanning line.

In the row coordinate (y coordinate) detection mode, the row electrode driver 2 sequentially scans the row electrodes y1, y2, ...
y'is supplied. In this case, the pulse width of the scan pulse Py ′ is widened, and the scan pulse Py ′ is simultaneously supplied to a plurality of adjacent electrodes, for example, 20 electrodes among the row electrodes y1, y2, ..., Yn. Are sequentially scanned in the open state.

In the column coordinate (x coordinate) detection mode, the column electrode driver 3 sequentially scans the column electrodes x1, x2, ...
x'is supplied. In this case, the pulse width of the scan pulse Px ′ is also widened, and the scan pulse Px ′ is simultaneously supplied to a plurality of adjacent electrodes of the column electrodes x1, x2, ..., Xm, for example, 20 electrodes. Are sequentially scanned in the open state.

The display mode period, the row coordinate detection mode period, and the column coordinate detection mode period are time-divided in each frame. It should be noted that the order is not limited to the example shown in the figure, and may be arbitrary.

Here, the polarity of the scan pulse Py in the display mode is 1
It is made to invert every frame. Further, it is desirable that the polarities of the scanning pulses Py ′ and Px ′ in the coordinate detection mode are also inverted for each frame, but they may be unipolar pulses for simplification of the circuit.
In this case, lower voltage is better, but if it is too low,
S / N cannot detect the scan pulses Py ′ and Px ′ well.

For example, in the display mode, the light emission threshold voltage is ± 200V.
On the other hand, + 215V or -165V is selectively supplied to the row electrodes y1, y2, ..., yn as the scan pulse Py, and + 50V or 0V is selectively supplied to the column electrodes x1, x2, ..., xm as the voltage VSD. , ± 215 V is supplied to the light emitting pixel portion, and ± 165 V is supplied to the non-light emitting pixel portion with the polarities alternately inverted for each frame. Also,
In the row coordinate detection mode, the row electrodes y1, y2, ...
, Yn is supplied with + 25V as the scanning pulse Py ′, and in the column coordinate detection mode, + 25V is supplied as the scanning pulse Px ′ to the column electrodes x1, x2, ..., Xm.

With the above configuration, in the display mode, the row electrodes y1, y2, ...
..., yn is sequentially supplied with a scanning pulse Py in units of one electrode, and the column electrodes x1, x2, ..., xm are simultaneously supplied with a voltage VSD corresponding to the display data SD for each scanning line. Therefore, display driving is performed by line-sequential scanning, and an image corresponding to the display data SD is displayed.

Reference numeral 5 denotes a pencil-shaped conductor (hereinafter referred to as "pen"), and by bringing the pen 5 into contact with an arbitrary position on the panel 1, a scanning pulse is detected by capacitive coupling.

In this case, in the coordinate detection mode as described above,
Since the scanning pulses Py ′, Px ′ are simultaneously supplied to a plurality of adjacent electrodes at the same time, the scanning pulses Py ′, Px ′ are supplied to only one electrode.
The level of the detection signal of the pen 5 increases. This will be described in detail with reference to FIG.

In the figure, 41 is a pencil-shaped conductor (hereinafter referred to as "pen"), and 42 is a glass plate of a thin film EL matrix panel. Reference numeral 43 denotes a matrix electrode, which is originally composed of two layers of a row electrode and a column electrode, but only one layer is shown for simplification of description. 44 is a changeover switch for scanning, 45 is a power source for scanning pulse, and 46 is an input impedance of an amplifier for scanning pulse detection (amplifier 6 in FIG. 1).

A capacitor exists between the pen 41 and the electrode 43 as shown in the figure, and its capacitance is designated as Ci corresponding to the electrode number i. The electrode 43 is grounded when j ≦ i−1 or j ≧ i + 4 and connected to the power supply 45 when i ≦ j ≦ i + 3. The number of electrodes 43 is n, and 1 ≦ j ≦ n.

FIG. 4 shows an equivalent circuit in this case. Here, CVS = Ci + Ci + 1 + Ci + 2 + Ci + 3 CGND = C1 + C2 + ... + Ci-1 + Ci + 4 + ... + Cn, and the detection signal vs by the pen 41 becomes | Zin | >> 1 / ωCGND as follows. | Zin | is the magnitude of the input impedance 46.

Here, VS is the voltage value of the power supply 45, Co is the total capacitance formed between the pen 41 and the electrode 43, and is CVS + CGND.

As is clear from the equation (1), in the system in which the power supply 45 is supplied to the electrodes 43 one electrode at a time, when n is several hundreds, CVS
Since << Co, the detection signal vs is small, and it becomes difficult to detect the scanning pulse. However, if the number of electrodes 43 to which the power supply 45 is simultaneously supplied is increased as in this example, the CVS is correspondingly increased.
Becomes larger, the detection signal vs becomes larger, and the detection of the scanning pulse becomes easier.

In this case, the capacitance of the capacitor formed by the electrode 43
As shown in FIG. 5, Ci becomes smaller as it gets farther from the pen 41. For example, in the case where the electrode pitch is 0.3 mm and the glass thickness is 2.4 mm, the influence can be neglected at a distance far from the left and right 10 electrodes. Therefore, the number of electrodes 43 to which the power source 45 is supplied at the same time may be 20, and even if the number of electrodes 43 is increased more, the effect of increasing the level of the detection signal cannot be expected.

In FIG. 1, the detection signal of the pen 5 is supplied to and amplified by the amplifier 6, and the detection signal vs from the amplifier 6 is supplied to the comparator 7 and compared with the reference voltage Vr. The output voltage vs of the amplifier 6 of the detection signal of the pen 5 decreases substantially in inverse proportion to the distance d between the pen 5 and the glass plate, as shown in FIG. The reference voltage Vr is set equal to the level of the detection signal vs when the distance d is do. Distance as described below
do is a position for entering the coordinate detection operation, is determined in advance in consideration of operability, and is set to 1 mm, for example. Detection signal vs when pen 5 is on glass (glass thickness = 2.4 mm), that is, d = 2.4 mm
Is 3V and d = 4 mm, the detection signal vs becomes 1V. Therefore, in this case, if Vr = 2V, do = 3.4 mm, which is a distance of 1 mm from the glass plate surface.

The comparator 7 outputs a high level "1" signal when the detection signal vs is larger than the reference voltage Vr, and outputs a low level "0" signal when the detection signal vs is smaller than the reference voltage Vr. And this comparator 7
Is output to the AND circuit 8.

Further, the detection signal vs from the amplifier 6 is supplied to the peak time detection circuit 9, and the peak time detection circuit 9 outputs a high level “1” signal at the peak time of the detection signal vs. At the time of, a low level “0” signal is output. Then, the output signal of the peak time point detection circuit 9 is supplied to the AND circuit 8.

From the AND circuit 8, the detection signal vs is higher than the reference voltage Vr, and a high level "1" signal is output at the peak time of the detection signal vs, and a low level "0" signal is output at other times. It The output signal of the AND circuit 8 is supplied to the row coordinate detecting section 10 and the column coordinate detecting section 11. In this case, the row coordinate detection unit 10 is composed of, for example, a counter,
A reset signal is supplied from the timing generation circuit 4 before the row coordinate detection mode is entered, and the reset signal is reset.
Sequential scan pulse P to the row electrodes y1, y2, ..., yn of panel 1
The clock is supplied and counted at the timing when y'is supplied, and the counting operation is stopped at the timing when the output signal of the AND circuit 8 becomes the high level "1". Therefore, the row coordinate detection unit 10 obtains a count value corresponding to an arbitrary position of the panel 1 with which the pen 5 is in contact as a row coordinate output.

The column coordinate detection unit 11 is also composed of, for example, a counter,
A reset signal is supplied from the timing generation circuit 4 before the column coordinate detection mode is set and reset, and
Sequential scan pulse P to the column electrodes x1, x2, ..., xm of panel 1
The clock is supplied and counted at the timing when x'is supplied, and the operation is stopped at the timing when the output signal of the AND circuit 8 becomes the high level "1". Therefore, from the column coordinate detection unit 11, a count value corresponding to an arbitrary position of the panel 1 with which the pen 5 is in contact is obtained as a column coordinate output.

FIG. 7 is a diagram showing a specific configuration of the embodiment. In FIG. 7, parts corresponding to those in FIG. 1 are designated by the same reference numerals.

In the figure, 21 is the row electrodes y1, y2, ..., Y of panel 1.
a shift register having a number of stages corresponding to the number of electrodes of n, 22
Is a driver having AND circuits 2A1 to 2An, exclusive NOR circuits 2E1 to 2En, N channel FETs 2N1 to 2Nn and P channel FETs 2P1 to 2Pn corresponding to the number of electrodes, and 23 is a power source V _{W +} (+ 215V), ground (0V) and Power supply 1 / 2VD (+25
Changeover switch for switching V), 24 is the power supply V _W- (−16
It is a changeover switch for switching between 5V) and ground (0V). The shift register 21, the driver 22, and the changeover switches 23 and 24 constitute the row electrode driver 2.

That is, the output terminals of the n stages of the shift register 21 are respectively connected to the input sides of the AND circuits 2A1 to 2An of the driver 22, and the output sides of the AND circuits 2A1 to 2An are connected to the input sides of the exclusive NOR circuits 2E1 to 2En, respectively. The output side of the exclusive NOR circuits 2E1 to 2En are connected to the gates of the N-channel FETs 2N1 to 2Nn, respectively, and
It is connected to the gates of P-channel FETs 2P1 to 2Pn.

The sources of the P-channel FETs 2P1 to 2Pn are connected to the movable terminals of the changeover switch 23, respectively.
The fixed terminal on the side a is connected to the power supply V _{W +} , the fixed terminal on the side b is grounded, and the fixed terminal on the side c is connected to the power supply 1 / 2VD. The switching of the changeover switch 23 is controlled by the timing generation circuit 4.

The sources of the N-channel FETs 2N1 to 2Nn are connected to the movable terminals of the changeover switch 24, respectively. This changeover switch
The fixed terminal on the a side of 24 is connected to the power supply V _W-, and the fixed terminal on the b side is grounded. The switching of the changeover switch 24 is controlled by the timing generation circuit 4.

The drains of the N-channel FETs 2N1 to 2Nn are connected to the drains of the P-channel FETs 2P1 to 2Pn, respectively, and the respective connection points are connected to the row electrodes y1, y2, ..., Yn of the panel 1. N channel FETs 2N1 to 2Nn, P channel F
Diodes are connected between the drains and sources of the ET2P1 to 2Pn.

In this case, in the display mode, the timing generation circuit 4 enables the AND signals 2A1 to 2An to the enable signals (see C and Q in FIG.
Is shown as enable). Then, in a certain frame, the changeover switch 23 is connected to the a side, the power source V _{W +} is supplied to the sources of the P-channel FETs 2P1 to 2Pn (shown in FIG. 8E), and the changeover switch 24 is connected to the b side to N. The sources of the channel FETs 2N1 to 2Nn are grounded (shown in FIG. 8F), and the inverting / non-inverting control signals (shown as y inverting / non-inverting in FIG. 8D) supplied to the exclusive NOR circuits 2E1 to 2En are low. Level 0. On the other hand, in the next frame, the changeover switch 23 is connected to the b side and the P channel FE
The sources of T2P1 to 2Pn are grounded (shown in FIG. 8E), the changeover switch 24 is connected to the a side, and N-channel FETs 2N1 to 2N are connected.
The power source V _W- is connected to the source of n (shown in FIG. 8F), and the inverting / non-inverting control signal is set to the high level “1”.

Further, the timing generating circuit 4 supplies the scan register Py data (illustrated as y data in FIG. 8A) to the shift register 21 and the clock (illustrated as y clock in FIG. 8B, N). To be done. As the data for the scan pulse Py, since the row electrodes y1, y2, ..., Yn are sequentially scanned one by one, the high level “1” continues for one clock.

Therefore, in a certain frame, P-channel FETs 2P1 to 2P
A low level "0" signal is sequentially supplied to the gates of n to be turned on, and the row electrodes y1, y2, ..., Yn of the panel 1 are sequentially supplied with the power supply V _{W +} as a scanning pulse Py on an electrode-by-electrode basis. To be done. In the next frame, a high level “1” signal is sequentially supplied to the gates of the N-channel FETs 2N1 to 2Nn to turn them on,
Scan pulse Py is applied to the row electrodes y1, y2, ..., Yn of panel 1.
As a result, the power supply V _W- is sequentially supplied for each electrode.

In the row coordinate detection mode, the timing generation circuit 4
The AND circuits 2A1 to 2An are supplied with enable signals (shown as y-enable in FIG. 8C). The change-over switch 23 is connected to the c side to connect the P-channel FETs 2P1 to 2Pn.
1 / 2VD power is supplied to the source of (as shown in Fig. 8E),
The changeover switch 24 is connected to the b side and connected to the N-channel FET 2N1.
The source of 2Nn is grounded (shown in FIG. 8F), and the inverted / non-inverted control signal (shown as inverted / non-inverted in FIG. 8D) supplied to the exclusive NOR circuits 2E1 to 2En is low level “0”. It is said that

Further, the timing generating circuit 4 supplies the shift register 21 with data for the scanning pulse Py '(shown as y data in FIG. 8A) and a clock (shown as y clock in FIG. 8B). It The data for this scan pulse Py ′ is a high level “1” for 20 clocks because a plurality of adjacent electrodes, for example, 20 electrodes of the row electrodes y1, y2, ..., Yn are simultaneously scanned. To be continued.

Therefore, two adjacent P-channel FETs 2P1 to 2Pn
A low level "0" signal is simultaneously supplied to 0 gates to be turned on, and the scan pulse Py 'is simultaneously applied to 20 adjacent electrodes of the row electrodes y1, y2, ..., Yn of the panel 1. The power source 1 / 2VD is supplied as, and scanning is performed sequentially in this state.

In the column coordinate detection mode, the timing generation circuit 4
The enable signal (illustrated as y-enable in FIG. 8C) supplied to the AND circuits 2A1 to 2An is at the low level "0".
It is said that The changeover switch 23 is connected to the b side, and the sources of the P-channel FETs 2P1 to 2Pn are grounded (see FIG. 8E).
, And the sources of the N-channel FETs 2N1 to 2Nn are grounded (shown in FIG. 8F), and the inversion / non-inversion control signal is at low level "0".
Therefore, a high level "1" signal is supplied to the gates of the N-channel FETs 2N1 to 2Nn to turn them on, and the row electrodes y1, y2, ..., Yn of the panel 1 are all grounded.

Further, 31 is a shift register having a number of stages corresponding to the number of electrodes of the column electrodes x1, x2, ..., Xm of the panel 1, 32 is a latch circuit having a number of stages corresponding to the number of electrodes, and 33 is the number of electrodes thereof. Corresponding to the NAND circuit 3A1 to 3Am, N channel FET3N1 to
A driver having 3Nm and P-channel FETs 3P1 to 3Pm,
Reference numeral 34 is a variable power supply circuit, and the shift register 31, the latch circuit 32, the driver 33, and the variable power supply circuit 34 constitute the column electrode driver 3.

That is, the output terminals of the m stages of the shift register 31 are respectively connected to the NAND circuit 3A1 of the driver 33 via the latch circuit 32.
.About.3Am input side, and the output sides of the NAND circuits 3A1 to 3Am are connected to the gates of the N-channel FETs 3N1 to 3Nm and the gates of the P-channel FETs 3P1 to 3Pm, respectively.

The sources of the P-channel FETs 3P1 to 3Pm are the variable power supply circuit 3
4 is connected to the output side, and the variable power circuit 34 has an input side connected to the power supply 1 / 2VD. The variable power supply circuit 34 is controlled by the timing generation circuit 4, and VD is set in the display mode.
Is output, and 1 / 2VD is output in the coordinate detection mode (illustrated in FIG. 8K). The sources of the N-channel FETs 3N1 to 3Nm are grounded.

The drains of the P-channel FETs 3P1 to 3Pm are connected to the drains of the N-channel FETs 3N1 to 3Nm, respectively, and their connection points are connected to the column electrodes x1, x2, ..., Xm of the panel 1. N channel FETs 3N1 to 3Nm, P channel F
A diode is connected between each drain and source of ET3P1 to 3Pm. In this case, in the display mode, the timing generation circuit 4 supplies the enable signals (illustrated as x enable in FIGS. 8A and 8B) to the NAND circuits 3A1 to 3Am.

Further, the timing generator circuit 4 supplies data to the shift register 31 (shown as x data in FIG. 8H and O), and also supplies a clock to the shift register 31 (x to x in FIG. 8I and P).
(Illustrated as a clock) is supplied. In this case, the row electrode
In one frame in which the power V _{W +} is supplied as the scan pulse Py to y1, y2, ..., Yn, the inverted data of the display data SD is supplied, while the power V _W- is supplied as the scan pulse Py. In the next frame, the display data SD is supplied as it is.

Then, the data is sequentially supplied to the shift register 31
Each time m pieces of data for a scanning line are set, a load signal (see FIG. 8) is sent from the timing generation circuit 4 to the latch circuit 32.
L data are supplied as x loads to L and N, m data for one scanning line are latched by the latch circuit 32, and m data are sequentially supplied to the shift register 31.
It is held for the scan line period. As a result, a sufficient period for EL emission, for example, about 40 μsec is secured.

Therefore, in a certain frame in which the power supply V _{W +} is supplied to the row electrodes y1, y2, ..., Yn as the scanning pulse Py, the gate of one of the N-channel FETs 3N1 to 3Nm corresponding to the display pixel portion is provided for each scanning line. A high level “1” signal is supplied to turn on, and a low level “0” signal is supplied to the gate of one of the P-channel FETs 3P1 to 3Pm corresponding to the non-display pixel section to turn on. 1 column electrode x1, x2, ...
The electrode corresponding to the display pixel portion of xm is grounded, and the voltage VD is supplied to the electrode corresponding to the non-display pixel portion.

On the other hand, the power supply V _W- next frame is supplied as a scanning pulse Py, 1 to the gate of a corresponding one to the display pixel portion of the P-channel FET3P1~3Pm every scanning line is supplied with a signal of low level "0" When turned on, N-channel FET3
A high level “1” signal is supplied to the gate of one of N1 to 3Nm corresponding to the non-display pixel portion to turn it on, and the panel 1
, Xm of the column electrodes x1, x2, ..., Xm are supplied with the voltage VD, and the electrodes corresponding to the non-display pixel portion are grounded.

In the row coordinate detection mode, the timing generation circuit 4
The enable signal (shown as x-enable in FIG. 8J) supplied to the NAND circuits 3A1 to 3Am is low level "0".
It is said that Therefore, a high level "1" signal is supplied to the gates of the N-channel FETs 3N1 to 3Nm to turn them on, and all the column electrodes of the panel 1 are grounded.

In the column coordinate detection mode, the timing generation circuit 4
The enable signals (shown as x-enable in FIG. 8J) are supplied from the NAND circuits 3A1 to 3Am. Then, the timing generator circuit 4 causes the shift register 31 to scan pulse P
Data for x '(shown as x data in FIG. 8H) is supplied, and a clock (shown as x clock in FIG. 8I) is supplied. The data for this scan pulse Px ′ is a plurality of adjacent column electrodes x1, x2, ..., Xm,
For example, since 20 electrodes are simultaneously scanned, the high level “1” is set to continue for 20 clocks. The load signal (shown as x load in FIG. 8L) is continuously supplied from the timing generation circuit 4 to the latch circuit 32, and the latch circuit 32 is set to the through mode.

Therefore, two adjacent P-channel FETs 3P1 to 3Pm
A low level “0” signal is supplied to 0 gates at the same time to turn on, and a scan pulse Px ′ is simultaneously applied to 20 adjacent electrodes of the column electrodes x1, x2, ..., Xm of the panel 1. A voltage of 1/2 VD is supplied and scanning is performed sequentially in this state.

Thus, in the display mode, the row electrodes y1, y2, ..., yn
Is sequentially supplied with a scanning pulse Py in units of one electrode,
A voltage corresponding to the display data SD is simultaneously supplied to the column electrodes x1, x2, ..., Xm for each scanning line, and display driving is performed by line-sequential scanning, and an image corresponding to the display data SD is displayed.

Further, the detection signal of the pen 5 is supplied to the amplifier 6, the detection signal vs from the amplifier 6 is supplied to the comparator 7 and the peak time point detection circuit 9, and the respective output signals are supplied to the AND circuit 8. Then, from the AND circuit 8, the detection signal vs is larger than the reference voltage Vr, and
A high level “1” signal is output at the peak of vs, and a low level “0” signal is output at other times.

The output signal of the AND circuit 8 is supplied as a count stop signal to the row coordinate detecting unit 10 and the column coordinate detecting unit 11 which are composed of counters.

Then, the same clock as the clock supplied to the shift register 21 (illustrated as y clock in FIG. 8B) is supplied from the timing generation circuit 4 to the row coordinate detecting unit 10 and the reset signal (G in FIG. 8G). Is supplied as y-counter reset) to be reset before the row coordinate detection mode is entered. Therefore, when the row coordinate detection mode is entered, the clock counting operation starts and the detection signal
The counting operation ends when vs is greater than the reference voltage Vr and the detection signal vs peaks, and the row coordinate detection unit 10 outputs a count value corresponding to an arbitrary position on the panel 1 with which the pen 5 is in contact as a row coordinate output. can get.

Further, the same clock as the clock supplied to the shift register 31 (illustrated as x clock in FIG. 8I) is supplied from the timing generation circuit 4 to the column coordinate detection unit 11, and a reset signal (M in FIG. 8) is also supplied. Is supplied as x counter reset) to be reset before entering the column coordinate detection mode. Therefore, when the column coordinate detection mode is entered, the clock counting operation starts and the detection signal vs.
Is larger than the reference voltage Vr and the counting operation ends at the peak time of the detection signal vs, and the column coordinate detecting section 8 obtains a count value corresponding to an arbitrary position of the panel 1 with which the pen 5 is in contact as a column coordinate output. To be

In FIG. 7, 4a is a RAM in which the display data SD is written.

As described above, according to this example, when the pen (pencil-shaped conductor) 5 is brought close to the glass surface of the panel 1, the output signal of the comparator 7 becomes a high level “1”, and the AND circuit 8 causes the row coordinate detector 10, Since the count stop signal is supplied to the column coordinate detection unit 11 and the coordinate detection operation is automatically started, by pressing the pen tip against the display as in the conventional case, the mechanical switch built in the pen is turned on to start the coordinate detection operation. It is easier to operate than the ones. Further, since the pen 5 does not require a mechanical switch, the number of parts is small and the pen 5 can be constructed at low cost. Further, since the pen 5 has no moving parts such as a mechanical switch, there is no fear of the pen 5 breaking down.

Further, since the panel 1 is used for both display and coordinate detection, the display surface of the display and the input surface of the tablet are surely aligned with the accuracy of one display pixel over the entire surface, so that the panel can be easily manufactured. it can.

Further, since the panel 1 is used in both the display mode and the coordinate detection mode, and the row electrode driver 2 and the column electrode driver 3 are commonly used, it is possible to omit a wasteful circuit,
It can be constructed at low cost and can be advantageous in terms of space.

Further, since the display mode period and the coordinate detection mode period are alternately provided in a time division manner, during the coordinate detection mode period, the scan pulse Py ′ is not affected by the interference signals due to various signals necessary for display driving. , Px ′ can be detected,
Coordinates can be detected well.

Further, in the coordinate detection mode, a plurality of adjacent lines, for example,
Since the scanning is sequentially performed while the scanning pulses Py ′ and Px ′ are supplied to 20 electrodes at the same time, the level of the detection signal of the pen 5 increases and the detection of the scanning pulses Py ′ and Px ′ becomes easy and the coordinates are The detection can be performed well.

Unlike the above-described embodiment, as shown in FIG. 9, the display 51 and the tablet 52 are formed independently of each other, and the tablet 52, which is integrally formed by bringing them into close contact with each other, has the same structure. Of course, the invention is likewise applicable.

As described above, according to the present invention, at least one of the row electrode and the column electrode of the panel is supplied with the scanning pulse having the same pulse width sequentially delayed by a phase shorter than the pulse width. That is, since the scanning pulses are supplied to a plurality of adjacent electrodes while partially overlapping with each other, the level of the detection signal of the detection conductor is increased, the detection of the scanning pulse is facilitated, and the coordinate detection is performed well. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 to 6 are diagrams for explaining the operation thereof, FIG. 7 is a concrete block diagram of the example of FIG. 1, and FIG. 8 is its operation. FIG. 9 is a block diagram of a conventional example for explanation. 1 ... Thin film EL matrix panel 2 ... Row electrode driver 3 ... Column electrode driver 4 ... Timing generation circuit 5 ... Pencil-shaped conductor 7 ... Comparator 8 ... AND circuit 9 ... Peak point detection circuit 10 ... Row coordinate detector 11 ... Column coordinate detector

Claims (1)

[Claims] 1. A matrix panel, a row electrode driver, a column electrode driver, a row coordinate detecting section, a column coordinate detecting section, and a detecting conductor, wherein the row electrode driver sequentially supplies the row electrodes of the panel. The scanning pulse supplied is detected by the detection conductor and is supplied to the row electrode coordinate detection unit to detect the row coordinates, and the scanning is sequentially supplied from the column electrode driver to the column electrodes of the panel. In the tablet in which the column coordinates are detected by the pulse being detected by the detection conductor and being supplied to the column coordinate detection unit, at least one of the row electrode and the column electrode of the panel is
A tablet characterized in that scanning pulses having the same pulse width are sequentially delayed by a phase shorter than the pulse width from corresponding electrode drivers.