JPH0766970B2 - MOSFET device - Google Patents

Description

The present invention relates to a MOSFET device, and more particularly to a MOSFET device capable of obtaining a desired functional Id-Vd characteristic.

(Prior Art) MOSFET drain current is a function of gate voltage and drain voltage. This relationship is a quadratic function of the drain voltage in the non-saturation region, is constant regardless of the drain voltage in the saturation region, and its function form is fixed.
Therefore, in the conventional MOSFET device design, the coefficient for the entire function that determines the current is set, and the functional form of the Id-Vd characteristic cannot be changed. Also, the Id of the desired function form
There was no MOSFET with -Id characteristics.

On the other hand, the function generator has been used when analyzing a function generator or a non-linear system by an analog computer, but its application as an element of a fuzzy computer is drawing attention. In other words, in the 1980s, the practical application of fuzzy control began, but since conventional Digil computers are not suitable for processing fuzzy information, they process fuzzy information efficiently and at high speed, and consume less power. There is a demand for the development of a computer dedicated to fuzzy control. Therefore, an IC that incorporates various membership functions that describe fuzzy sets
And if there is an IC that processes fuzzy logic, it can be easily done by processing a fuzzy set with a conventional digital computer.

On the other hand, various function generators are required to process fuzzy logic. In the current technology, a function generator approximates a non-linear function with a broken line and is configured by using a diode, a resistance constant voltage source, and a constant current source.

(Problem to be Solved by the Invention) A function generator including various elements such as a diode, a resistor, and a constant current source has a drawback that the number of components is too large. In particular, a large number of elements are required to improve the accuracy. On the other hand, by using the integrated circuit manufacturing technology, the geometric pattern of the electrode region can be set to a desired shape.

Therefore, an object of the present invention is to provide a MOSFET device in which a desired functional Id-Vd characteristic can be obtained by appropriately setting the pattern shape of each electrode region.

(Means for Solving the Problems) A MOSFET device according to the present invention includes a semiconductor substrate of one conductivity type, a source region of opposite conductivity type, a drain region of opposite conductivity type, electrodes of these regions, and the source region. In a MOSFET device comprising a channel region located between the drain region and a gate electrode separated from the channel region by an insulating layer, a drain side end of the gate electrode is formed during operation. It is characterized in that it is formed in a step shape along a direction orthogonal to the extending direction and outputs a drain current that changes stepwise according to the drain voltage.

(Operation) When the drain-side end of the gate electrode does not overlap with the drain region through the insulating layer (in the present specification, this non-overlapping portion is referred to as a “gap region”), the gap region Inversion layer is not formed on
Therefore, no channel is formed. On the other hand, since a pn junction is formed on the peripheral edge of the drain region, a depletion layer is formed on the peripheral edge of the drain region. This depletion layer expands as the drain voltage increases, and gradually expands so as to extend to the gate electrode side at the end portion on the gate electrode side. When the edge of the depletion layer spreads to just below the edge of the gate electrode, the drain depletion layer functions as a drain for carriers, and as a result, the channel also exists in the gap area. Will be formed. Therefore, if a gap area having a varying distance is formed between the gate electrode and the drain region, the channel width gradually increases as the drain voltage gradually increases, and thus the drain current increases. The form in which the drain current increases substantially corresponds to the gap shape. For example, if a gap portion in which the gap length changes stepwise is formed, the drain shape increases stepwise as shown in FIG. 2 as the drain voltage increases. Current Id is formed,
If you create a gap where the gap length changes linearly,
An almost linearly increasing drain current is obtained. The present invention is based on such recognition, and an object of the present invention is to provide a MOSFET device in which a gap shape and an impurity concentration of a substrate are appropriately set and a desired function-type output characteristic is obtained. Therefore, according to the present invention, by appropriately designing the gap between the gate electrode and the drain region, it is possible to realize a function generator having a desired function by using only one FET device.

(Embodiment) FIG. 1 shows a structure of an example of a MOSFET device according to the present invention. FIG. 1A is a plan view, FIG. 1B is a sectional view taken along line I-I, and FIG. 1C. Is a cross-sectional view taken along line II-II, No. 1
FIG. D is a schematic plan view. In this example, a design example of a P-channel MOSFET that outputs a stepwise drain current will be described. Using the n-type substrate 1, P by boron diffusion
The source region 2 and the drain region 3 of the shape are formed. Therefore, a pn junction and a depletion layer are formed at the peripheral edge of the drain region in contact with the n-type region. The source region 2 and the drain region 3 are formed in a rectangular shape, and a p channel is formed between the source region 2 and the drain region 3. An insulating layer 4 made of SiO ₂ is formed on the surface of the substrate 1, and a gate electrode 5 is formed on a portion of the insulating layer 4 where a channel is formed.
Further, the source electrode 6 and the drain electrode 7 are formed on the portions of the insulating layer 4 corresponding to the source and drain regions, respectively. As shown in FIG. 1A, the end portion of the source region 2 on the gate electrode 5 side and the end portion of the gate electrode 5 on the source region 2 side are formed so as to overlap each other with the insulating layer 4 sandwiched therebetween. On the other hand, the end of the gate electrode 5 on the drain side is shown in FIG.
As shown in FIG. 3, the stepped portion 5a is formed stepwise so as to sequentially approach the drain region 3 along the direction orthogonal to the channel, and only the stepped portion 5a overlaps the drain region 3 through the insulating layer 4, and the remaining two stepped portions are formed. 5b and 5c are formed so as not to overlap the drain region and form a gap area. Figure 1d
As shown in, the widths of the steps 5a to 5c in the direction orthogonal to the channel are W ₁ , W ₂ and W ₃ , respectively, and the gap lengths of the steps 5b and 5c (from the gate electrode end to the end of the drain region). Distance) is set to l ₂ and l ₃ .

FIG. 2 is a schematic graph showing Id-Vd characteristics of the MOSFET device shown in FIG. The horizontal axis shows the drain voltage (Vd),
The vertical axis represents the drain current (Id). These Vd and Id
Is a relative value. The pn junction is treated as a staircase junction. When an appropriate gate bias is applied to the gate electrode and the drain voltage Vd is gradually increased, Id also gradually increases and reaches the first saturation region. At this time, Vd is still low, so the stairs
The depletion layer 8 formed in the areas 5b and 5c does not spread to just below the gate electrode 5, a channel is formed only in the step portion 5a, and a drain current corresponding to the width W ₁ flows. Further, Vd increases, the depletion layer 8 of the staircase portion 5b spreads to just below the gate electrode 5, a channel is formed also in this gap region, and a drain current corresponding to (W ₁ + W ₂ ) flows.
Further, when the drain voltage is increased, the depletion layer formed in the staircase portion 5c expands, a channel is also formed in this gap area, and a drain current corresponding to (W ₁ + W ₂ + W ₃ ) flows. In this way, the drain current that changes stepwise in three steps can be output only by forming three gap areas having different gap lengths.

FIG. 3 shows a reference example for explaining the present invention, and FIG. 3a is a schematic plan view showing the constitution of each region, and FIG.
FIG. B is a graph showing measured values of Id-Vd characteristics. In this example, p-channel MOSF whose drain current increases almost linearly
A design example of the ET device will be described. A rectangular p-type source region 10 and a rectangular p-type drain region 11 are formed on an n-type substrate, and a gate electrode 12 is formed between these regions via an insulating layer. The gate electrode is overlapped with the source region at the end portion on the source side. On the other hand, at the drain-side end, the edge is angle φ with respect to the gate-side edge of the drain region 11.
= It is formed in a straight line inclined by 13 °. Then, the gate electrode is overlapped with the drain region in the lower area on the drawing. Therefore, the gap area 12 in which the gap length changes linearly is formed between the gate electrode and the drain region. In FIG. 3b, the solid line shows the Id-Vd characteristics of the above-mentioned configuration, and the broken line shows the measured value measured by exchanging the source and drain. When a gap is formed between the gate electrode and the drain region, the drain current increases almost linearly with the increase of the drain voltage in the range of the gate voltage V _G of −12V to −20V. On the other hand, when a gap is formed between the source region and the gate electrode, the saturation value is reached when the drain voltage increases. From this measurement result, it can be understood that the extension of the depletion layer in the gap region formed between the gate electrode and the drain region strongly contributes to the Id-Vd characteristics.

FIG. 4 shows a MOSFET reference example of the present invention.
FIG. 4A is a schematic plan view showing the shapes of the source and drain regions and the gate electrode, and FIG. 4B is the measured value of the Id-Vd characteristic thereof. In this example, a design example in which Id increases almost in proportion to Vd is shown.

In order to realize the proportional characteristic, the source and drain regions may be formed by a pn step junction on a substrate having a low impurity concentration, the gate width may be extended in proportion to Vd, and the channel length may be in inverse proportion to the gate width.

First, the source region is formed in a rectangular shape, and the end of the source region is made parallel to the X axis so that the channel length in the Y axis direction is inversely proportional to the gate width. Next, consider a drain in which the drain end of the gate is moved in parallel. Consider a group of n translation curves that recede toward the gap side at equal intervals. In this example, for simplicity, this is shown by a group of four parallel-moving parallel movement curves. Here, n is equally divided in the gate width direction at equal intervals perpendicular to the source / gate end, and the intersections are connected to the left and right outside in n steps. In this way, a gate width proportional to the gap and a gate length inversely proportional to the gate width can be obtained. Since this gate length is integrated with the gate width, the square of the gate width, that is, the square of the gap characteristic can be obtained.
In the case of the step junction, as a result, the Id-Vd characteristic almost proportional to the drain voltage shown in FIG. 4B was obtained.

FIG. 5 also shows a reference example for explaining the present invention. In this example, the gate electrode 32 is formed with a wedge-shaped recess on both the source and drain sides, and the source region 30 and the drain region 31 are formed in a wedge shape. The wedge angle of the source and drain regions was 2θ = 53 °. The angle of the gap formed between the gate electrode and the drain region is 13 °. The minimum channel length between the tip of the source and drain regions is 50 μm
Is. In the FET having such a structure, three FET devices in which the tip of the drain region penetrates under the gate electrode were manufactured, and the Id-Vd characteristics thereof were measured. Penetration amount is 0μ
m, 10 μm and 20 μm, and the measured results are shown in FIG.
Each is shown in c. The solid line shows the calculation result, and the broken line shows the measured value. As is clear from FIGS. 6A to 6C, Id does not reach saturation even when Vd increases in all three FETs, and Id increases as Vd increases. Further, as the amount of penetration of the tip of the drain region increases, the drain current also increases and tends to approach saturation. It is considered that the fact that the change in the increase in current is larger than the calculated value when the drain voltage is low is attributed to the larger spread of the depletion layer in the case of the low-concentration substrate. Therefore, the use of the low-concentration substrate has an advantage that the clearance during manufacture can be set wider.

7a and 7b are schematic plan views showing reference examples for understanding the present invention. FIG. 7a shows an example in which a gate electrode having a circular drain side end is formed between the source region 40 and the drain region 41. The drain end of the gate electrode may be formed in an elliptical shape. In the embodiment shown in FIG. 7b, the source region 50 is rectangular, the drain region 51 is formed with a wedge-shaped recess, and the drain end of the gate electrode 52 is formed in a wedge shape.

Next, to explain the simulation results of characteristics, we attempted the model calculation of MOSFET in which the depletion region expands and the gate width changes, based on the conventional theory of impurity atom thermal diffusion and the theory of operation of MOSFET. Here, the electric field dependence (2) of the mobility μ in the gradient channel approximation (1) is considered as the model of the MOSFET.

At Vd <(Vg-Vt), Id = μCo × (W / L) {Vg-Vt) Vd−Vd × Vd / 2 (1) μ = μo / [{1 + θ (Vg-Vt)} × {1 + Vd / L) (μo / Vsat)}] (2) Here, in the case of Vd <(Vg−Vt), Vg = Vg−Vt in equations (8) and (9). Vsat is a parameter and corresponds to the saturation speed.

(W / L) of the equation (1); the relationship in which the aspect ratio depends on the drain voltage can be calculated as follows. In the gap region, the drain voltage Vg is entirely added to the depletion region, but in the back gate region, only the pinch-off region where the potential from the drain is (Vg-Vt) or higher is the depletion region. Therefore, the potential difference in the depletion region is {Vd− (Vg−
Vt)}, which is smaller than the gap region, and the thickness d of the pinch-off depletion region becomes narrower as the gate voltage increases. On the other hand, the depletion layer in the gap region is formed with the potential difference Vd. The thickness d of the depletion region also depends on the impurity ion density N distribution of the substrate. The impurity ion concentration distribution changes near the drain boundary.

Here, for simplification, consider a) graded joining and b) staircase joining.

a) Gradient coupling; Impurity ion distribution in metallurgical transition region
If [atoms / cm ³ / cm] is set, the thickness D of the depletion layer is given by the equation (3).

Here, when Vd>, the thickness d of the depletion layer on the gap side can be approximated by the equation (4).

b) staircase junction; impurity ion distribution in the p and n regions (Na>
If the staircase junction is approximated as Nd), the thickness D of the depletion region is (1
Given in 2).

Here, when Vd> φ and Na> Nf = N, the thickness d of the depletion layer can be approximated by the equation (13).

If the depletion layer extends from the metallurgical transition region of the pn junction to the substrate region, its thickness is Vd (3 /
2) Power: {1/2] of Vd in constant concentration area from {(4)}
Power: It can be approximated by changing to {(3)} on the way.

Next, the shape of the gap is considered. When the gap between the gate electrode and the drain has a wedge angle ψ, the drain end of the gate electrode is enlarged by the equation (7).

Δd = d / sin ψ = d / sin 13 ° = 4.45 × d (7) When this gate electrode is a FET with a wedge-shaped angle 2 of 2 = 2 (ψ + θ) = 2 × 39.5 as shown in FIG. Shows that the width W of the gate is given by the equation (8) and the channel length is extended only in the drain portion, and can be approximated by the equation (9).

_{W = W 0 + 2 * Δd} * sin = W 0 + 2 * Δd * sin39.5 ° = W 0 + 1.2721Δd (8) (L> Lo, W> when the Wo) L = Lo + Δd * sin = Lo + 0.7716Δd ( 9) (When L <Lo, W <Wo) L = Lo-Wo / tan θ = Lo-2.0057Wo (10) Here, the increased gate width is equally divided into n pieces, and the increased wedge-type MOSFET is existing. When the increase ratio Δ (W / L) eq of the FET channel aspect ratio is calculated as When Σ in equation (11) is calculated by integration, L = Lo + (W−Wo) / (2 × tan) Δ (W / L) eq = (2 × tan) × [I _n {(W−Wo) + 2 × tan} −I _n {2 * Lotan}] (13) (W−Wo) / (2 × tan} When <1, using the inversion formula In (1 × X) = X−X × X / 2 of Δ (W / L) eq to (2 × tan) × [(W−Wo) / 2 × tan
}] × [1- (W−Wo) / {4 × Lotan}] = {(W−W
o) / Lo} x [1- (W-Wo) / {4 x Lotan}] (14) On the other hand, assuming the average channel of ΔL to be ΔL / 2, calculate the aspect ratio (W / L) eq of the increased channel. Then Δ (W / L) eq ~ (2 × tan) × {Lo + (Δd) × (cos
) / 2} = {(W-Wo) / Lo} [1 / {1+ (L-Lo) / (2 × L
o)}] = {(W-Wo) / Lo} [1 / {1- (L-Lo) / (2 × L
o)}] Equations (15) and (15) are obtained, which coincides with Equation (14). If ψ is set to a small value, the characteristics of the MOSFET will be greatly characterized.

We simulated the wedge-shaped gap MOCFET prototyped using Eq. (12). The impurity concentration profile of the MOS interface may differ from that of the bulk because the atomic state is different from that of the bulk inside the semiconductor.However, when the concentration profile is calculated from the theory of thermal diffusion of impurity atoms in the bulk, the doped acceptor Density of the substrate is 10 + 15 [atoms / c
The position of the pn boundary that is equal to the donor density of [m ³ ] is 3.
It is 6 μm, and the position where the concentration becomes 1/100 is 4.3 μm. The density change at the interval of 0.7 μm has a Gaussian distribution.

On the other hand, when the thickness of the depletion layer formed on a substrate with a uniform donor density is calculated using equation (13), when the drain voltage is higher than the threshold voltage, the impurity concentration is in the constant range from the gradient concentration. In consideration of the compensation effect on, the impurity ion concentration is fixed at a value of 80%: N = 8 × 10 + 14 [atoms / cm ³ ] and based on the depletion layer formula (6) and the aspect ratio formula (12). The calculated results are shown by the solid lines in Figures 6, a, b, and c.

In this simulation, since the drain electric field dependence of the mobility related to the channel length does not change so much,
For simplicity, the value in the saturation region, that is, Vd = Vg−Vt, is approximated.

Further, the wedge-shaped source / drain MOSFET portion formed by overlapping the gate electrode and the boron diffusion has the aspect ratio of the MOSFET equivalent to the ratio of the average channel length and the gate width. Calculation is gate oxide film thickness 750Å, Shikiichi voltage V
t = 2.5V, gate width and length initial channel μm
A): Wo = 9; Lo = 62.b): Wo = 24; Lo = 6
5.c): 51; Lo = 71.

This simulation (solid line) almost agrees with the measurement result (score). The large measured current near the non-saturation region is due to the impurity concentration of the drain pn junction region, and in reality, the impurity ions are compensated and the depletion region is formed with a low concentration and a low voltage. Measurement results The gate voltage dependence of Fig. 5 shows that the gate voltage also contributes to the formation of the drain depletion layer, and the surface impurity concentration also changes.

This impurity atom concentration distribution can be artificially controlled.

As described above, according to the present invention, since the drain side end of the gate electrode is formed stepwise along the direction orthogonal to the channel direction, Id that changes in a desired step shape
A −Vd characteristic can be realized. As a result, one MO
A SFET device can represent a function generator that can produce a desired function output.

[Brief description of drawings]

1A to 1D are schematic plan views showing a first embodiment of a MOSFET device according to the present invention, a sectional view taken along the line I-I, a sectional view taken along the line II-II,
And a schematic plan view, FIG. 2 is a graph showing Id-Id characteristics of the MOSFET device of the first embodiment, FIG. 3 is a schematic plan view of a MOSFET device of the reference example, and a graph showing output characteristics, FIG. And b are schematic plan views showing the configuration of the MOS of the reference example and graphs showing the output characteristics, FIG. 5 is a schematic plan view showing the configuration of the MOSFET device of the reference example, and FIGS. A graph showing the output characteristics when the drain region of the MOSFET device of the example is moved to the gate side by 0 μm, 10 μm, and 20 μm, respectively. It is a schematic plan view. DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Source region 3 ... Drain region, 4 ... Insulating layer 5 ... Gate electrode, 6 ... Source electrode 7 ... Drain electrode, 8 ... Depletion layer 9 ... Inversion layer

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, a source region of opposite conductivity type, a drain region of opposite conductivity type, electrodes of these regions, and a channel region located between the source region and the drain region. A MOSFET device comprising a gate electrode separated from the channel region by an insulating layer, the drain-side end of the gate electrode being along a direction orthogonal to an extending direction of a channel formed during operation. It is characterized in that it is formed in a staircase shape, and is configured to output a drain current that changes stepwise according to the drain voltage.
MOSFET device.