JPH0766806A - Atm switch - Google Patents

Abstract

PURPOSE:To avoid the limit of a transfer rate based on a difference from a wiring length by reading cells from an input buffer in a timing in response to the wiring length difference and taking bit synchronization for each output line. CONSTITUTION:Cells inputted from input lines 101-104 are stored in input buffers 21-24. A cell read timing generating circuit 1 generates a read timing and transfers it to the buffers 21-24 via signal lines 61-64. The buffers 21-24 send cells at their own period and cells are sent among the adjacent buffers 21-24 at a deviated time. An operating timing of each switch in cross points 511-544 is set in following to or synchronously with the circuit 1. A cell is transferred in a switch network 50 without bit synchronization and inputted to bit synchronization circuits 301-304, in which synchronization is taken. The circuits 301-304 uses plural or one clock with a predetermined frequency from signal lines 401-404 to take bit synchronization of cells from signal lines 111-114 and output cells after bit synchronization to output lines 201-204.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a switching device for digital communication. In particular, it relates to a technique for increasing the speed of an ATM (asynchronous transfer mode) switching device.

[0002]

2. Description of the Related Art A conventional example will be described with reference to FIG. FIG. 12 is a block diagram of a conventional device. Input line 1
The cells input from 01 to 104 are input to the bit synchronization circuits 711 to 744 at each cross point passage to be bit synchronized and output from the output lines 201 to 204. At this time, it is necessary to distribute a clock in consideration of the cell transit time to each cross point.

In the case of the clock distribution line shown in FIG. 12, the most upstream crosspoint 511 and the most downstream crosspoint 54.
Inevitably, a delay time m of 1 and 1 occurs. Therefore, the upper limit of the cell transfer rate in the switch network 50 is 1 / m [Hz].

[0004]

As described above, the conventional A
In the TM switch, the distribution line length of the clock limits the maximum speed of the transferred cells. In this conventional example, 1 /
To achieve a cell transfer rate exceeding m [Hz],
It is necessary to carefully design the wiring.

The present invention has been made against such a background, and an object of the present invention is to provide an ATM switch capable of avoiding the limitation of the cell transfer rate in the switch network due to the difference in wiring length and achieving high-speed cell transfer. And

[0006]

According to the present invention, a plurality of N input lines and a plurality of M output lines are accommodated, and cells input from the N input lines are transferred to the M input lines according to their header information. It is an ATM switch equipped with a switch network that is switch-connected to an output line of a book.

Here, a feature of the present invention is that an input buffer circuit for temporarily accumulating cells arriving at each of the N input lines is provided, and cell read timing for controlling the read timing of this input buffer circuit. A generator circuit is provided, and the M output lines are each provided with an independent bit synchronization circuit that operates according to cells coming from the switch network.

It is preferable that the cell read timing generation circuit includes circuit means for giving different timing signals to each input buffer circuit according to a physical signal propagation distance from each input buffer circuit to the output line. The switch network is preferably a matrix switch.

The bit synchronization circuit includes means for generating m clocks having different phases, means for detecting a change point of data contained in the cell corresponding to the m clocks, and the change points. It is desirable to provide means for bit-synchronizing the data with a clock that does not exist.

It is desirable that a contention arbitration circuit be provided for each of the M output lines that takes in signals from the N input lines.

[0011]

Although the ATM switch of the present invention does not perform bit synchronization on the input side where cells arrive, an input buffer circuit is provided for each input line and the incoming cells are temporarily stored in this input buffer circuit. This input buffer circuit reads N ×
The M cell switches are controlled by a cell read timing generation circuit provided in common.

The read timing generating circuit sends out short pulses for each input buffer, and the generation timing of the short pulses is delayed according to the signal propagation time which is adjusted in advance to the physical shape of the switch network. In consideration of the above, they occur with a time shift of d. That is, a read timing signal is given to an input buffer circuit whose distance between the input buffer circuit and the output line is long, the read timing signal is delayed according to the distance, and the output timing of the cell is changed on the output line. Set so that they are almost equal. It suffices to prepare and use this time d step by step, and this time d is a value determined from the physical shape of the switch network, and it is not necessary to change it once it has been determined. Further, since the time d × n (where n is a natural number) precedes each other, if the shape of the switch network becomes large, the time d or the integer n may be increased, and the delay causes the repetition. The frequency is no longer limited.

The operation timing of the switch follows or synchronizes with the cell read timing generation circuit. And
At the next stage, that is, after the output line that does not appear in the drawing of this application,
Since the incoming cell needs to be bit-synchronized, it is bit-synchronized at the output line of the ATM switch. At that time, the signal amplitude of the cell appearing on the output line is matched with that of the cell to achieve synchronization. In that case, there is basically no relation to bit synchronization in the switch, and bit synchronization is taken at the input side of the switch, and it is no longer used after that switch. Therefore, the internal delay of the ATM switch naturally does not cause a problem. That is, in the present invention, unlike the conventional method in which bit synchronization is performed on the input side of the ATM switch and the ATM switch is operated according to the bit synchronization, bit synchronization is not required inside the ATM switch.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a first embodiment device of the present invention.

In the present invention, the input lines 101 to 104 and the output lines 201 to 204 are accommodated, and the input lines 101 to 1
A switch network 50 for switching and connecting the cells inputted from No. 04 to the output lines 201 to 204 according to the header information.
It is an ATM switch equipped with.

Here, the feature of the present invention is that input buffer circuits 21 to 24 for temporarily accumulating cells arriving at the input lines 101 to 104 are provided, and the read timing of the input buffer circuits 21 to 24 is set. A cell read timing generation circuit 1 for controlling the output line 201 to
Indicated by 204 are independent bit synchronization circuits 301 to 304 that operate in accordance with cells coming from the switch network 50, respectively.
Is provided.

The cell read timing generation circuit 1 is a circuit means for giving different timing signals to the respective input buffer circuits 21-24 according to the physical signal propagation distance from the respective input buffer circuits 21-24 to the output lines 201-204. It is a configuration including. The switch network 50 is a matrix switch.

Next, the operation of the apparatus according to the first embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. FIG. 2 is a time chart showing the clock of the cell read timing generation circuit 1. The cells input from the input lines 101 to 104 are input buffer 2
1 to 24 are accumulated. Cell read timing generation circuit 1
Generates timing for reading cells stored in the input buffer circuits 21 to 24 and transfers the timing to the input buffer circuits 21 to 24 via the signal lines 61 to 64. Each of the input buffer circuits 21 to 24 sends out a cell at a cycle Ts,
Between adjacent input buffer circuits 21 to 24, as shown in FIG. 2, cells are transmitted with a time shift of d hours.
The operation timing of the switches in each of the cross points 511 to 544 follows the cell read timing generation circuit 1 or is synchronized with it. In this way, cells are transferred within the switch network 50 without bit synchronization.

At the output of the switch network 50, the cells are input to the bit synchronization circuits 301 to 304, and bit synchronization is not achieved until they are input to the switch network 50. The bit synchronization circuits 301 to 304 synchronize bits of the cells input from the signal lines 111 to 114 with a plurality of clocks or one clock having a constant frequency which is input via the signal lines 401 to 404, and after the bit synchronization. The cells are output to the output lines 201 to 204.

Next, the switch network 50 of the first embodiment of the present invention will be described in more detail with reference to FIG. FIG. 3 is a detailed configuration diagram of the switch network 50. Input line 101-
The cell input from 104 is branched at branch points 51 to 54, one is input to the competition control circuit 15, and the other is connected to the cross points 511 to 544. The competition control circuit 15 performs competition control between cells input from the input lines 101 to 104, and transmits the control result to all the cross points 511 to 544 via the signal lines 351 to 354. The selector 60 at the cross point 5ij (i, j = 1 to 4: i row and j column) is input via the signal line 35j as the output of the cell input from the left adjacent cross point 5i (j-1). The signal line 4ij or 2ij is selected based on the value. As described above, the cell connected to the crosspoint 5ij is transferred through the preset route.

Next, referring to FIG. 4, the bit synchronization circuit 30
The algorithms 1 to 304 will be described. FIG. 4 is a diagram showing a clock selection algorithm using four-phase clocks c1 to c4. This algorithm detects the time domain where the data change point exists by punching the input cells with a multi-phase clock, and the clock having a phase that avoids the time domain of the data transition point and the input punched with this clock. Compare with the cell value. Here, the data change point region exists between the clocks c1 and c2, and the clock c2
The clock c3 immediately after is selected.

Next, a time chart of the multi-phase clock will be described with reference to FIG. FIG. 5 is a diagram showing a time chart of a 4-phase clock. The four-phase clock means four clocks input within one bit period (T). These four clocks are input at equal intervals (every T / 4) here. In this algorithm, m-phase clocks c1 to
cm is used, and the data change point area is clock ch and c.
Clocks c1 to c when existing between (h + 1)
(H-1) or clocks c (h + 2) to cm are candidates for the selected clock, and the actually selected clock is determined according to system design conditions based on the guarantee of jitter of input data (1 <h <M-2).

Next, the bit synchronizing circuits 301 to 304 of the first embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram of the bit synchronization circuits 301 to 304 of the first embodiment of the present invention. The multi-phase clock generation circuit 10 is based on the clock input through the signal lines 401 to 404, and here, the four-phase clocks 901 to 901 at the timing shown in FIG.
904 is generated and output. D flip-flop circuit 70
1 to 704 hold and update cells input via the signal lines 111 to 114 at the timings of the multiphase clocks 901 to 904.

The change point detection circuit 11 inputs the values of the input cells held in different phases via the signal lines 905 to 908 and controls the selectors 121 and 122 according to the clock selection algorithm shown in FIG. 3 here. To generate the output signal for outputting to the signal lines 909 and 910.
The selector 121 inputs the values of the input cells held in different phases via the branch points 84 to 87 of the signal lines 905 to 908, and based on the signal input via the signal line 909,
Select one of the signal lines 905 to 908 to select the signal line 91
Connect to 1. The selector 122 uses the multiphase clock 90.
1 to 904 are input via branch points 88 to 91, and a clock 901 is input based on a signal input via a signal line 910.
~ 904 select one clock and select signal line 912
Connect to. The D flip-flop circuit 705 holds and updates the value input via the signal line 911 with the clock input via the signal line 912, and outputs the output line 20.
Output to 1 to 204.

Next, operations of the change point detection circuit 11 and the selectors 121 and 122 will be described with reference to FIGS. FIG. 7 shows a change point detection circuit 11 and a secreter 12.
It is a block block diagram of 1,122. FIG. 8 is a time chart showing the operation of each part of the change point detection circuit 11 and the selectors 121 and 122. Fig. 9 shows the reset time Tr
FIG. The bit synchronization circuits 301 to 304 have four
It uses the phase clock. The selection clock determined by detecting the data change point of the first bit of the cell input from the signal lines 111 to 114 to the bit synchronization circuits 301 to 304 is output until the reset signal 971 is input.

As shown in FIG. 8, clocks 901 to 90 are provided.
4 is input at equal intervals T / 4. The outputs of the D flip-flop circuits 701 to 704 shown in FIG.
It is input to the change point detection circuit 11 via 08. Signals 921 to 924 of EXORs 711 to 714 shown in FIG.
Only one output outputs a high level by a maximum of 3T / 4, and the other outputs become a high level by a maximum of T / 4. EXOR711
The outputs of ˜714 become low level when the two values match and high level when they do not match. The data change point exists between the two clocks at the 3T / 4 high level. Signal 931
Reference numeral 934 denotes an input of the D flip-flop circuits 731 to 734, and when the signal 961 is at low level, the EXOR 71
The outputs of 1 to 714 are the same as those of the D flip-flop circuit 7
31-734 inputs, and when the signal 961 is at high level, the output values of the EXORs 711-714 are ignored and low-level signals are input to the D flip-flop circuits 731-734. The signals 981 to 984 are outputs of the D flip-flop circuits 731 to 734, and the input signal 931
The clock for punching through ~ 934 is converted to data updated later in the output signals of the binary D flip-flop circuits 70g and 70 (g + 1) compared by the EXORs 711-714 corresponding to the D flip-flop circuits 731-734. The inversion of the used clock c (g + 1) is used. The usable clock timing may be from c (g + 1) to the next cg (g = 1 to 4). Signal 95
Reference numerals 1 to 954 are outputs of the SR flip-flops 741 to 744, and when the signals 981 to 984 are once at the high level, they output the high level until the reset signal 971 is input. In the first embodiment of the present invention, the signal 952 becomes high level. When any of the SR flip-flops 741 to 744 becomes high level, the signal 9 output from the OR 751
61 becomes a high level and is connected to AND 721-724, and all the inputs of the D flip-flop circuits 731-734 become a low level. In the selectors 121 and 122, the signal line 908 and the clock 904 paired with the signal line through which the signal 952 is transmitted are 911 and 9 respectively.
12 is connected.

When the bit synchronizing circuits 301 to 304 are initialized, the switch network 50 is controlled so as to stop the cell input to the signal lines 111 to 114, and the SR flip-flops 741 to 744 receive reset signals. By applying 971 for a time corresponding to three clocks or more,
The initial state of can be given. This reset signal 9
71 is supplied from the outside of the bit synchronization circuits 301 to 304. Here, as shown in FIG. 9, the cell read timing generation circuit 1 is configured to provide a reset time zone Tr at the end of the cell and insert the reset signal 971 therein when reading the cell.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 10 is a configuration diagram of the bit synchronization circuits 301 to 304 having a clock selection algorithm using a three-phase clock used in the second embodiment of the present invention. FIG. 11 is a time chart showing the operation of each part of the change point detection circuit 11 and the selectors 121 and 122 in the second embodiment of the present invention. Multi-phase clock generation circuit 10
Generates and outputs three-phase clocks 901 to 903 based on the clocks input via the signal lines 401 to 404. The D flip-flop circuits 701 to 703 hold and update cells input via the signal lines 111 to 114 at the timings of the multiphase clocks 901 to 903.
The change point detection circuit 11 inputs the values of the input cells held in different phases via the signal lines 905 to 907. Here, output signals for operating the selectors 121 and 122 according to the clock selection algorithm shown in FIG. 4 are generated and output to the signal lines 909 and 910. In Figure 4,
Although the clock selection algorithm is shown as a four-phase clock, the principle can be similarly explained when a three-phase clock is used.
The selector 121 inputs the values of the input cells held in different phases via the branch points 84 to 86 of the signal lines 905 to 907, and based on the signal input via the signal line 909,
Select one of the signal lines 905 to 907 to select the signal line 91
Connect to 1. The selector 122 uses the multiphase clock 90.
1 to 903 are input via branch points 88 to 90, and a clock 901 is input based on a signal input via a signal line 910.
1 to 903 are selected and connected to the signal line 912. The D flip-flop circuit 705 holds and updates the value input via the signal line 911 with the clock input via the signal line 912, and outputs the output lines 201 to 20.
Output to 4.

Change point detection circuit 11 and selectors 121, 1
The operation of 22 will be described. Bit synchronization circuits 301 to 304
Uses a three-phase clock. Signal lines 111 to 11
The selection clock determined by detecting the data change point of the first bit of the cell head input from 4 to the bit synchronization circuits 301 to 304 is output until the reset signal 971 is input.

As shown in FIG. 11, clocks 901-9 are provided.
03 are input at equal intervals of T / 3. The outputs of the D flip-flop circuits 701 to 703 become signals 905 to 907. The signals 921 and 922, which are the outputs of the D flip-flop circuits 811 and 812, have the same phase as the signal line 907. The signals 1931 and 1932, which are the outputs of the EXORs 821 and 822, are delayed by d1 and the result is output. The output of EXOR 821 and 822 is 2
It goes low when the values match and goes high when the values do not match. The signal 1941 or 1942 which is the output of the D flip-flop circuits 831 and 832 becomes high level in the region where the data change point exists. In FIG.
Since the output of the D flip-flop circuit 831 becomes high level, there is a data change point between the clocks c1 and c2. The signals 1951 to 1954, which are the outputs of the SR flip-flops 841 and 842, output the high level of the signal 1951 or 1953 until the reset signal 971 is input once the input signal 1941 or 1942 becomes the high level. Signals 1952 and 1954 are signals 1951 and 1953, respectively.
Is an inverted signal of. Here, the signal 1951 is delayed by d2.
It goes high later. In the selectors 121 and 122, the signal line 907 paired with the signal line for transmitting the signal 1952 which is the inverted signal of the signal 1951 and the signal line for transmitting the clock 903 are connected to the signal lines 911 and 912, respectively.

The cell and the frame signal indicating the existence of this cell are transferred in parallel, and the bit synchronizing circuits 301 to 304 synchronize the bit of the input cell only when this frame signal is present. A malfunction due to noise or the like can be avoided.

The waveform distortion of the cell transferred in the switch network 50 is suppressed to the extent that a code error does not occur by applying well-known techniques such as balanced transmission of this cell and making the number of gate stages even. it can.

In the bit synchronization circuits 301 to 304,
The selection error of the selected clock caused by the jitter of the input cell can be avoided by fixing the selected clock to one cell cycle by the guarantee circuit composed of the OR 751 and AND 721 to 724 shown in FIG.

[0034]

As described above, according to the present invention,
By arranging the bit synchronization circuit at the output section of the ATM switch, the ATM switch output section can be bit-synchronized with the cell having an arbitrary phase. Therefore, the wiring length of the cell transfer path in the switch network can be increased. Wiring can be designed without being aware of As a result, it is possible to avoid the cell transfer rate limitation due to the wiring length difference between the plurality of wirings, and configure an ATM switch capable of high-speed cell transfer.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an apparatus according to a first embodiment of the present invention.

FIG. 2 is a time chart showing a clock of a cell read timing generation circuit.

FIG. 3 is a detailed configuration diagram of a switch network.

FIG. 4 is a diagram showing a clock selection algorithm using four-phase clocks.

FIG. 5 is a diagram showing a time chart of a four-phase clock.

FIG. 6 is a block configuration diagram of a bit synchronization circuit according to the first embodiment of the present invention.

FIG. 7 is a block configuration diagram of a change point detection circuit and a secreter.

FIG. 8 is a time chart showing the operation of each part of the change point detection circuit and the selector.

FIG. 9 is a diagram showing a reset time range.

FIG. 10 is a configuration diagram of a bit synchronization circuit according to a second embodiment of the present invention.

FIG. 11 is a time chart showing the operation of each part of the change point detection circuit and the selector in the second embodiment of the present invention.

FIG. 12 is a block diagram of a conventional example device.

[Explanation of symbols]

1 Cell Read Timing Generation Circuit 10 Multi-Phase Clock Generation Circuit 11 Change Point Detection Circuit 15 Contention Control Circuit 21-24 Input Buffer Circuit 50 Switch Network 61-64 Signal Line 101-104 Input Line 201-204 Output Line 301-304 Bit Synchronization Circuits 111-114, 211-234, 351-354, 4
01-404, 411-443, 905-944, 96
1-966 991-998 Signal lines 511-544 Cross points 51-54, 71-78, 81-95 Branch points 971 Reset signals c1-cm, 901-904, ... Clocks 701-705, 731-734, 811, 812 , 8
31, 832 D flip-flop circuit 60, 121, 122 selector 711-714, 821, 822 EXOR 721-724 AND 921-924, 1931-1934, 981-98
4, 951-954, 961, 1941, 1942, 1
951 to 1954 signal 771, 772, 751 OR 761 to 768 AND 741 to 744, 841, 842 SR flip-flop Tr reset time region

Claims (5)

[Claims] 1. A plurality of N input lines and a plurality of M output lines are accommodated, and cells input from the N input lines are switched and connected to the M output lines according to the header information. An ATM switch having a switch network is provided with an input buffer circuit for temporarily accumulating cells arriving at each of the N input lines, and a cell read timing generation circuit for controlling the read timing of the input buffer circuit, An ATM switch characterized in that each of M output lines is provided with an independent bit synchronization circuit which operates in accordance with a cell coming from a switch network. 2. The cell read timing generation circuit includes circuit means for applying different timing signals to each input buffer circuit according to a physical signal propagation distance from each input buffer circuit to an output line. ATM switch. 3. The ATM switch according to claim 1, wherein the switch network is a matrix switch. 4. The bit synchronization circuit includes means for generating m clocks (c1 to cm) having different phases and data contained in the cells corresponding to the m clocks (c1 to cm). Change point (eg ch and c (h +
1)) and a clock (for example, c1 to c) where this change point does not exist.
The AT according to claim 1, further comprising means for synchronizing the data bit by (h-1) or c (h + 2) to cm.
M switch. 5. The ATM switch according to claim 1, wherein a contention arbitration circuit is provided for each of the M output lines for receiving the signals of the N input lines.