JPH0766787A - Pointer abnormality detecting system - Google Patents

Abstract

PURPOSE:To provide a pointer abnormality detecting system capable of effectively detecting the abnormality of an AU-4-Nc pointer by simple constitution. CONSTITUTION:A pointer abnormality detecting system for detecting the abnormality of the AU-4-Nc pointer at the time of receiving an STM-N frame in synchronous digital hierarchy transmission is provided with a detecting means 10 for detecting discrepancy by comparing respective data of the received AU-4-Nc pointer with respective data stored in itself and a judging means 20 for judging the abnormality of the pointer when the means 10 detects any one or more coincidence continuously > n frames. Preferably respective data of H1#2/H1#3N bytes and H2#2/H2#3N bytes are fixed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pointer anomaly detection system, and more particularly, to AU-for receiving an STM-N frame in transmission of a synchronous digital hierarchy.
The present invention relates to a pointer abnormality detection method for detecting abnormality of a 4-Nc pointer. CCITT (International Telegraph and Telephone Advisory Committee)
Is a so-called Synchronous Digital Hierarchy (SDH: Synchronous) that can flexibly synchronize and synchronize various high speed service signals and existing speed signals in accordance with the progress of the ISDN era.
Digital Hierarchy) and defines a new synchronization interface in it. In response to this, the interface applied to Japan has been standardized domestically by the TTC (Telephone and Telephone Technical Committee).

[0002]

2. Description of the Related Art SDH is a basic STM (Synchronou
s Transport Module) -1 frame interface speed is {9 (rows) x 270 (columns) x 8 (bits)} / 12
5 (μs) = 155.52 Mb / s, and network connections around the world are connected to STM-N frames (155.52 Mb / s ×).
N) is standardized at the interface speed.

As shown in FIG. 4, this STM-1 frame has an overhead (9 rows × 9 bytes) for transmitting network operation management information when transmitting a main signal and a payload (9 rows × 261 bytes) for transmitting a main signal. ), And a virtual container (VC: Virtua) standardized in the payload.
l Container) is mapped (multiplexed) and transmitted, and the head position of the virtual container and the type (CI: CI) of the virtual container are controlled by the AU (Administrative Unit) pointer provided at the fixed position (4th line) of the overhead.
Concatenation indication).

By the way, in recent years, a method for mapping a VC-4-Nc virtual container into an STM-N frame and transmitting it has been devised. For that purpose, AU-
It is necessary to detect a pointer abnormality of the 4-Nc pointer and notify the failure. Figure 6 is a VC-4-N _C STM
It is a figure explaining the mapping to -N frame. VC
-4-N _C is a virtual container of 9 rows × (N × 261) bytes, and has 1 in the payload of the STM-N frame.
It is installed individually. In this case, AU-4-N _C pointer pair (H1 # 1, H2 # 1) the contents of it to indicate the head position of VC-4-N _C (J1 byte position), the other 3N
-1 set (H1 # 2, H2 # 2) to (H1 # 3N, H2 #
The contents of 3N) would represent the concatenation indication CI of VC-4-N _C.

[0005]

[SUMMARY OF THE INVENTION However, in the method of transmitting recently newly devised VC-4-N _C mapped to STM-N frame, unified AU-4
-N _C of pointer detection method is not defined. An object of the present invention is to provide a pointer abnormality detection method capable of effectively detecting a pointer abnormality of an AU-4-Nc pointer with a simple configuration.

[0006]

The above-mentioned problems can be solved by the structure shown in FIG. That is, the pointer abnormality detection method of the present invention is applicable to the ST in the transmission of the synchronous digital hierarchy.
In the pointer abnormality detection method for detecting the abnormality of the AU-4-Nc pointer when receiving the MN frame,
Detecting means 10 for detecting inconsistency by comparing each data of the received AU-4-Nc pointer with each data held by itself, and the detecting means 10 continuously detect any one or more inconsistencies for n frames. The determination means 20 for determining the pointer abnormality based on the above detection is provided.

[0007]

In the figure, the detecting means 10 receives the received AU-4.
-A mismatch is detected by comparing the respective data of # 1 to # 3N of each H1 and H2 of the Nc pointer with the respective data of # 1 to # 3N of each H1 and H2 possessed by itself. Since the detection means 10 as described above only needs to detect the presence or absence of a mismatch for each data, the circuit scale is small. Then, the determination unit 20 counts, for example, 1 for each frame when the detection unit 10 detects any one or more mismatches,
When a mismatch of n frames or more is continuously detected, it is determined that the pointer is abnormal. In this way, despite the single and simple configuration of the determination means 20, effective protection can be taken for the pointer abnormality determination, and the reliability of the pointer abnormality detection can be improved. Therefore, the circuit scale is small as a whole, and the pointer abnormality can be efficiently inspected.

Preferably, H1 held by the detection means 10
# 2 to H1 # 3N bytes and H2 # 2 to H2 # 3N
Each byte of data is fixed. That is, VC-4-
H1 # 2 to H1 # 3 N bytes and H2 # 2 to H2 representing the concatenation indication CI of Nc
Since each data of # 3N bytes is fixed,
In the detecting means 10, each data for comparison is fixed, and even if the multiplicity N increases, the inspection circuit can be constructed in a small scale as a whole.

[0009]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals denote the same or corresponding parts throughout the drawings. FIG. 2 is a diagram showing the configuration of the pointer abnormality detection system of the embodiment. In the figure, 10 is a detection means, and in the detection means 10, ₁₁ is AU-.
4-N _C H1 that checks H1 # 1 byte in pointer
# 1 testing unit, 1 ₂₁ is also H2 # 1 testing unit for inspecting H2 # 1 byte. Further, 1 ₁₂ is an H1 # 2 inspection unit for inspecting the H1 # 2 bytes, which is not shown below, but is similarly H1 # 3 to H1 # 3N and H2 # 2 to H2 #.
Each inspection unit for inspecting each byte of (3N-1) follows, and _123N is H2 # 3 for inspecting H2 # 3N bytes.
N inspection section.

Further, in the H1 # 1 inspection section _{11 1} , 2 ₁
Is a serial-parallel converter (SP), 2 ₂ and 2 ₃ are 8-bit registers (REG), 2 ₄ and ₂₅ are comparators (CMP), 2 ₆ are counters (CTR), 2 ₇ ,
2 ₈ denotes an AND gate circuit (A). H2 # 1 testing unit 1 ₂₁ is the same configuration as H1 # 1 testing unit 1 _11. Further H1 and # 2 test section 1 _12, 3 ₁ serial - parallel converter (SP), 3 ₂ a comparator (CMP),
3 ₃ is an AND gate circuit (A). Then, the remaining H1 # 3 inspection unit 1 _{13 to} H2 # 3N inspection unit 1 _23N are H1 #.
2 The inspection unit 1 ₁₂ has the same configuration.

On the other hand, 20 is a judging means, and the judging means
At 20, 4₁Is an OR gate circuit (O), 4₂Is
Lip flop (FF), 4₃Is a counter (CTR)
is there. It should be noted that the AU− input to the detecting means 10 is
4-N_CThe pointer is processed by an overhead processing unit (not shown).
Supplied. Now, H1 # 1 inspection unit 1₁₁Focusing on
SP2₁When the H1 # 1 byte is received at
Clock signal CK₁₁(However, CK₁₁At this timing
Generic name of a series of clock signals that occur)
This makes SP2₁Received H1 # 1 byte is REG2₂
Loaded in. Thus, SP2₁Is the current reception H
Holds 1 # 1 byte and REG2₂Is the reception one frame before
There is a relationship to hold the signal H1 # 1 byte. CMP2_FourIs
SP2₁Receive H1 # 1 byte (A) and REG2 ₂Receiving
Comparing both data with the signal H1 # 1 byte (B),
When A = B, a HIGH level is output, which causes CT
R2₆Is incremented by 1. When A = B is not satisfied, LOW level
Output the CTR2₆Is reset.

Therefore, when the coincidence of both data continues (P-1) times or more under such a condition, the output Q of the CTR ₂₆ is H.
When the IGH level is reached and A = B is satisfied at the same timing of the next frame, the received H1 # 1 byte of SP2 ₁ is loaded into REG2 ₃ . That is, this REG2
_When the same H1 # 1 byte is continuously received P times or more, 3 stores it as a correct H1 # 1 byte (AU instruction pointer).

On the other hand, CMP2_FiveIs SP2₁Current status of
Signal H1 # 1 byte (A) and REG2 ₃Determined to be correct
Compare both data with the AU instruction pointer (B)
When A = B, the LOW level is output. in this case
No error is detected. However, if A = B is not satisfied,
Outputs HIGH level, and as a result, AND gate circuit
Two₈Is the clock signal CK₁₁Error detection signal
Issue POER₁₁Will be output. In addition, H2 # 1 inspection
Inspection Department 1_{twenty one}The same applies to the clock signal in this case.
Issue CK_{twenty one}Is its SP2₁H2 # 1 byte is received at
Occurs at the timing, which causes the same operation as above.
Be seen.

Focusing on the H1 # 2 inspection section 1 ₁₂ , C
MP3 ₂ is the currently received H1 # 2 byte (A) of SP3 ₁ and H1 # internally patterned (fixed).
2 bytes: and comparing the both data with (B eg 9B _H), in the case of A = B outputs a LOW level. In this case, no error is detected. However, when A = B is not satisfied, a HIGH level is output, and as a result, the error detection signal POER ₁₂ is output at the timing of the clock signal CK ₁₂ via the AND gate circuit 3 ₃ . Although not shown, each inspection unit for inspecting subsequent CI bytes up to H1 # 3N has, for example, 9B _H as internally patterned data.

On the other hand, each inspection section for inspecting each CI byte after H2 # 2 has, for example, FF _H as internally patterned data. That is, for example, H2 # 3
In the N inspection unit 1 _23N , the CMP3 ₂ is SP3 ₁
The data of the currently received H2 # 3N byte (A) and the internally patterned H2 # 3N byte (B: FF _H ) are compared, and when A = B, the LOW level is output. To do. In this case, no error is detected. However, when A = B is not satisfied, the error detection signal POER _23N is output at the timing of the clock signal CK _23N .

In the judging means 20, the OR gate circuit 4
₁ takes the logical OR of each error detection signal POER _{11 to} POER _23N , and forcibly sets the flip-flop 4 ₂ when any one or more error detection signals are input. As a result, the output Q of the FF4 ₂ becomes HIGH level, and the inspection pulse CP generated at a predetermined timing once per frame rises to CTR4.
₃ is incremented by 1. After that, the FF4 ₂ outputs the inspection pulse C
It is reset when P falls. Therefore, if no error detection signal is input in the next frame,
FF4 ₂ remains reset, which causes CT
R4 ₃ is reset in synchronization with the rise in the check pulse CP of the frame. When any one or more of the error detection signal is input to the n frame or determining means 20 successively, CTR4 ₃ is a pointer error detection signal POER of the output Q to HIGH level, thus pointer abnormality is detected .

FIG. 3 shows the operation of the pointer abnormality detection system of the embodiment.
It is a work timing chart. In this example, STM-N
Error detection signal POER₁₁~ POE
R_{twenty three N}None of these have occurred. However, STM-N
Any one or more error detection signals POE
R₁₁~ POER_23NCounter 4 ₃
The count value of is incremented by 1 for each frame. That
At the end timing of the STM-N frame.
As a result of the error detection signal having continued for 4 frames,
Counter 4₃Pointer error detection signal POER from Q
Is being output. In addition, the next STM-N frame
Error detection signal POER at the end timing₁₁~ P
OER_23NSince neither of these occurred, the pointer error
-The detection signal POER is reset.

Incidentally, the configuration of the above embodiment is left as it is, as shown in FIG.
It can also be applied to the case of inspecting the pointer of VC-4 as shown in FIG. In this case, the 8-bit register in place of the fixed pattern scheme provided in the case if VC-4-N _C pointer and VC-4 pointer in the concatenation indication CI as content differs in, From system to concatenation indication CI
May be set.

Further, if three sets of the H1 # 1 inspection section 1 ₁₁ and the H2 # 1 inspection section 1 ₂₁ of the above embodiment are provided, the idea of the present invention can be applied to the inspection of the pointer of the VC-32. It can be realized with a relatively small circuit scale. Further, the STM of the present invention
-N for N frames and AU-4-Nc pointers
= 1, that is, the case where VC-4 is mapped to the STM-1 frame is also included.

[0020]

As described above, according to the present invention, the detecting means 10 for detecting a mismatch by comparing each received data of the AU-4-Nc pointer with each data held by itself, and the detecting means 10. Since the means 10 includes the determination means 20 for determining the pointer abnormality by continuously detecting any one or more inconsistencies of n frames or more, the pointer abnormality of the AU-4-Nc pointer can be effectively provided with a simple configuration. It is possible to detect and reduce the circuit scale and power consumption.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a diagram showing a configuration of a pointer abnormality detection system according to an embodiment.

FIG. 3 is an operation timing chart of the pointer abnormality detection system according to the embodiment.

FIG. 4 is a diagram illustrating an example of mapping VC-32 to an STM-1 frame.

FIG. 5 is a diagram illustrating an example of mapping VC-4 to STM-1 frame.

Figure 6 is a diagram illustrating the mapping of the STM-N frame of VC-4-N _C.

[Explanation of symbols]

 10 Detecting means 20 Judging means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuji Takizawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kazuyuki Tajima 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Satomi Ikeda, Satoshi Kamitadanaka, Nakahara-ku, Kawasaki, Kanagawa 1015, Fujitsu Limited (72) Inventor Hiroyuki Sato 1015, Uedota, Nakahara-ku, Kawasaki, Kanagawa Fujitsu Limited (72) Inventor, Hitoshi Uematsu Tokyo Nihon Telegraph and Telephone Corporation, 1-1-6 Uchisaiwaicho, Chiyoda-ku (72) Inventor Hiromi Ueda 1-1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (2)

[Claims] 1. When receiving an STM-N frame in transmission of a synchronous digital hierarchy, the AU-4-
In a pointer abnormality detection method for detecting an abnormality in an Nc pointer, a detection means (10) for detecting a mismatch by comparing each received data of the AU-4-Nc pointer with each data held by itself, The means (10) continuously repeats any one or more mismatches.
A pointer abnormality detection method comprising: a determination unit (20) for determining a pointer abnormality by detecting more than one frame. 2. The data of H1 # 2 to H1 # 3N bytes and H2 # 2 to H2 # 3N bytes held by the detecting means (10) are fixed.
Pointer abnormality detection method.