JPH0766714A - Ecl gate circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption while holding high speed operation. CONSTITUTION:When high potential side power supply potential VCC and low potential side power supply potential VEE are impressed, the same power supply current is allowed to flow between both the potential VCC, VEE through a current switching circuit 30, a clamping transistor(TR) 40 and a current switching circuit 50. Since the VEE is impressed to the circuit 30, the circuit 30 executes stable logical. operation and variation in the power supply potential due to the logical operation is turned to be fixed voltage through the TR 40 and the fixed voltage is impressed to the circuit 50. Thereby the circuit 50 independently executes stable logical operation. Since partial charge of power consumption based upon a power supply current flowing between the VCC and VEE is taken by both the circuits 30, 50, power consumption per gate is reduced to a half of a conventional value.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an ECL (Emitter Coup) which is one of basic circuits formed in a semiconductor integrated circuit device manufactured by a bipolar technology or a bipolar CMOS (complementary MOS transistor) technology.
led Logic) This is related to the gate circuit.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. References: Shibata / Yamamoto / Tominaga / Takahashi / Toyo, "Introduction to VLSI Technology", First Edition (1986-9-1), Heibonsha, P.
110-111 As described in the above-mentioned documents, the ECL gate circuit is a current switching type logic circuit based on a differential amplifier circuit in which the emitters of transistors are commonly connected. Since each transistor does not perform a saturation operation, it can form a high-speed switching circuit and is widely used in various devices that require a high-speed logic gate. Since the basic form of the circuit is an emitter follower, the input impedance is high and the output impedance is low, so a large fan-out can be obtained.
On the other hand, the power consumption is higher than that of TTL (transistor / transistor / logic).

FIG. 2 shows a conventional EC described in the above document.
It is a circuit diagram which shows one structural example of an L gate circuit. This EC
The L gate circuit compares the plurality of input signals A1, A2 and A3 with the reference potential V _BB and outputs the comparison result from the output nodes N15 and N16, and the current switch circuit 10 to the current switch circuit 10. A high-speed digital circuit composed of bipolar transistors, which includes a constant current source circuit 20 for supplying a constant current, and emitter follower circuits 21 and 22 connected to the output nodes N15 and N16, respectively, for improving the driving capability of the load. The current switch circuit 10 has a plurality of input transistors 11, 1 whose input signals A1, A2, A3 are input to their bases, respectively.
2 and 13 and a reference transistor 14 to which a reference potential V _BB is input, and these transistors 11 and
12, 13, 14 emitters are commonly connected. The collectors of the plurality of input transistors 11, 12, 13 are commonly connected to the output node N15, and
15 through the resistor 15 to the high-potential-side power supply potential V _CC (= 0
V). The collector of the reference transistor 14 is connected to the output node N16, and the output node N1
6 is connected to the power supply potential V _CC through the resistor 16.
The commonly connected emitters of the transistors 11, 12, 13, and 14 are connected to the power supply potential V _EE on the low potential side via the constant current source circuit 20.

The emitter follower circuit 21 is a circuit for driving an output load connected to the output terminal Q1 by using the output signal of the output node N15 of the current switch circuit 10 as an input, and the emitter follower transistor 21a and the resistor 2
It has 1b. The transistor 21a has a collector connected to the power supply potential V _CC , a base connected to the output node N15, and an emitter connected to the output terminal Q1. Resistance 21
b, one end thereof is the output terminal Q1 and the other end thereof is the power supply potential V _EE.
Respectively connected to. Similarly, the emitter follower circuit 22 outputs the output node N of the current switch circuit 10.
It is a circuit for driving the output signal of 16 and outputting it from the output terminal Q2, and has an emitter follower transistor 22a and a resistor 22b. The transistor 22a has a collector at the power supply potential V _CC and a base at the output node N16.
The emitters are connected to the output terminal Q2. The resistor 22b has one end connected to the output terminal Q2 and the other end connected to the power supply potential V _EE . This kind of EC
In the well-known ECL 10KH specification in the L gate circuit, the power supply potential V _CC = 0V and the power supply potential V _EE = −5.2.
V and reference potential V _BB = -1.29V.

Next, the operation will be described. Multiple input signals A
When the potentials of 1, 1, A2 and A3 are lower than the reference potential V _BB , the transistor 14 is turned on and the transistors 11, 12, 13 are turned off. Transistor 1
When 4 is turned on, a constant current supplied by the constant current source circuit 20 flows through the resistor 14 through the transistor 14 to cause a voltage drop, so that the potential of the output node N16 is lower than the power supply potential V _CC by a voltage drop. . V _CC to 0
V, if this voltage drop is designed to be 0.8V, the potential of the output node N16 becomes -0.8V. Transistor 22a
Since the built-in voltage between the base and the emitter is about 0.8V, the potential of the output terminal Q2 becomes the "L" level of about -1.6V. When the transistors 11, 12 and 13 are turned off, no current flows through the resistor 15, so that the output node N
The potential of 15 is equal to the power supply potential V _CC . Transistor 21
Since the built-in voltage between the base and the emitter of a is about 0.8V, the potential of the output terminal Q1 becomes "H" level of about -0.8V. When the potential of any one of the plurality of input signals A1, A2, A3 (for example, A1) is higher than the reference potential V _BB , the transistor 11 is turned on and the transistor 14 is turned off. Therefore, contrary to the above,
The potential of the output node N16 becomes 0 V, the output terminal Q2 becomes "H" level, and the potential of the output node N15 becomes -0.
It becomes 8V, and the output terminal Q1 becomes "L" level. NOR output from output terminal Q1, output terminal Q
An OR (logical sum) output can be taken out from 2. In this type of circuit, the power supply current can be kept constant, which can suppress power supply noise.

[0006]

However, the conventional ECL gate circuit composed of bipolar transistors has the following problems and it is difficult to solve them. In the conventional ECL gate circuit, each of the transistors 11, 12, 13, 14, ... Does not perform a saturation operation, so that it has an advantage of operating at a higher speed than a CMOS gate circuit or a bipolar CMOS gate circuit. However, since it is necessary to constantly supply current to the current switch circuit 10, there is a problem of high power consumption, which is difficult to solve with a relatively simple circuit configuration. The present invention provides an ECL gate circuit that solves the problem that the above-mentioned conventional technique has, which makes it difficult to reduce power consumption while enabling high-speed operation.

[0007]

In order to solve the above problems, the present invention provides an ECL gate circuit having a plurality of transistors whose emitters are commonly connected, and a current path is switched by their base inputs. 1 current switch circuit, a first emitter follower circuit that drives an output load based on the output signal of the first current switch circuit, a clamping transistor to which a fixed potential is applied to the base, and an emitter are commonly connected. A second current switch circuit having a plurality of transistors, whose current paths are switched by their base inputs, and a second emitter follower circuit for driving an output load based on the output signal of the second current switch circuit. , And a constant current source circuit for supplying a constant current. The first current switch circuit, the clamping transistor, the second
The current switch circuit and the constant current source circuit are sequentially connected in series between the first and second power supply potentials.

[0008]

According to the present invention, since the ECL gate circuit is constructed as described above, when the first and second power supply potentials are applied, the same current flows through the first and second current switch circuits. Although the potential at the connection point between the first current switch circuit and the clamping transistor fluctuates according to the logical operation of the first current switch circuit, the potential at the connection point between the second current switch circuit and the clamping transistor becomes A constant voltage is applied by the clamping transistor, and a constant voltage is applied to the second current switch circuit. Therefore, the first and second current switch circuits are
Stable logical operation is performed independently. The same current flows through the first and second current switch circuits, and their power consumption is shared by these first and second current switch circuits, so that the power consumption per gate is 1 / 2. Therefore, the above problem can be solved.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of an ECL gate circuit composed of bipolar transistors showing an embodiment of the present invention. The ECL gate circuit includes a first current switch circuit 30 connected between a first power supply potential (for example, a high-potential-side power supply potential) V _CC and a node N30, and a node between the nodes N40 and N50. It has the 2nd current switch circuit 50 connected. The clamping transistor 40 is connected between the nodes N30 and N40, and the node N50 is connected to the second power supply potential (for example, the power supply potential on the low potential side) V _EE via the constant current source circuit 60. There is. To the two output nodes N35 and N36 of the first current switch circuit 30, two emitter follower circuits 41 and 42 that drive an output load based on their outputs are connected. Similarly, to the two output nodes N55 and N56 of the second current switch circuit 50, two emitter follower circuits 61 and 62 for driving an output load based on their outputs are connected, respectively. The first current switch circuit 30 has a plurality of input signals A1, A
2, A3 and the reference potential V _th 1 are compared with each other and their comparison results are output from the output nodes N35 and N36. The input signals A1, A2 and A3 are respectively input to the bases of the NPN type. Input transistors 31, 32,
33, and an NPN-type reference transistor 34 having a base to which the reference potential V _th 1 is input, and their emitters are commonly connected to a node N30. Transistor 3
The collectors of 1, 32 and 33 are commonly connected to the output node N35, and the output node N35 is connected to the power supply potential V _CC through the resistor 35. The collector of the transistor 34 is connected to the output node N36, and the output node N3
6 is connected to the power supply potential V _CC through the resistor 36.

The emitter follower circuit 41 connected to the output node N35 has an NPN type emitter follower transistor 41a whose base is connected to the output node N35.
And a resistor 41b, and the collector of the transistor 41a is connected to the power supply potential V _CC . The emitter of the transistor 41a has an output terminal Q for extracting the NOR output.
1 and the output terminal Q1 is connected to the power supply potential V _EE via the resistor 41b. The emitter follower circuit 42 connected to the output node N36 is connected to the output node N3.
6 has an NPN type emitter follower transistor 42a whose base is connected to 6 and a resistor 42b, and the collector of the transistor 42a is connected to the power supply potential V _CC . The emitter of the transistor 42a is connected to the output terminal Q2 for extracting the OR output, and the output terminal Q2 has a resistor 4
It is connected to the power supply potential V _EE via 2b. The collector of an NPN-type clamping transistor 40 is connected to the node N30 of the first current switch circuit 30. A constant potential V _C is applied to the base of the transistor 40, and the emitter thereof is the second current switch circuit 5
0 node N40. The transistor 40 functions to make the potential of the node N40 constant.

The second current switch circuit 50 has a first
Similarly to the current switch circuit 30 of FIG. 3, the circuit compares the plurality of input signals A4, A5, A6 with the reference voltage V _th 2 and outputs the comparison result from the two output nodes N55, N56. This current switch circuit 50
Is an NPN type input transistor 51, 52, 53 whose input signals A4, A5, A6 are input to their bases, respectively.
And an NPN type reference transistor 54 into which the reference potential V _th 2 is input, and their emitters are commonly connected to a node N50. Transistors 51 and 5
The collectors of 2, 53 are commonly connected to an output node N55, and the output node N55 is connected to a node N4 via a resistor 55.
It is connected to 0. The collector of the transistor 54 is
It is connected to the output node N56, and the output node N56 is connected to the node N40 via the resistor 56. The emitter follower circuit 61 connected to the output node N55 is
The node N55 has an NPN type emitter follower transistor 61a connected to the base and a resistor 61b, and the collector of the transistor 61a is connected to the power supply potential V _CC . The emitter of the transistor 61a is N
It is connected to an output terminal Q3 for extracting the OR output, and the output terminal Q3 is connected to the power supply potential V _EE via the resistor 61b. The emitter follower circuit 62 connected to the output node N56 has its emitter follower transistor 62a of NPN type whose base is connected to the output node N56, and a resistor 62b, the collector of the transistor 62a to the power source potential V _CC It is connected. The emitter of the transistor 62a is connected to the output terminal Q4 for extracting the OR output, and the output terminal Q4 is connected to the power supply potential V _EE via the resistor 62b.
It is connected to the.

The node N50 of the second current switch circuit 50 is connected to the power supply potential V _EE via a constant current source circuit 60 for supplying a constant current to the ECL gate circuit. FIG. 3 is a circuit diagram showing a configuration example of the constant current source circuit 60 in FIG. This constant current source circuit 60 has a resistor 60a, one end of which is connected to the power supply potential V _CC , and the other end of which is connected two NPN type transistors 60b and 60c forming a current mirror circuit. Transistor 6
0b has the collector of the second current switch circuit 5
0 node N50 and base is transistor 6
The emitter is the power supply potential V _EE to the base and collector of 0c.
Respectively connected to. The transistor 60c has a collector and a base connected to the resistor 60a and an emitter connected to the power supply potential V _EE , respectively. The operation of the ECL gate circuit configured as above will be described. When the power supply potentials V _CC and V _EE are applied, a constant power supply current is generated by the current mirror operation of the transistors 60b and 60c in the constant current source circuit 60, the first current switch circuit 30, the clamping transistor 40, and the second current switch. Flow through circuit 50. First current switch circuit 3
For 0, the switching operation is performed by applying the power supply potential V _CC , and the potential of the node N30 fluctuates by the switching operation, but a constant potential V _C is applied to the base of the transistor 40, and the collector current of the transistor 40 changes. Since it is constant, the base-emitter voltage of the transistor 40 is constant. Therefore, the second current switch circuit 5
A constant voltage is applied to the node N40 of 0, and the second current switch circuit 50 performs a stable switching operation based on the voltage. Therefore, the first and second current switch circuits 30 and 50 can perform independent logical operations.

For example, the first current switch circuit 30
When the potentials of the input signals A1, A2 and A3 are lower than the reference potential V _th 1, the transistor 34 is turned on and the transistors 31, 32 and 33 are turned off. When the transistor 34 is turned on, a constant current supplied by the constant current source circuit 60 flows to the resistor 36 through the transistor 34 and a voltage drop occurs, so that the potential of the output node N36 drops by a voltage drop below the power supply potential V _CC. . At the same time, the potential of the output terminal Q2 also drops by the amount of this voltage drop and becomes "L" level. Transistor 31,
When 32 and 33 are turned off, no current flows through the resistor 35, so that no voltage drop occurs. The potential of the output node N35 is equal to the power supply potential V _CC , and the output terminal Q1 becomes "H" level. On the other hand, when the potential of any one of the input signals A1, A2 and A3 (for example, A1) is higher than the reference potential V _th 1, the transistor 31 is turned on and the transistor 34 is turned off. Therefore, contrary to the above, a constant current supplied by the constant current source circuit 60 flows through the resistor 35 and a voltage drop occurs, so that the potential of the output node N35 falls below the power supply potential V _CC by a voltage drop. At the same time, the potential of the output terminal Q1 also drops by the amount of this voltage drop and becomes "L" level. Further, since no current flows through the resistor 36, no voltage drop occurs. The potential of the output node N36 is equal to the power supply potential V _CC , and the output terminal Q1 becomes "H" level. The constant current source circuit 60 supplies a constant current to the current flowing through the first current switch circuit 30. This current flows through the clamping transistor 40 to the second current switch circuit 50.

The second current switch circuit 50 performs the same logical operation as the first current switch circuit 30. In the ECL gate circuit of FIG. 1, in order to operate at high speed, each bipolar transistor 31, 32, 3
It is necessary that 3, ... Do not operate in saturation, and in designing, pay attention to this point and set the power supply potential and the like as follows. For example, the ECL 10KH specification is adopted, and the power supply potential V _CC = 0V and the power supply potential V _EE = −4.94V (ECL 1
(Maximum voltage in 0 KH standard), the reference potential V _{t h} 1
= −1.1 V, reference potential V _th 2 = −3.57 V, and fixed potential V _C = −1.67 V, output terminals Q1, Q2,
It is assumed that the output voltage amplitudes of Q3 and Q4 are designed to be 0.6V. Since the built-in voltage between the base and emitter of the bipolar transistor is about 0.8V, the first
Output nodes N35, N3 of the current switch circuit 30 of
The output voltage of 6 is 0V to -0.6V, output terminals Q1 and Q2
Output voltage is -0.8V to -1.4V, and the voltage of the node N30 of the first current switch circuit 30 is -1.6V to
The voltage of the node N40 of the −1.9V and the second current switch circuit 50 becomes −2.47V. This allows the second
Output nodes N55 and N5 of the current switch circuit 50 of
6 has an output voltage of -2.47V to -3.07V, output terminals Q3 and Q4 have output voltages of -3.27V to -3.87V,
The voltage of the node N50 of the second current switch circuit 50 is -4.07V to 4.37V. If, for example, a circuit as shown in FIG. 3 is used as the constant current source circuit 60 in FIG. 1, all the bipolar transistors other than the clamping transistor 40 in FIG. 1 and the transistor 60b in FIG.
Since its base-collector junction is not reverse biased, it always operates in the unsaturated region. Clamping transistor 40 and transistor 60b in constant current source circuit 60
Operates in the shallow saturation region because a reverse bias of -0.23V is applied between the base and collector junctions. However, it has been confirmed that there is no hindrance to the high speed operation of the ECL gate circuit of FIG.

As described above, this embodiment has the following advantages. In the conventional ECL gate circuit of FIG. 2, for example, the power supply potential V _EE is -5.2 V and one set of the current switch circuits 10 is operated. On the other hand, in the present embodiment, since two sets of current switch circuits 30 and 50 are connected in series via the clamping transistor 40, for example, when the power supply potential V _EE is −5.2 V, those two sets are connected. The current switch circuits 30 and 50 can be operated independently, and two sets of gate circuits can be configured. Therefore, the current switch circuit 30,
The power consumption per gate due to the current flowing through 50 is halved as compared with the conventional one, so that the power consumption per gate can be reduced. Moreover, since the first and second current switch circuits 30 and 50 are connected in series via the clamping transistor 40, the circuit structure is simple. The present invention is not limited to the above-mentioned embodiment, and for example,
The bipolar transistor that constitutes the ECL gate circuit of FIG. 1 may be configured as another transistor such as a PNP type transistor, or the input transistors 31 to 33, 51 to 53.
Can be set to an arbitrary number other than that shown in the figure, or the constant current source circuit 60 of FIG.

[0016]

As described in detail above, according to the present invention, since the first and second current switch circuits are connected in series via the clamping transistor, a predetermined power source is provided. The same current flows through the first and second current switch circuits due to the potential, and these two sets of current switch circuits can independently perform a logical operation,
Two sets of gate circuits can be constructed. Therefore, the power consumption per gate due to the current flowing through the first and second current switch circuits is halved as compared with the conventional one, and the power consumption can be reduced. Moreover, since the first and second current switch circuits are connected in series via the clamping transistor, the voltage made constant by the clamping transistor is applied to the second current switch circuit, and the voltage causes The second current switch circuit performs the switching operation. Therefore, the first and second current switch circuits perform stable logical operation with a relatively simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an ECL gate circuit showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional ECL gate circuit.

3 is a circuit diagram of a constant current source circuit in FIG.

[Explanation of symbols]

30, 50 1st, 2nd current switch circuit 31-33, 51-53 Input transistor 34, 54 Reference transistor 40 Clamp transistor 41, 42, 61, 62 Emitter follower circuit 41a, 42a, 61a, 62a Emitter follower transistor 60 constant current source circuit N35, N36, N55, N56 output node Q1, Q2, Q3, Q4 output terminal V _C fixed potential V _CC high potential side power source potential V _EE low potential side power source potential V _th 1, V _th 2 Reference potential

Claims (1)

[Claims] 1. A first current switch circuit having a plurality of transistors whose emitters are commonly connected and whose current paths are switched by their base inputs, and an output load based on an output signal of the first current switch circuit. A first emitter follower circuit for driving the transistor, a clamping transistor to which a fixed potential is applied to the base, and a plurality of transistors whose emitters are commonly connected,
A second current switch circuit whose current path is switched by their base inputs, a second emitter follower circuit that drives an output load based on the output signal of the second current switch circuit, and a constant current source that flows a constant current. A first current switch circuit, a clamping transistor, a second current switch circuit, and a constant current source circuit, which are connected in series between the first and second power supply potentials. An ECL gate circuit characterized by the above.