JPH0766658B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method in a semiconductor memory device, and more specifically, a random access memory (RAM) port and a serial access memory (SAM) inside. And a data transfer method in a 2-port memory device having a port.

[Prior Art] In recent years, a 2-port memory device has been proposed for application to a graphic display system. This 2
The port memory device has two ports, a RAM port that can be randomly accessed and a SAM port that can be serially accessed. For details, see the Nikkei Electronics magazine, August 12, 1985 issue ( p.211 to 240)
Is shown in. A conventional data transfer method between a RAM port and a SAM port is disclosed in, for example, Japanese Patent Laid-Open No. 62-242252. Hereinafter, these conventional examples will be described.

FIG. 3 is a block diagram showing a schematic configuration of a conventional 2-port memory device. In the figure, this two-port memory device includes a RAM (random access memory) 1, a SAM (serial access memory) 2, a transfer unit 3, and a control circuit 4. The RAM 1 is composed of a memory cell array 11, a row decoder 12, an I / O switch 13, and a column decoder 14. The memory cell array 11 has a plurality of word lines WL.
, And a plurality of pairs of bit line pairs BL, ▲ ▼ are arranged to intersect with each other, and a memory MC is provided at each intersection.
The row decoder 12 selects one word line from the plurality of word lines WL based on the input row address. I /
The O switch 13 is provided for each bit line BL and ▲ ▼, and is commonly connected to the I / O line 15.
The column decoder 14 receives I / O based on the input column address.
By selectively opening and closing the switch 13, a desired bit line pair BL and ▲ ▼ is selected. As is well known,
In the RAM 1 as described above, data can be written into and read from any memory cell MC at any time.

The transfer unit 3 is provided between the RAM1 and the SAM2, and is provided between the RAM1 and the SAM2.
Transfers data between each other. The transfer unit 3 includes a precharge circuit 3 provided for each bit line pair BL, ▲ ▼.
1, including a sense amplifier 32 and a transfer gate 33.
Each precharge circuit 31 precharges the corresponding bit line pair BL, ▲ ▼ by a precharge signal PR given from a timing control circuit (not shown). Each sense amplifier 32 amplifies a minute potential difference appearing between the corresponding bit line pair BL, {circle around (1)} during reading or writing of data. These sense amplifiers 32 are activated by a pair of sense amplifier activation signal lines SD, ▲ ▼ extending from the control circuit 4. Each transfer gate 33 has a corresponding bit line pair BL, ▲ ▼ and S depending on the applied transfer signal TG.
Controls opening and closing with AM2.

The SAM 2 includes a data register 21 and a serial selector 22. The data register 21 is provided for each bit line BL, ▲ ▼, and corresponds to one row (1
Holds data for word line). Serial selector 22
Reads the data held in the data register 21 and serially outputs it to the input / output line 23, and writes the serial data input via the input / output line 23 into the data register 21.

Next, with reference to FIG. 4, the circuit configuration of the transfer unit 3 and its peripheral circuits in FIG. 3 will be described. Memory cell MC ₀
Is composed of an N-channel type MOS transistor (hereinafter referred to as an NMOS transistor) NQ1 and a capacitor C, and is selected by setting the word line WL to H level. The precharge circuit 31 _0, NMOS transistors NQ2 and NQ3
Are serially inserted between the bit line BL ₀ and {circle around ( ₀₎ }. A precharge signal PR is applied to the gates of the NMOS transistors NQ2 and NQ3 from a timing control circuit (not shown). And the precharge circuit 31
₀ is turned on when the precharge signal PR is at the H level, and the precharge voltage Vcc / 2 is set to the bit line pair BL ₀ , ▲ ▼
_{Apply 0} . As a result, the bit line pair BL ₀ , ▲ ▼
₀ is precharged. The sense amplifier 32 _0, MOS transistors (hereinafter P-channel NMOS transistors NQ4 and NQ5 a pair of cross-coupled with a pair with each other, PM
It is called an OS transistor) composed of PQ1 and PQ2.
The sense amplifier 32 _0, the sense amplifier activation signal line pair SD from the control circuit 4, ▲ ▼, respectively, H-level,
Bit line pair BL ₀ , ▲ ▼
A small potential difference between ₀ is amplified. Transfer gate 33 ₀
Is composed of two NMOS transistors NQ6 and NQ7 which are respectively interposed between the bit line pair BL ₀ , ▲ ▼ ₀ and the storage node line DR ₀ , ▲ ▼ ₀ of the data register 21 ₀ . These NMOS transistors NQ6 and NQ7 are turned on when the transfer signal TG is at H level, and the bit line pair BL ₀ , ▲
▼ ₀ is connected to the storage node pair DR ₀ , ▲ ▼ ₀ .
The data register 21 ₀ is composed of two inverters IV1 and IV2 connected in parallel in opposite directions between the bit line pair BL ₀ , ▲ ▼.

The memory cell MC ₁ , precharge circuit 31 ₁ , sense amplifier 32 ₁ , transfer gate 33 ₁ and data register 21 ₁
Also has the same configuration as the memory cell MC ₀ , the precharge circuit 31 ₀ , the sense amplifier 32 ₀ , the transfer gate 33 ₀ and the data register 21 ₀ , respectively. Further, in FIG. 4, these memory cells, precharge circuits, sense amplifiers, transfer gates and data registers are shown as two for simplification.
Although only pairs are shown, there are actually many pairs as shown in FIG.

The control circuit 4 includes a sense amplifier activation signal line pair SD,
▼ Two NMOS transistors NQ8 and NQ inserted in series between
9, a PMOS transistor PQ3 inserted between the sense amplifier activation signal line SD and the power supply Vcc, and an NMOS transistor NQ10 inserted between the sense amplifier activation signal line ▲ ▼ and the ground. To be done. NMOS transistor NQ8
A precharge signal PR is applied to each gate of NQ9 and NQ9 from a timing control circuit (not shown). Then, these NMOS transistors NQ8 and NQ9 are turned on when the precharge signal PR is at a high level, and apply the precharge voltage Vcc / 2 to the sense amplifier activation signal line pair SD, ▲ ▼. As a result, the sense amplifier activation signal line pair S
D and ▲ ▼ are precharged. In addition, the gates of the PMOS transistor PQ3 and the NMOS transistor NQ10 are
A sense amplifier enable signal ▲ ▼ and SAE are respectively applied from a timing control circuit (not shown).
Then, the PMOS transistor PQ3 and the NMOS transistor N
Q10 is the sense amplifier enable signal ▲ ▼, SAE
Are turned on at L level and H level respectively,
The sense amplifier activation signal line SD is driven to H level, and the sense amplifier activation signal line () is driven to L level.

In the above configuration, RAM1 and SAM2 operate asynchronously. Then, 1 stored in the memory cell array 11
Data for one row (one word line) is collectively transferred to the data register 21 of the SAM 2 by the transfer unit 3, and serially output from the input / output line 23 by the serial selector 22.
In addition, the data input from the serial selector 22 is held in the data register 21, and the transfer unit 3 collectively RA
It is transferred to M1 and written in the memory cell array 11.

Next, a method of transferring data from the RAM1 to the SAM2, for example, from the memory cell MC ₀ to the data register 21 ₀ will be described with reference to the waveform diagram of FIG. Prior to data transfer, the precharge signal PR is at H level, and the bit line pair BL ₀ , ▲
▼ ₀ and sense amplifier activation signal line pair SD, ▲ ▼
Are both precharged to Vcc / 2. When the precharge signal PR is set to L level at time t ₀ , the bit line pair BL ₀ , ▲
▼ ₀ and sense amplifier activation signal line pair SD, ▲
▼ becomes a high impedance state while maintaining the level of Vcc / 2. Next, when the word line WL is set to the H level at time t ₁ , the electric charge stored in the capacitor C of the memory cell MC ₀ is read onto the bit line BL ₀ . Here, if the H level is stored in the capacitor of the memory cell MC ₀ , the potential of the bit line BL ₀ slightly rises. After time Δt ₁ sufficient for reading out the charges, that is, at time t ₂ , sense amplifier enable signal SAE,
▲ ▼ the H level, respectively, when the L level, the sense amplifier 32 ₀ is paired bit lines BL _0, ▲ ▼ starts amplification of the potential difference between _0. After a time period Δt ₂ for which this amplification is sufficiently performed, at time t ₃ , the transfer signal TG is set to the H level. Since the drive capacities of the inverters IV1 and IV2 forming the data register 21 ₀ are set smaller than the drive capacities of the respective transistors forming the sense amplifier 32 ₀ ,
The data stored in the data register 21 ₀ is rewritten by the sense amplifier 32 ₀ via the transfer gate 33 ₀ .
Data stored in the memory cells MC ₀ by the above operation is transferred to the data register 21 _0.

Then from SAM2 to RAM1, for example, data register 21 ₀
The method of transferring data to the memory cells MC ₀ from will be described with reference to the waveform diagram of Figure 6. Prior to data transfer, the precharge signal PR is set to H level to precharge each node. When the transfer signal TG is set to H level after the precharge signal PR is set to L level at time t ₀ , the potential of the bit line pair BL ₀ , ▲ ▼ ₀ changes according to the data stored in the data register 21 _0. start. For example, if storage node {circle over ( ₀₎ } is at H level and storage node DR ₀ is at L level, bit line {circle around ( ₀₎ } starts changing to H level and bit line BL ₀ starts changing toward L level. Next, when the word line WL is set to the H level at time t ₁ , the electric charge stored in the capacitor in the memory cell MC ₀ is read out onto the bit line BL ₀ , but it is absorbed by the driving capability of the data register 21 _0. Will be done. Bit line pair BL ₀ , ▲
▼ After the potential difference between ₀ becomes large, the sense amplifier is activated at time t ₂ to set the bit line BL ₀ to the L level and the bit line ▲
▼ Set ₀ to H level. At this time, the word line WL is H
Since it is at the level, the data is written in the memory cell MC ₀ .

In the above description, only the set having a reference numeral of 0 is taken, but the data transfer is performed in the same manner for the other sets.

By the way, in a graphic display system, a usage such as transferring not all of all data but only a part thereof is often used. 7th
FIG. 8 and FIG. 8 show an example of a 2-port memory device which enables such partial transfer. The transfer gate 33 ₀ is configured to be controlled by the transfer signal TG ₀ , and the transfer gate 33 ₁ is configured to be controlled by another transfer signal TG ₁ , and only the transfer signal corresponding to the data register to be transferred is set to the H level. Partial transfer is done by doing so. However, in the case of the configuration shown in FIG. 7 and FIG. 8, in the conventional transfer method, the following problems occur when transferring data from the data register 21 to the memory cell MC. This will be described with reference to the waveform chart of FIG. time
It is assumed that after the precharge signal PR is set to the L level at t ₀ , the transfer signal TG ₀ becomes the H level and the transfer signal TG ₁ remains at the L level. At this time, bit line pair BL ₀ , ▲ ▼
₀ of voltage starts changing in accordance with the data stored in the data register 21 _0. For example, storage node DR ₀
Is at the H level and the storage node {circle over ( ₀₎ } is at the L level, the potential of the bit line BL ₀ rises from Vcc / 2 and the potential of the bit {circle over ( ₀ )} drops from Vcc / 2. Then, the potential of the bit line BL ₀ becomes higher than the threshold voltage of the NMOS transistor NQ5 constituting the sense amplifier 32 _0, the MNO
The S transistor NQ5 turns on. Similarly, when the potential of the bit line {circle around ( ₀ )} becomes lower than the threshold voltage of the PMOS transistor PQ1 forming the sense amplifier 32 ₀ , this P
The MOS transistor PQ1 is turned on. Therefore, the sense amplifier activation signal line SD and the bit BL ₀ , and the sense amplifier activation signal line ▲ ▼ and the bit line ▲ ▼ ₀ are connected. At this time, the sense amplifier activation signal line SD, ▲ ▼
Since both are in the high impedance state, the potential of the sense amplifier activation signal line SD is pulled to the bit line BL ₀ and starts to rise, and the potential of the sense amplifier activation signal line ▲ ▼ is pulled to the bit line ▲ ▼ _0. Start descent. The potential of the sense amplifier activation signal line SD, ▲ ▼ is Vcc / 2,
When changing over the threshold voltage of the transistors constituting the sense amplifier 32 _1, sense amplifier 32 ₁ starts an amplifying operation. However, at this time, the word line WL is not yet at the H level, or even if it is at the H level, the data of the memory cell MC ₁ is not sufficiently read to the bit line pair BL ₁ , ▲ ▼ ₁ . , sense amplifier 32 _1, thereby amplifying the data in accordance with the asymmetry built into the self.

[Problems to be Solved by the Invention] Since the conventional data transfer method in the two-port memory device is executed as described above, when partial data transfer from the data register to the memory cell is performed, the data transfer is performed. There is a risk that the data stored in the masked memory cell may be destroyed.

The present invention has been made to solve the above problems, and when partial data transfer is performed between a memory cell and a data register, data is stored in a memory cell in which the data transfer is masked. The purpose is to prevent data corruption.

[Means for Solving the Problems] In the semiconductor memory device according to the present invention, a plurality of sense amplifier driving means are provided for each group of bit line pairs, and each of these sensor amplifier driving means is provided with a sense amplifier of a corresponding group. They are commonly connected and separated from the sense amplifiers of another group.

[Operation] In the present invention, the sense amplifier activation signal line pair extending from each sense amplifier driving means is separated between the group of sense amplifiers for executing data transfer and the group of sense amplifiers for which data transfer is masked. , The mutual influence is eliminated.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. In this embodiment, each transfer gate 33 ₀ , 33 ₁ is assumed to be controlled by either of the two transfer signals TG ₀ , TG ₁ . Note that, although FIG. 1 shows only one set of transfer gates controlled by each of the transfer signals TG ₀ and TG ₁ for simplification, a large number of transfer gates actually exist. Therefore, the transfer gates and the bit line pairs belonging thereto are divided into a first group controlled by the transfer signal TG ₀ and a second group controlled by the transfer signal TG ₁ . Two sets of control circuits are provided corresponding to these two groups. One of the control circuit 4 _0, the sense amplifier (first belonging to the first group
In the figure, it is provided for the sense amplifier 32 ₀ ) and the other control circuit 4 ₁ is provided for the second group of sense amplifiers (the sense amplifier 32 _{1 in} FIG. ₁ ). The control circuit 4 ₀ and the sense amplifier 32 ₀ belonging to the first group are connected by a sense amplifier activation signal line pair SD ₀ , ▲ ▼ ₀ . Further, the control circuit 4 ₁ and the sense amplifier 32 ₁ belonging to the second group are connected to the sensor amplifier activation signal line pair SD ₁ , ▲
▼ Connected by ₁ . What is important is that the sense amplifier activation signal line pair is divided between the groups. That is, in FIG. 1, the sense amplifier activation signal line pair SD ₀ , ▲ ▼ ₀ and SD ₁ , ▲ ▼ ₁ are electrically separated. As a result, it is possible to prevent the sense amplifiers from affecting each other and malfunctioning. The other configurations are shown in FIGS.
The device is similar to the conventional device shown in the figure, and corresponding parts are designated by the same reference numerals.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to the waveform chart of FIG. First, at time t ₀ , the precharge signal PR is set to the L level, then the transfer signal TG _{0 is set} to the H level, and the transfer signal TG ₁ is kept at the L level, as described in the conventional example of FIG. , Bit line pair BL ₀ , ▲
▼ potential difference between ₀ increases as data in the data register 21 _0. In response to this, the sense amplifier activation signal line pair SD ₀ , ▲ ▼ ₀ starts to change to H level and L level, respectively. However, the sense amplifier activation signal line pair SD _1, ▲ ▼ _1, the sense amplifier activation signal line pair SD _0,
Since it is separated from {circle around ( ₀₎ }, the pair of sense amplifier activation signal lines SD ₁ and {circle around ( ₁₎ } is kept precharged to Vcc / 2. Similarly, for bit line pair BL ₁ , ▲ ▼ ₁
Keep precharged to Vcc / 2. Then time t ₁
When the word line WL becomes H level in the memory cell MC
_The data stored in ₀ and MC ₁ is the bit line B
Read on L ₀ , BL ₁ . At this time, since the bit line BL ₀ is driven by the data register 21 ₀ via the transfer gate 33 ₀ , the data read from the memory cell MC ₀ is canceled. On the other hand, since the bit line BL ₁ is in the high impedance state, its potential changes according to the data read from the memory cell MC ₁ . After the period Δt ₁ for which this reading is sufficiently performed, when the sense amplifier enable signal SAE, ▲ ▼ is set to H level and L level, respectively, at time t ₂ , the sense amplifier activation signal line ▲
▼ ₀ , ▲ ▼ ₁ is driven to L level, and sense amplifier activation signal lines SD ₀ and SD ₁ are driven to H level. As a result, the sense amplifier 32 ₀ amplifies the data in the data register 21 ₀ and the sense amplifier 32 ₁ amplifies the data in the memory cell MC ₁ , and these data are rewritten in the memory cells MC ₀ and MC ₁ , respectively. .

Although the transfer gate is controlled by either of the two transfer signals in the above embodiment, the number of transfer signals may be three or more. In this case, the number of control circuits and sense amplifier activation signal line pairs may be increased according to the number of transfer signals. However, the sense amplifier activation signal line pair extending from a certain control circuit must be electrically separated from any sense amplifier activation signal line pair extending from another control circuit.

As described above, according to the present invention, the sense amplifier driving means is provided for each group of bit line pairs, and each sense amplifier driving means drives only the sense amplifiers of the corresponding group. Since it is electrically separated from the sense amplifiers of the other groups, the partial transfer of data from the data register to the memory cell does not affect the sense amplifiers of each group and the transfer is masked. It is possible to prevent the data stored in the memory cell from being destroyed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a partial configuration of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a waveform diagram for explaining the operation of the embodiment shown in FIG. FIG. 3 is a block diagram showing a schematic configuration of a conventional 2-port memory device. FIG. 4 is a diagram showing a circuit configuration of the transfer unit 3 and its peripheral circuits in the 2-port memory device shown in FIG. 5 and 6 are waveform diagrams for explaining the operation of the conventional device shown in FIG. FIG. 7 is a block diagram showing a schematic configuration of a conventional 2-port memory device capable of partial data transfer. FIG. 8 is a diagram showing a circuit configuration of a data transfer unit and its peripheral circuits in the conventional device shown in FIG. FIG. 9 is a waveform diagram for explaining the operation when data is transferred from the data register to the memory cell in the conventional device shown in FIGS. 7 and 8. In the figure, reference numeral 1 denotes RAM, 2 is SAM, 3 is the data transfer unit, 4 ₀
And 4 ₁ control circuit, SD, ▲ ▼ sense amplifier activating signal line, 11 is a memory cell array, WL denotes a word line, BL,
▲ ▼ is a bit line, MC is a memory cell, 12 is a row decoder, 13 is an I / O switch, 14 is a column decoder, 21 is a data register, 22 is a serial selector, 31 is a precharge circuit, 32 is a sense amplifier, 33 Indicates a transfer gate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomohiro Yamada 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation LSI Research Laboratory (56) Reference JP-A-63-50998 (JP, A)

Claims (1)

[Claims] 1. A plurality of word lines, a plurality of sets of bit line pairs arranged orthogonal to these word lines, and a plurality of memory cells arranged at the intersections of these word lines and bit line pairs. A memory cell array; a plurality of precharge circuits for precharging the bit line pairs; a plurality of data registers provided for the bit line pairs; and a connection between the bit line pairs and the data registers. A plurality of gate means, a transfer control line for controlling the gate means, a plurality of sense amplifiers for amplifying a potential difference appearing in each bit line pair, a sense amplifier driving means for driving the sense amplifiers, The bit line pair, the data register, the gate means, and the sense amplifier are divided into a plurality of groups, and each of the transfer control lines has a gate means of A plurality of groups are provided corresponding to the groups, and each transfer control line is selectively activated in response to a signal input from the outside in addition to the address signal. A plurality of corresponding sense amplifier driving means are commonly connected to the sense amplifiers of the corresponding groups, respectively, and are separated from the sense amplifiers of another group. Is transferred to the data register, the transfer control lines are selectively activated after activating all the sense amplifier driving states at the same time, and when transferring the data of the data register to the memory cell, the transfer is performed. A semiconductor memory device characterized by activating all the sense amplifier driving means at the same time after selectively activating a control line. .