JPH0766654B2 - Discontinuity extraction device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a discontinuity point extraction device, and more particularly to a discontinuity point extraction device used, for example, when editing a work mainly composed of video information.

(Prior Art) When editing a video signal and an audio signal, in particular, a video signal and an audio signal, for example, when producing a work mainly based on the video signal, the time code data, which is a time information signal, is pulsed. After performing signal processing such as code modulation (PCM), this time code data is recorded on an audio signal recording track of a recording medium on which the original video signal and audio signal are recorded, for example, a magnetic recording medium such as a magnetic tape. One step per frame, or from the vertical blanking period of the video signal recording track
A work tape in which the time code data is recorded so as to step by 1 at a time position after 12H or 14H (where H is a horizontal period) is manufactured.

In the following description, the case where the time code data is recorded in the recording portion of the vertical blanking period of the video signal recording track will be described as an example.

Further, the above-mentioned "video signal" is, of course, a black-and-white video signal or a color video signal, but is not limited to these signals and is a modulated digital signal obtained by pulse code modulating other analog information signals. Includes the digital signal existing at the video signal transmission position of the composite video signal.

Then, this work tape is reproduced, and only the necessary portion is recorded on another tape to create an edited tape. In this edited tape, the values of the above-mentioned time code data are discontinuous before and after the portion (editing point) where the editing is performed. Therefore, it is not possible to calculate the total recording time of the edited tape by simply obtaining the first time code data and the last time code data of the edited tape, and the time required for each cut is unknown. there were.

Therefore, each time the edited tape is played back, the playback of the edited tape is interrupted every time an edit point appears, and the still image display state (pause state) is entered, and the time code data played at that time is superimposed on the still image. Pauses the display (sets the priority so that the timecode data is displayed with priority over the still image and displays it in a superimposed manner), and the editor checks the displayed timecode data values and writes them down. ,
This work is continuously performed before and after each discontinuity point of the time code data, and the time and total recording time are calculated for each edit cut from the value of the time code data written at the end to create an edit sheet. It was

(Problems to be solved) Conventionally, as described above, each time an edited tape is played back and the editing point appears, the editing apparatus is made stationary and the value of the time code data displayed on the screen is confirmed. , It is difficult to find the edit point by looking at the playback image, and when checking the time code data on the screen, there is a possibility that the value of the time code data may be read incorrectly or written incorrectly. If the edited data is a tape that has been dubbed (copied) over, the playback image will deteriorate and it will be difficult to check the timecode data value. There is a problem that the transformation of the format is mistakenly regarded as a discontinuity point, and the judgment of the edited part, that is, the time code data A lot of mental and physical burdens are imposed on the determination of continuous points, and it is necessary to perform a complicated calculation after checking the edit points (discontinuous points) to calculate the time for each edit cut. Therefore, there is a problem that the efficiency of editing work is very poor.

Further, the conventional device for detecting the discontinuity of the time code data has a complicated structure and is expensive because it becomes a large-scale device.
It also had the problem of being uncommon.

Therefore, the present invention forcibly detects the discontinuity point of the time information signal by forcibly detecting the time information signal extracted from the reproduction signal obtained by reproducing the recording signal including the time information for each basic cycle of the reproduction signal. The edit points can be easily confirmed by distinguishing between, and the time information signal that is missing or has a deformed format due to a cause such as dropout can be interpolated.
It is possible to calculate the required time and the total required time of the period in which the time information signal is continuous from the information of the determined discontinuity without erroneously determining the discontinuity. It is an object of the present invention to provide a discontinuity extraction device that does not need to execute calculation and therefore can improve work efficiency during editing.

(Means for Solving Problems) The present invention provides a discontinuity extracting device having a structure as shown in FIG. 1 in order to solve the above problems. First
FIG. 1 is a block system diagram of an embodiment of a discontinuous extraction device according to the present invention. The discontinuous extraction device shown in FIG. 1 is an extraction means (time code reader 2) for extracting this time information signal (time code data) from a reproduction signal obtained by reproducing an information recording signal containing time information (time code). ), A recording element (RAM18) for recording the time information signal obtained by the extracting means, and a control means (CPU9) for controlling the recording operation of the recording element.
A display signal generating means (VDP11) corresponding to the time information signal recorded in the recording element, and generating a display signal of the same form as the reproduction signal, and the output signal from the display signal generating means. A synchronous coupling means (synchronous coupling circuit 12) for synchronously coupling a display signal to the reproduction signal, and the control means (CPU9) is configured to generate the display signal after synchronously coupling the display signal and the reproduction signal. Means or a signal of a unit transmission cycle of the reproduction signal (for example, a vertical synchronization signal), which is supplied from one of the means and the synchronous coupling means.
The following operation is forcibly performed, that is, when the continuity of the time information signal obtained by the extraction means is checked and a discontinuity point is detected, the cause of this discontinuity point is the lack of the time information signal. , It is determined by the change of the sequence of the time information signal, and when the time information signal is missing, the time information signal is missing from the time information signal recorded in the recording element at a temporal position before and after the missing time information signal. An operation of interpolating a time information signal and recording it again in the recording element, and recording the time information signal before and after the discontinuity point as data of the discontinuity point in the recording element when the sequence of the time information signal changes. I do.

(Examples) FIG. 1 is a block system diagram of an embodiment of the discontinuity extracting device according to the present invention, and FIG. 4 is a flow chart for explaining the operation of the discontinuity extracting device shown in FIG. Is.

In FIG. 1, 1 is a video tape recorder (hereinafter referred to as VT
The video signal output from the video signal output terminal V1out of VTR 1 is supplied to the video signal input terminal V2in of the time code reader 2 and the audio signal output terminal A of VTR 1
The audio signal output from 1out is supplied to the audio signal input terminal A5in of the monitor 5.

Further, the video signal input terminal V1in and the audio signal input terminal A1in of the VTR 1 are supplied with the video signal and the audio signal from the video signal output terminal V3out and the audio signal output terminal A3out of the VTR 3, and the VTR 1 is supplied from the VTR 3 The recorded video and audio signals are edited and recorded. Therefore, the time code data output from VTR 1 has discontinuities.

The time code reader 2 reads the time code data from the video signal supplied to the video signal input terminal V2in of the time code reader 2 and generates the corresponding character signal C for displaying the time code data. The video signal supplied from 1 is mixed in the mixing circuit 4, and is supplied from the character signal superimposed video signal output terminal V2wc of the time code reader 2 to the video signal input terminal V5in of the monitor 5.

Therefore, an image in which time code data is superimposed on the reproduced image of VTR 1 is reproduced and displayed on the monitor 5.

The video signal output from VTR 1 input to the video signal input terminal V2in of the time code reader 2 is supplied from the return terminal RE of the time code reader 2 to the video signal input terminal V6in of the monitor 6.

Since the video signal supplied to the monitor 6 is a video signal in which the character signal C is not superimposed by the time code reader 2, only the edited image is reproduced and displayed on the monitor 6.

Note that only video signals are supplied to the monitor 6, and audio signals are not supplied.

The time code reader 2 separates the time code data from the video signal or the video signal supplied from the VTR 1 and outputs it as a 4-bit serial data signal from the data input / output terminal (DATA I / O). The code data (4-bit serial data signal) is input to the interface circuit 7, converted into a data signal in a form that can be taken into the personal computer 8 by the interface circuit 7, and then the central processing unit (hereinafter referred to as CPU) of the personal computer 8. ) 9 through the input / output port (I / O) 10.

Further, the field signal FI is output from the interface circuit 7.
ELD, advance notice signal Rout, and clock signal WR are also transmitted.

The time code data taken into the personal computer 9 is subjected to predetermined signal processing by the CPU 9, a recording element such as a random access memory (RAM18), and a video display processor (hereinafter referred to as VDP) 11. (For example, after being converted as a predetermined character signal),
The R, G, B, Ys and Ym signals are supplied to the video signal input terminals R, G, B, Ys and Ym of the monitor 6.

The video signal output terminal V6out of the monitor 6 outputs the video signal supplied from the VTR 1 to the video signal input terminal V6in of the monitor 6 via the time code reader 2.

The video signal output from the video signal output terminal V6out of the monitor 6 is supplied to the sync separation circuit 13 in the sync coupling circuit 12 in the personal computer 8, and the sync signal separated in the sync separation circuit 13 is supplied to the phase detection circuit 14. It is supplied to one input terminal.

The other input terminal of the phase detection circuit 14 is supplied with the synchronization signal separated from the output signal of the VDP11, and the phase detection circuit 14 supplies the synchronization signal supplied to one input terminal and the other input terminal. Then, a phase error voltage corresponding to the phase difference between the two signals (a voltage that reduces the error between the two signals) is output.

A voltage controlled oscillator (hereinafter referred to as VCO) 15 outputs a signal having a frequency corresponding to the phase error voltage supplied from the phase detector 14 to VDP 11.

Therefore, the phase detection circuit 14, the VCO 15, and the VDP 11 form a PLL (phase locked loop) circuit, and a signal supplied to one input terminal of the phase detection circuit 14 is supplied to the other input terminal. The signals are synchronized and the sync separation circuit
The synchronization signal output from 13 is also supplied to the vertical synchronization signal separation circuit 19, and the VDP 11 operates using the vertical synchronization signal supplied from the vertical synchronization signal separation circuit 19. That is, VDP11
Since the vertical sync signal of the video signal output from the monitor 6 is synchronized with the vertical sync signal of the video signal output from the video signal output terminal V6out of the monitor 6,
The reproduced image in which the time code data is superimposed on the video signal supplied from is displayed.

Further, the vertical synchronizing signal (V sync) of the video signal output from the VDP 11 is supplied to the interrupt input terminal INT of the CPU 9.

The video signal and audio signal before editing are supplied from the video signal output terminal V3out 'and audio signal output terminal A3out' of the VTR 3 to the video signal input terminal V16in and audio signal input terminal A16in of the monitor 16.

VTR 1 and VTR 3 are connected to the remote control signal input terminals R of the respective VTRs from the remote control device 17.
The operation is controlled by the control signal supplied to M.

FIG. 2 is a diagram for explaining the operation of the discontinuity point extracting device shown in FIG. 1, and FIG. 3 is an enlarged view of a portion surrounded by an ellipse in FIG.

The time code data is subjected to signal processing such as PCM, and is recorded on an audio signal recording track formed on a recording medium such as a magnetic tape every frame, or on a video signal recording track in a vertical period of a video signal (see FIG. Each composite sync signal shown in A) is recorded twice as shown in FIG. 2B.

The time code reader 2 shown in FIG. 1 described above extracts the time code data from the recording signal and decodes it.

More specifically, the time code reader 2 is shown in FIG. 2 (C) immediately after reading the VITC (Vertical Internal Time Code) which is the time code data shown in FIG. 2 (B) contained in the video signal. Field signal FIELD, second
The time code data transmission and the notice signal Rout shown in FIG. 3D (FIG. 3A) are transmitted.

In addition, the VITC described above will be explained in more detail.
TC is, for example, time information such as hours, minutes, seconds on the video signal,
It is recorded as a 90-bit serial data signal composed of frame information, synchronization bits, error correction code, etc. When the time code reader 2 reads this VITC, it reads VI
TC is output as a data signal in units of 4 bits from the output terminal DATA I / O in synchronization with the clock signal WR shown in FIG. 2 (E) (FIG. 3 (B)).

The field signal FIELD shown in FIG. 2C is VTR.
The video signal sent from 1 becomes L level in the even field, and becomes H level in the odd field, and the advance notice signal Ro for sending the time code data shown in FIG.
ut becomes L level for a predetermined period immediately after reading VITC shown in FIG. 2B, and normally becomes H level (including the case where VITC cannot be read).

When the time code data is read, the time code data (4-bit serial data signals D _{0 to} D ₃ ) shown in FIG. 3 (C) (FIG. 2 (F)) is shown in FIG. 3 (B). ) (Fig. 2 (E)) and is transmitted in synchronization with the clock signal WR.

Specifically, at the falling edge of the clock signal WR (FIG. 3 (B)), each bit of the 4-bit serial data signals D _{0 to} D ₃ (FIG. 3 (B)) which is time code data is taken. If, for example, a 64-bit shift register is used, 1
4bit data can be taken in simultaneously with one clock signal.

Note that FIG. 2 shows the two VITCs (second
First VITC of VITC indicated by a ₁ and a ₂ in the figure (B)
(VITC indicated by a ₁ in Fig. 2 (B))
The second two VITCs sent out (b ₁ , b ₂ in Fig. 2 (B))
Of the VITC shown in (2), the second VITC (VITC shown in b2 in FIG. 2B) is read, and the two VITC sent to the third (c in FIG. 2B) are read. It shows the case where both VITC shown in ₁ and c ₂ could not be read.

Third VITC (VIT indicated by c ₁ and c ₂ in Fig. 2 (B)
The video signal transmitted immediately after C) is an odd field, and the field signal FIELD shown in FIG.
D should be at H level, but because VITC could not be read, field signal FIELD was switched at the field switching point.
D does not reverse and L level continues.

In addition, because the third VITC could not be read, the second
Neither the advance notice signal Rout shown in FIG. 2D nor the 4-bit serial data signal which is the time code data shown in FIG. 2F is output immediately after the third VITC is transmitted.

By the way, in the method of polling and detecting the advance notice signal Rout supplied from the time code reader 2 using the CPU, when the time code data cannot be read, neither the time code data nor the advance notice signal Rout is sent out. Therefore, the CPU cannot immediately detect the missing time code data.

If the CPU 9 is interrupted during or immediately before the advance notice signal Rout is transmitted, there is a possibility that the advance notice signal Rout may pass during the interruption process and may not be detected.

Therefore, the video signal output from the VDP 11 is synchronized with the video signal including the time code data (the video signal supplied from the VTR 1).

In other words, as shown in FIG. 1, the sync separation circuit 13, the phase detection circuit 14, and the VCO 15 are used as the synchronous coupling circuit 12 to generate V.
Vertical sync signal of playback video signal output from TR 1 and VDP1
Since the vertical sync signal of the video signal output from 1 is synchronized, and the vertical sync signal (V sync) of the video signal output from VDP11 is supplied to the interrupt input terminal INT of CPU 9, 9 is interrupted every cycle of the vertical synchronizing signal, and the interrupt process is performed.

Also, the timing at which the 4-bit serial data signal, which is time code data, is sent out together with the advance notice signal Rout from the time code reader 2 is 12H immediately after the vertical synchronization signal is transmitted.
Or since it is set to be immediately after 14H, if the CPU interrupt process is set to the time code data extraction process, specifically, if set to the process of detecting the advance notice signal Rout,
Since the CPU 9 is interrupted for each vertical sync signal, the time code data can be read reliably, and when it cannot be read, it is determined that a dropout has occurred, and when a dropout occurs, it is read before and after. The time code data can be corrected by interpolating the missing portion from the information of the time code data.

The read time code data can be recorded in the personal computer 8 and the length of each cut, extraction of edit points, etc. can be displayed on the screen based on the value of the time code data. It is also possible to output to an output device such as a printer.

Next, the control processing operation of the CPU 9 described above will be described with reference to FIG.

When the VTR 1 shown in FIG. 1 is in the reproduction state and the time code reader 2 extracts the time code data from the video signal reproduced and output from the VTR 1, the personal computer 8 starts the control processing operation and proceeds to step 20. Move.

In step 20, the CPU 9 determines whether or not the notice signal Rout is taken in from the data signal supplied from the time code reader 2, and if it is not taken in, (NO) is step 20.
Go back to step 21 and if yes (YES), go to step 21.

To step 21 CPU 9 sends warning signal Rou detected in step 20
The CPU 9 reads the time code data coming after t, records (stores) the read data in the RAM 18, and proceeds to step 22.

In step 22, the video signal output from monitor 6 and VDP1
Determine whether the video signal output from 1 is in phase synchronization. If the phase is synchronized (YES), the process proceeds to step 23. If the phase is not synchronized (NO), the process returns to step 20 again.

It should be noted that in FIG. 1, the signal for detecting whether or not the phases are synchronized is not supplied to the CPU 9, but if the predetermined time has elapsed after the synchronous coupling circuit 12 is activated, the two video signals become in the synchronized state. , CPU 9 operates according to a program that sets the time until the two video signals are in the synchronized state. Further, as another method for detecting synchronization, for example, the synchronization coupling device 12 may be configured to supply a synchronization detection signal to the CPU 9 for detection.

In step 23, it is determined whether or not there is an interrupt input from VDP11 to CPU 9, that is, whether or not the vertical synchronization signal (V sync) is supplied from VDP11 to the interrupt input terminal INT of CPU 9, and there is an interrupt. If (YES), the process proceeds to step 24, and if there is no interrupt (NO), the process returns to step 23 again.

In step 24, it is determined whether the advance notice signal Rout has arrived. If the advance notice signal Ruot has arrived (YES), the process proceeds to step 25. If the advance notice signal Rout has not arrived (NO), the process proceeds to step 26.

In step 25, the time code data output from the time code reader 2 is read, and the process proceeds to step 27.

In step 27, it is determined whether or not the format of the time code data read in step 25 is correct. If it is correct (YES), the process proceeds to step 28, and if it is not correct, the process proceeds to step 34.

In step 28, the time code data is recorded (stored) in the RAM 18 in the personal computer 8 and then in step 29.
Move to.

In step 29, the RAM 18 already has special data (this special data is data such as dropout or other time code loss or format change, and discontinuous time code data due to edit points). Judge whether it is stored and record (remember)
If yes (YES), move to step 30, and if not recorded (stored), move to step 31.

In step 30, correction is performed when the special data is generated due to dropout, and the process proceeds to step 31.

Specifically, it is already recorded (stored) in RAM 18 before the special data.
Data that has been received and data that comes after the special data are compared, and if there is a correlation between the two, convert this special data to the specified data and interpolate the data that has been dropped or the format has changed due to dropout, etc. To do.

In step 31, it is judged whether or not a discontinuity is found,
When the discontinuity point is found (YES), the process proceeds to step 32, and when the discontinuity point is not found (NO), the process proceeds to step 33.

In step 32, the data before and after the discontinuity point found in step 31 is used as the data of the discontinuity point at a predetermined address of the RAM 18, for example, the address where the time code data output from the time code reader 2 is fetched and stored (stored). It is recorded (stored) in an address different from that and moves to step 33.

In step 33, the storage area of the RAM 18 which records (stores) the time code data output from the time code reader 2 is updated, and the process returns to step 23.

In step 26, it is determined whether or not the period in which the warning signal Rout is not detected has passed a certain period. If it has passed (YES), the control processing operation is terminated, and if it has not passed (NO), the process proceeds to step 34. Move.

The fact that the control processing operation has moved to step 34 means that the time code data output from the time code reader 2 is missing due to a dropout or the like, or is not sent in the correct format. At this time, CPU 9 uses these data as special data in RAM.
Record (store) in 18 and move to step 31. That is, special data, which is data corresponding to the time position when the time code data is missing or when the time data in the correct format is not output, is recorded (stored).

Further, in the above embodiment, an example in which the vertical synchronization signal is supplied to the interrupt terminal INT of the CPU 9 as an interrupt signal has been described, but the present invention is not limited to this. The output signal of the timer circuit that outputs a signal having the same cycle as the vertical synchronizing signal supplied from the VDP 11 may be supplied to the interrupt input terminal INT of the CPU 9.

(Effects of the Invention) Since the present invention has the above-described configuration, it is possible to reliably determine the discontinuity point of the time information signal and easily confirm the edit point, and also to eliminate the dropout or the format due to a cause such as dropout. The transformed time information signal can be interpolated, the discontinuity points are not erroneously discriminated, and the required time and the total required time of the period in which the time information signal is continuous are calculated from the discriminated discontinuity point information. Therefore, there is an advantage that it is not necessary to execute the complicated calculation which has been necessary in the past, and therefore the working efficiency at the time of editing can be improved.

Furthermore, the present invention provides, as a control circuit, "a unit transmission synchronization of the reproduction signal, which is supplied from either the display signal generating means or the synchronous coupling means after the display signal and the reproduction signal are synchronously coupled. The control circuit that forcibly controls the recording operation of the recording element by the signal of "," can be used to extract the discontinuity points by using a general-purpose personal computer that can be synchronously coupled to the video signal, and with a simple configuration. It can be realized at low cost as a small device.

[Brief description of drawings]

FIG. 1 is a block system diagram of an embodiment of the discontinuity extracting device according to the present invention, FIG. 2 is a diagram for explaining the operation of the discontinuity extracting device shown in FIG. 1, and FIG. Figure 2 is an enlarged view of the part indicated by the oval in Figure 2, and Figure 4 is the CP shown in Figure 1.
7 is a flowchart for explaining a control processing operation of U 9. 1,3 …… Video tape recorder (VTR), 2 …… Time code reader, 4 …… Mixing circuit, 5,6,16 …… Monitor, 7 …… Interface circuit, 8 …… Personal computer, 9 …… Center Arithmetic processing unit (CPU), 10 ... I / O port (I / O), 11 ... Video display processor (VDP), 12 ... Synchronous coupling circuit, 13 ... Synchronous separation circuit, 14 ... Phase detection circuit, 15 ...... Voltage controlled oscillator (VC
O), 17 ... Remote control device, 18 ... Random access memory (RAM).

Claims (2)

[Claims] 1. An extracting means for extracting the time information signal from a reproduction signal obtained by reproducing an information recording signal containing time information, a recording element for recording the time information signal obtained by the extracting means, and the recording. Control means for controlling the recording operation of the element, display signal generating means for generating a display signal corresponding to the time information signal recorded in the recording element and having the same form as the reproduction signal, and the display signal generation A synchronous coupling means for synchronously coupling the display signal output from the means to the reproduction signal, the control means, after the synchronous coupling of the display signal and the reproduction signal, the display signal generating means and the By the signal of the unit transmission cycle of the reproduction signal supplied from either one of the synchronous coupling means, the following operation is forcibly performed, that is, the time information signal obtained by the extraction means is When the discontinuity point is detected by examining continuity, it is determined whether the cause of the discontinuity point is due to the lack of the time information signal or the change in the sequence of the time information signal, and the time information When the signal is missing, the time information signal missing from the time information signal recorded in the recording element at the temporal position before and after the missing time information signal is interpolated and recorded again in the recording element. The operation of recording time information signals before and after the discontinuity point in the recording element as data of the discontinuity point in the case of a change in the sequence of the discontinuity point. 2. The discontinuity extracting device according to claim 1, further comprising a timer circuit for outputting a signal at a time interval of a unit transmission cycle of the reproduction signal, wherein the output signal of the timer circuit is used to output the signal. A discontinuity extracting device, wherein a control circuit forcibly performs the above operation.