JPH0766211A - Dry etching - Google Patents

Abstract

PURPOSE:To prevent trenching in a contact hole when an insulating layer and a polysilicon layer are simultaneously exposed at an etching surface. CONSTITUTION:When a side-wall contact hole 10 is opened in a multilayer film composed alternately of insulating layers 2, 5 and 7 and polysilicon layers 3 and 6, the etching of the insulating layer 5 is stopped at a silicon nitride layer 4 (Si3N4) provided directly under the second polysilicon layer 3 having a narrower pattern than the width of an opening 9 in a resist mask 8. After that, the second polysilicon layer 3 is selectively etched, so that the etching surface is corrected to be flat, causing no trenching during the following etching process. The silicon nitride layer 4 can be directly above the second polysilicon layer 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method applied in the field of fine processing such as a semiconductor device manufacturing field, and in particular, even when material layers having different etching characteristics are simultaneously exposed on a surface to be etched during etching. The present invention relates to a technique capable of forming a contact hole for a sidewall contact having a good shape, for example, by suppressing an abnormal shape.

[0002]

2. Description of the Related Art In the field of manufacturing semiconductor integrated circuits, 256M DRAM or 64M which is a next-generation memory device.
To develop a large-capacity memory device of SRAM class, research on a fine processing technology for realizing a minimum processing size of 0.25 μm is underway. On the other hand, in parallel with the progress of such fine processing technology, the cell structure has become complicated in order to reduce the chip area. For example, in SRAMs that use TFTs (thin film transistors) as load elements, it is not uncommon for polysilicon wiring layers to be stacked in three layers, four layers, or more layers.

When interconnecting such multi-layered wiring, opening individual connection holes for each wiring layer not only complicates the process, but also limits the reduction of the cell area and the improvement of the degree of integration. Occurs. As a countermeasure against this, a so-called sidewall contact (plug-in wiring) structure has been proposed in recent years. This is because by opening a connection hole that penetrates a laminated film in which a wiring layer and an interlayer insulating film are alternately laminated a plurality of times and filling the connection hole with a plug, a plurality of wiring layers facing the side wall surface or the bottom surface of the connection hole can be formed. Is a structure for interconnecting.

For example, 1991 IEEE Inte
national Electron Device
s Meeting (IEDM 91) Proceedings, p. Four
77 to 480, an SRAM in which a sidewall contact is applied to a storage node is reported. This is because the driver transistor is penetrated through the bottom gate layer (second polysilicon layer) of the double gate type pMOS-TFT which is a load element and the TFT channel / power line layer (third polysilicon layer). A connection hole reaching the gate electrode (polycide film including the first polysilicon layer) is opened, and pM is formed on the inner wall surface thereof.
By connecting the top gate layer (4th polysilicon layer) of the OS-TFT, the upper and lower gate electrodes are connected,
Also, the TFT channel / power line layer is connected to the gate electrode of the driver transistor.

In the etching for opening the contact hole for making the sidewall contact as described above, typically, SiO _{x is used.}
It is necessary to alternately etch material layers having different etching characteristics, such as an inter-layer insulating film composed of and a wiring layer composed of polysilicon. The simplest way to do this is to move the wafer back and forth between an etching device for SiO _{x and} an etching device for polysilicon, and perform SiO _x / polysilicon selective etching in the former case and polysilicon / SiO _x selective etching in the latter case. Is.
In this specification, the material layer to be the target of selective etching is expressed in the form of (upper layer side layer) / (lower layer side layer). This method requires a plurality of etching apparatuses or etching apparatuses, but has an advantage that each thin film can be processed with good controllability.

[0006]

According to the above method,
As long as one of the SiO _x layer and the polysilicon layer is exposed on the entire surface of the etched region, etching proceeds without any problem. However, when the polysilicon layer is exposed only in a part of the region to be etched due to misalignment in the lithography process or layout reasons, there is a possibility that the shape of the contact hole may deteriorate. This problem will be described with reference to FIGS.

FIG. 6 is a perspective view showing the vicinity of the opening region of the sidewall contact hole on the wafer, and FIG. 7A is a sectional view taken along the line AA. This wafer consists of a second polysilicon layer (2nd p) on a silicon substrate (Si) 21.
interlayer insulating film (SiO ₂ ) 2 with embedded
Second and third polysilicon layers (3rd polySi) 2
4. An interlayer insulating film (SiO ₂ ) 24 is sequentially laminated, and a resist mask (PR) 26 having an opening 27 according to a predetermined hole pattern is formed thereon by photolithography. This opening 27
Is formed at the vertical projection position of the second polysilicon layer 23, and the opening diameter thereof is larger than the pattern width of the second polysilicon layer 23.

With respect to this wafer, first, the interlayer insulating film (SiO ₂ ) 25 is etched by an etching device for SiO _x , then the third polysilicon layer 24 is etched by an etching device for polysilicon, and further etching for SiO _{x is performed} . The interlayer insulating film 22 is etched by the apparatus to form the sidewall contact hole 28 part way. Here, the etching of the interlayer insulating film 22 must be stopped when the surface of the second polysilicon layer 23 is exposed even if a slight overetching should be performed.
However, as shown in FIG. 7B, since the interlayer insulating film 22 is exposed at the same time on both sides of the second-layer polysilicon layer 23, the etching of the interlayer insulating film 22 proceeds at this portion, and the trench portion 29 is formed. Will occur.

The wafer in this state is carried into the etching apparatus for polysilicon, and the second polysilicon layer 23 is removed as shown in FIG. 7 (c). Further, by etching the remaining portion of the interlayer insulating film 22 with an etching device for SiO _x , when the side wall contact hole 28 is completed, as shown in FIG.
As shown in (d), the underlying silicon substrate (Si) 2
The trench portion 29 is transferred to 1.

Although the problems when the underlayer is the silicon substrate (Si) 21 have been described above, when the underlayer is the W-polycide film, a more serious problem occurs as shown in FIG. FIG. 8 shows a W-polycide film in which the base of the interlayer insulating film 22 is formed on another interlayer insulating film 29,
That is, the first polysilicon layer (1st polyS)
i) 30 and a tungsten silicide layer (WSi _x) 3
The case where it is a laminated film of No. 1 is shown.

In this case, overetching of the interlayer insulating film 22 is started in a state where the tungsten silicide layer 31 is exposed in the peripheral portion of the sidewall contact hole 28 and the interlayer insulating film 22 remains near the center. However, here, the etching rate of the tungsten silicide layer 31 rapidly increases, and a large contact portion 32 is formed. This is Si
O _x etching generally joined by oxygen released from the interlayer insulating film 22 on the fluorine-based chemical species used in the high vapor pressure than W atoms of the tungsten silicide layer 31 WF _x WO _x F _y (oxyfluorides tungsten This is because it is quickly removed in the form of).

Therefore, it is an object of the present invention to provide a dry etching method capable of suppressing a shape abnormality even when material layers having different etching characteristics are simultaneously exposed in a region to be etched as described above. .

[0013]

The dry etching method of the present invention is proposed in order to achieve the above-mentioned object. At least one layer of a conductive material is provided in the middle of the first insulating film in the film thickness direction. At least one of the conductive material layers is used when etching a predetermined region of a laminated film having layers interposed therebetween while ensuring selectivity with respect to a substrate holding the laminated film.
A second insulating film having etching selectivity with respect to the first insulating film is stacked directly on the layer to form the stacked film,
This laminated film is etched until the second insulating film is exposed, the second insulating film is etched, and the conductive material layer immediately below the second insulating film is formed into the first insulating film. The step of etching is performed under the condition that the etching rate is equal to that of the insulating film and the step of etching the remaining portion until the substrate is exposed.

On the other hand, the second insulating film may be laid directly under the conductive material layer. In this case, the procedure for etching the laminated film is slightly different from that described above, and the steps of etching until the second insulating film and the conductive material layer immediately above the second insulating film are exposed and the step of etching the conductive material layer. And the step of etching the second insulating film and the step of etching the remaining portion until the substrate is exposed.

In any case, the second insulating film is
In the conductive material layer, the conductive material layer is formed at least closest to the substrate, or at least directly above or directly below the conductive material layer having an exposed area in the predetermined region smaller than the area of the predetermined region. Here, when there is only one conductive material layer, the second insulating film is, of course, formed immediately above or below this layer.

If a conductive material layer having an exposed area smaller than a predetermined area is located closest to the substrate, a second insulating film is formed immediately above or below this layer. Further, when there are a plurality of conductive material layers each having an exposed area smaller than a predetermined area, a second insulating film may be provided for each conductive material layer, but this also increases the number of film forming steps and the number of etching steps. It will increase. Practically, it is sufficient to provide the lowermost layer among the conductive material layers.

If the predetermined region is a connection hole, it is a typical process for forming the so-called sidewall contact hole as described above. In this case, a typical constituent material of the first insulating film is a SiO _x based material, and a typical constituent material of the conductive material layer is a silicon based material such as polysilicon or refractory metal polycide. In the present invention, a material having an etching selection ratio with respect to the SiO _x based material is required as a constituent material of the second insulating film, and a suitable material thereof is a silicon nitride (SiN _x ) based material.

[0018]

In the present invention, the etching selectivity between the first insulating film and the second insulating film is utilized to correct the surface to be etched flat when the second insulating film is exposed. The local progress of etching (trenching) of the first insulating film can be prevented. That is, the second insulating film functions as an etching stop layer or a buffer layer against overetching.

For example, the first insulating film is SiO _x and the second insulating film is
The insulating film is SiN _x, conductive material layer is composed respectively of polysilicon, when the second insulating film directly above the conductive material layer is laminated, the etching of the first insulating film a second insulating It is possible to stop at the surface of the film and then selectively remove only the second insulating film. That is, even if the first insulating film is exposed together with the conductive material layer after removing the second insulating film, the etched surface is flat. If the conductive material layer is removed under the condition that the first insulating film and the first insulating film can be etched at a constant rate, the surface to be etched is kept flat. Therefore, even after etching the remaining portion of the laminated film, trenching does not occur on the bottom surface of the connection hole.

On the other hand, when the second insulating film is laid directly under the conductive material layer, the etching of the first insulating film is stopped at the surface of the second insulating film and the conductive material layer immediately above the second insulating film. Then, only the conductive material layer can be selectively removed. At this point, the surface to be etched is also flat, and the final shape of the contact hole is not adversely affected.

If the second insulating film is first formed in contact with the lowermost conductive material layer, even if the shape abnormality occurs before the etching reaches this point, the exposed surface of the second insulating film is not exposed. The surface to be etched can be once flattened. Further, when it is known in advance which conductive material layer is exposed with an exposure area smaller than a predetermined area, by forming the second insulating film in contact with the layer, the occurrence of shape abnormality can be prevented. can do.

If this dry etching is performed in the region where the contact hole is formed, the sidewall contact / contact having a good shape is formed.
Holes can be formed.

[0023]

EXAMPLES Specific examples of the present invention will be described below.

Example 1 In this example, in the process of etching a side wall contact hole by etching an interlayer insulating film sandwiching two polysilicon layers, a silicon nitride layer is formed immediately above the lower polysilicon layer. This is an example in which the occurrence of abnormal shape is suppressed by stacking layers. This process will be described with reference to FIGS.

The wafer before etching is shown in FIG.
You This wafer is a second layer on a silicon substrate (Si) 1.
Polysilicon layer (2nd polySi) 3 was embedded
Interlayer insulation film (SiO₂) 2, silicon nitride layer (Si₃N
_Four) 4, interlayer insulating film (SiO₂) 5th and 3rd layer Polysilico
Layer (3rd polySi) 6, interlayer insulating film (SiO
₂) 7 is formed, and the laminated film
Predetermined hole pattern by photolithography on top
Resist mask provided with openings 9 according to
(PR) 8 is formed.

Here, the interlayer insulating film 2 is made of, for example, C.
A SiO ₂ film is flatly deposited on the silicon substrate (Si) 1 by the VD method, the polysilicon layer is patterned on the surface to form a second polysilicon layer 3, and the SiO ₂ film is further formed on the entire surface of the wafer. Is deposited and then flattened by a method such as etching back by RIE until the second polysilicon layer 3 is exposed, or by reducing the film thickness by a chemical mechanical polishing method.

The silicon nitride layer 4 is formed by plasma CVD.
It was formed to a thickness of about 50 nm by the method. The opening 9 is formed at the vertically projected position of the second-layer polysilicon layer 3, but the opening diameter is larger than the pattern width of the second-layer polysilicon layer 3.

The above laminated film was sequentially etched by the following steps to form the sidewall contact hole 10. The contents of etching in each step and a reference drawing are shown. Step 1: SiO ₂ / polySi selective etching [FIG. 1 (b)] Step 2: polySi / SiO ₂ selective etching [FIG. 1 (c)] Step 3: SiO ₂ / Si ₃ N ₄ selective etching [FIG. 2 (d)] Step 4: Si ₃ N ₄ / SiO ₂ selective etching [FIG. 2 (e)] Step 5: SiO ₂ -polySi constant velocity etching [FIG. 2 (f)] Step 6: SiO ₂ / Si selective etching [FIG. 3 ( g)] Here, the material layer for the selective etching is described in the form of (upper layer side layer) / (lower layer side layer).

Next, each step will be described.

[Step 1] First, the wafer shown in FIG. 1A was set in a magnetic field microwave plasma etching apparatus for SiO ₂ , and the interlayer insulating film 7 was etched under the following conditions as an example. c-C ₄ F ₈ Flow rate 50 SCCM Gas pressure 0.26 Pa Microwave power 1200 W (2.45 GH
z) RF bias power 230 W (800 kHz)
z) Wafer mounting electrode temperature −50 ° C.

The etching conditions are such that when the underlying third polysilicon layer 6 is exposed, a selection ratio of 100 or more can be obtained depending on the carbon-based polymer deposited on the exposed surface. By this step, the sidewall contact hole 10 having an anisotropic shape was formed partway. At this time, since the third polysilicon layer 6 is exposed on the entire bottom surface of the sidewall contact hole 10 as shown in FIG. 1B, the state shown in FIG. It hardly changed.

[Step 2] Next, the wafer was transferred to a magnetic field microwave plasma etching apparatus for polysilicon, and as an example, the third polysilicon layer 6 was etched under the following conditions. HBr flow rate 30 SCCM O ₂ flow rate 5 SCCM Gas pressure 0.65 Pa Microwave power 850 W (2.45 GH
z) RF bias power 10 W (2 MHz) Wafer mounting electrode temperature 0 ° C.

The etching conditions are SiO using a Br type etchant that cannot spontaneously extract Si atoms from Si--O bonds having high interatomic bond energy.
_{This is} a typical high selective etching condition for the ₂ type material layer. As a result, as shown in FIG. 1C, the third polysilicon layer 6 was selectively removed, and the underlying interlayer insulating film 5 was exposed.

[Step 3] Next, the wafer is again made of SiO 2.
Returning to the etching apparatus for ₂ , the interlayer insulating film 5 was etched under the following conditions as an example. C ₆ F ₆ Flow rate 50 SCCM Gas pressure 0.65 Pa Microwave power 1200 W (2.45 GH
z) RF bias power 200 W (800 kHz)
z) Wafer mounting electrode temperature −50 ° C.

Here, originally, the C / F ratio (C atom in the molecule is
C with a large ratio of the number of atoms to the number of F atoms)₆F ₆(Hexafluoro
(Benzene) is efficiently dissociated in ECR plasma to form C
F_x ⁺While producing a large amount of₃N_FourSystem material layer
F that causes a decrease in selectivity to^*The amount of
Hold down. Therefore, maintain a practical etching rate.
Approximately 30 selections for the silicon nitride layer 4 while holding
The ratio can be secured, as shown in Fig. 2 (d).
Then, stop the etching on the exposed surface of the silicon nitride layer 4.
I was able to

In order to thoroughly dissociate C ₆ F ₆ into ions as described above, so-called high-density plasma capable of achieving an ion density of 10 ¹¹ ions / cm ³ or more is required. As the high-density plasma, in addition to the ECR plasma used in this embodiment, helicon wave plasma, IC
P (Inductively Coupled Pla)
sma), TCP (Transformer Coup)
red plasma), hollow-anode type plasma, helical resonator plasma, etc. can be used.

[Step 4] Next, the silicon nitride layer 4 was etched in the same etching apparatus for SiO ₂ by changing the etching conditions as described below as an example. CH ₃ F flow rate 50 SCCM Gas pressure 0.23 Pa Microwave power 850 W (2.45 GH
z) RF bias power 150 W (800 kHz)
z) Wafer mounting electrode temperature −50 ° C.

The base of the etching in this step is the second polysilicon layer 3 running in the center of the bottom surface of the sidewall contact hole 10 and the interlayer insulating film 2 exposed at both ends thereof. The CH ₃ F is a gas that enables high selective etching for both of them. That is, Si
Since CF _x ⁺ which is an etchant of O ₂ is hardly generated, a high selection ratio can be secured for the interlayer insulating film 2. Further, since the depositability is excellent, a high selection ratio can be secured for the second polysilicon layer 3 which cannot supply oxygen by depositing a carbon-based polymer on the exposed surface thereof.

Conventionally, the state shown in FIG. 2 (e) is Si.
Since it occurred during the selective etching of O ₂ / polysilicon, the etching of the interlayer insulating film in the peripheral portion proceeded to cause trenching. However, in the present invention, only the silicon nitride layer 4 should be selectively removed. It was possible to keep the etched surface flat.

[Step 5] Next, the etching conditions are further changed as follows by way of example in the same etching apparatus for SiO ₂ , and the interlayer insulating film 2 and the second polysilicon layer 3 are etched at a constant rate. It was C ₂ F ₆ flow rate 20 SCCM S ₂ F ₂ flow rate 30 SCCM Gas pressure 0.23 Pa Microwave power 850 W (2.45 GH
z) RF bias power 250 W (800 kHz)
z) Wafer mounting electrode temperature −50 ° C.

This condition is that S (sulfur) dissociated from S ₂ F _{2 is} generated so that oxygen supplied from the interlayer insulating film 2 does not increase the etching rate of the second polysilicon layer 3.
It is intended to capture oxygen in order to make both etching rates equal. By this step, as shown in FIG. 2F, the etched surface of the interlayer insulating film 2 could be exposed flat.

[Step 6] Finally, the remaining portion of the interlayer insulating film 2 was etched under the same conditions as in [Step 1] described above. As a result, as shown in FIG. 3G, the sidewall contact hole 10 having a good shape while maintaining a high selection ratio with respect to the underlying silicon substrate (Si) 1.
Was able to be completed.

This side wall contact hole 10 is formed by removing the resist mask 8 and then depositing, for example, a fourth polysilicon layer 11 on the entire surface of the wafer as shown in FIG. 3 (h). Could be embedded in.

Embodiment 2 In this embodiment, in the process of etching the interlayer insulating film sandwiching the two polysilicon layers to form the sidewall contact hole, a silicon nitride layer is formed immediately below the lower polysilicon layer. This is an example in which the occurrence of abnormal shape is suppressed by laying. This process will be described with reference to FIGS. 4 and 5. The reference numerals in FIGS. 4 and 5 are common to those in FIGS.

The wafer before etching is shown in FIG. This wafer has an interlayer insulating film (SiO ₂ ) 2 and a silicon nitride layer (Si ₃ N ₄ ) on a silicon substrate (Si) 1.
4, a second polysilicon layer (2nd polySi) 3 patterned into a predetermined shape, an interlayer insulating film (SiO 2).
₂ ) 5, 3rd polysilicon layer (3rd polyS)
i) 6, a resist mask (PR) in which a laminated film including an interlayer insulating film (SiO ₂ ) 7 is formed, and openings 9 are formed on the laminated film according to a predetermined hole pattern by photolithography. 8 is formed.

The pattern width of the second polysilicon layer 3 is smaller than the opening diameter of the opening 9.

The laminated film was sequentially etched by the following steps to form the side wall contact hole 10. The contents of etching in each step and a reference drawing are shown. Step 1: SiO ₂ / polySi selective etching [FIG. 4 (b)] Step 2: polySi / SiO ₂ selective etching [FIG. 4 (b)] Step 3: SiO ₂ / Si ₃ N ₄ selective etching [FIG. 4 (c)] Step 4: polySi / Si ₃ N ₄ selective etching [FIG. 5 (d)] Step 5: Si ₃ N ₄ / SiO ₂ selective etching [FIG. 5 (e)] Step 6: SiO ₂ / Si selective etching [FIG. 5] (F)] Next, each step will be described.

First, in step 1, the interlayer insulating film 7 is formed.
Subsequently, in step 2, the third polysilicon layer 6 was selectively etched. The etching conditions in these steps are as described in Example 1.

[Step 3] Next, the wafer was set in a magnetic field microwave plasma etching apparatus for SiO ₂ , and the interlayer insulating film 5 was etched under the following conditions as an example. c-C ₄ F ₈ flow rate 30 SCCM S ₂ F ₂ flow rate 10 SCCM N ₂ flow rate 10 SCCM gas pressure 0.26 Pa microwave power 1200 W (2.45 GH
z) RF bias power 200 W (800 kHz)
z) Wafer mounting electrode temperature −50 ° C.

In this step, S by c-C ₄ F ₈
In addition to io ₂ / polySi selective etching, S ₂ F ₂
The use of SiO ₂ and N ₂ also enables selective etching of SiO ₂ / Si ₃ N ₄ . This is because sulfur nitride compounds such as polythiazyl (SN) _x produced by the reaction of S released from S ₂ F ₂ and N released from N ₂ can be used for ensuring selectivity. Because.

This etching was stopped when the second polysilicon layer 3 and the silicon nitride layers 4 at both ends thereof were exposed, as shown in FIG. 4 (c). Conventionally, since the silicon nitride layer 4 does not exist, the interlayer insulating film 2 exposed at both ends of the second polysilicon layer 3 is etched and trenching occurs.

[Step 4] Next, the wafer was transferred to a magnetic field microwave plasma etching apparatus for polysilicon, and as an example, the second polysilicon layer 3 was etched under the following conditions. HBr flow rate 30 SCCM O ₂ flow rate 5 SCCM Gas pressure 0.65 Pa Microwave power 850 W (2.45 GH
z) RF bias power 10 W (2 MHz) Wafer mounting electrode temperature 0 ° C. These conditions are the same as in step 2 of Example 1, but the selection ratio is about 30 for Si ₃ N _{4 as} well. Can be secured. By this step, as shown in FIG. 5D, the second polysilicon layer 3 was selectively removed, and the surface to be etched could be made flat.

Thereafter, in step 5, the silicon nitride layer 4 is selectively etched as shown in FIG. 5E, and subsequently placed in step 6 to form the interlayer insulating film as shown in FIG. 5F. 2 was selectively etched. As a result, the sidewall contact hole 10 having a good shape could be completed.

The present invention has been described above based on the two examples, but the present invention is not limited to these examples. For example, the base of the laminated film is S as described above.
A W-polycide film may be used instead of the i substrate. In addition, it goes without saying that the details of the wafer configuration, the etching apparatus used, and the etching conditions can be changed as appropriate.

[0055]

As is apparent from the above description, by applying the present invention, the surface to be etched can be kept flat even when material layers having different etching characteristics are exposed at the same time during etching. . Therefore, it is possible to form a connection hole having a good shape even when a laminated film having a complicated multilayer structure is etched as in the process of forming a sidewall contact. As a result, the reliability of the sidewall contact can be improved and the degree of freedom in the layout of the wiring pattern on the semiconductor chip can be increased. The present invention greatly contributes to miniaturization and high integration of semiconductor devices such as memory elements.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing an example of a process in which the present invention is applied to sidewall contact hole processing in the order of the steps, and FIG. 1A shows a wafer before etching in which a resist mask is formed on a laminated film. A state, (b) shows a state where the interlayer insulating film is selectively etched, and (c) shows a state where the third polysilicon layer is selectively etched.

2A and 2B are schematic cross-sectional views showing the continuation of the process of FIG. 1, in which (d) is a state in which an interlayer insulating film is selectively etched, (e) is a state in which a silicon nitride layer is selectively etched, ( f) shows a state in which the interlayer insulating film and the second polysilicon layer are etched at a constant rate.

FIG. 3 is a schematic cross-sectional view showing the continuation of the process of FIG. 2, in which (g) is a state in which the interlayer insulating film is selectively etched, and (h) is a completed fourth-layer sidewall contact hole polysilicon. Represents the state of being embedded in layers.

FIG. 4 is a schematic cross-sectional view showing another example of the process in which the present invention is applied to the sidewall contact hole processing in the order of steps, in which (a) shows a resist mask formed on a laminated film before etching. A wafer state, (b) shows a state where the interlayer insulating film and the third polysilicon layer are selectively etched, and (c) shows a state where the interlayer insulating film is selectively etched.

5 is a schematic cross-sectional view showing a continuation of the process of FIG. 4, (d) showing a state in which the second polysilicon layer is selectively etched, and (e) showing a silicon nitride layer being selectively etched. The state and (f) show the state in which the interlayer insulating film is selectively etched.

FIG. 6 is a perspective view showing a configuration example of a conventional wafer in which two polysilicon layers are interposed in an interlayer insulating film.

FIG. 7 is a schematic cross-sectional view for explaining problems in the conventional sidewall contact hole processing, FIG. 7A is a state of a wafer before etching in which a resist mask is formed on a laminated film, and FIG. ) Is 2 during the etching of the interlayer insulating film.
A state in which trenches are formed at both ends of the second-layer polysilicon layer, (c) shows a state in which the second-layer polysilicon layer is removed, and (d) shows a state in which trenches are formed in the Si substrate. .

FIG. 8 is a schematic cross-sectional view for explaining another problem in the conventional sidewall contact hole processing, showing a state in which a touched portion is formed in the underlying WSi _x layer of the laminated film.

[Explanation of symbols]

1 ... Si substrate 2, 5, 7 ... Interlayer insulating film (SiO ₂ ) 3 ... Second polysilicon layer (2nd po)
lySi) 4 ... Silicon nitride layer (Si ₃ N ₄ ) 6 ... Third polysilicon layer (3rd po)
lySi) 8 ・ ・ ・ Resist mask (PR) 9 ・ ・ ・ Opening 10 ・ ・ ・ Sidewall contact hole 11 ・ ・ ・ 4th polysilicon layer (4th po)
lySi)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/90 C

Claims (8)

[Claims] 1. A laminated film having at least one conductive material layer interposed in the middle of the first insulating film in the film thickness direction, while ensuring selectivity with respect to a substrate holding the laminated film. In a dry etching method of etching a region, a second insulating film having etching selectivity with respect to the first insulating film is stacked immediately above at least one layer of the conductive material layer to form the stacked film, Etching the laminated film until the second insulating film is exposed; etching the second insulating film; and forming a conductive material layer immediately below the second insulating film into the first conductive film. The method of dry etching is characterized in that the step of etching is performed under the condition that the etching rate is equal to that of the insulating film and the step of etching the remaining portion until the substrate is exposed are performed separately. 2. The dry etching method according to claim 1, wherein the second insulating film is laminated in the conductive material layer, at least immediately above the conductive material layer closest to the substrate. 3. The dry film according to claim 1, wherein the second insulating film is laminated immediately above a conductive material layer having an exposed area at least in the predetermined region smaller than the area of the predetermined region. Etching method. 4. A laminated film having at least one conductive material layer interposed in the middle of a thickness direction of a first insulating film in a predetermined area while ensuring selectivity with respect to a substrate holding the laminated film. In the dry etching method of etching inside, a second insulating film having etching selectivity with respect to the first insulating film is laid directly under at least one layer of the conductive material layer to form the laminated film, The step of etching the laminated film is performed until the second insulating film and the conductive material layer immediately above are exposed, the step of etching the conductive material layer, and the second insulating film are etched. A dry etching method, characterized in that the step is divided into a step and an etching step of etching the remaining portion until the substrate is exposed. 5. The dry etching method according to claim 4, wherein the second insulating film is laid in the conductive material layer at least immediately below the conductive material layer closest to the substrate. 6. The dry film according to claim 4, wherein the second insulating film is laid directly under a conductive material layer whose exposed area in at least the predetermined region is smaller than the area of the predetermined region. Etching method. 7. The method according to claim 1, wherein the predetermined region is a region where a connection hole is formed.
The dry etching method according to item. 8. The method according to claim 1, wherein the first insulating film is made of a silicon oxide based material, the conductive material layer is made of a silicon based material, and the second insulating film is made of a silicon nitride based material. Item 8. The dry etching method according to any one of items 7.