JPH0766153A - Fabrication of semiconductor device - Google Patents

Fabrication of semiconductor device

Info

Publication number
JPH0766153A
JPH0766153A JP21279293A JP21279293A JPH0766153A JP H0766153 A JPH0766153 A JP H0766153A JP 21279293 A JP21279293 A JP 21279293A JP 21279293 A JP21279293 A JP 21279293A JP H0766153 A JPH0766153 A JP H0766153A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
layer
insulating film
gold layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21279293A
Other languages
Japanese (ja)
Inventor
Satoru Nakatsuka
悟 中塚
Mitsuo Okada
光雄 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP21279293A priority Critical patent/JPH0766153A/en
Publication of JPH0766153A publication Critical patent/JPH0766153A/en
Pending legal-status Critical Current

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  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To effect patterning of electrode wiring layer on a semiconductor substrate by including a step for forming a gold layer on a semiconductor substrate formed with an insulation film having a window, a step for immersing the semiconductor substrate formed with the gold layer into a hydrofluoric acid solution, and a step for washing the semiconductor substrate with water. CONSTITUTION:An insulation film 3 having a window 2 at a region for forming an electrode wiring layer is formed on a semiconductor substrate 1 on which elements are formed and then a gold layer 4 is formed thereon. When the semiconductor substrate 1 is immersed into a hydrofluoric acid solution, the insulation film is etched slightly and the insulation film 3 is eroded below the gold layer 4 which is thereby floated slightly. The semiconductor substrate 1 is then washed with water to remove only the gold layer 4 from the insulation layer 3 thus forming an electrode wiring layer of predetermined pattern. This method eliminates the steps for forming, patterning and removing photoresist film thus reducing the fabrication process.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

【0002】[0002]

【従来の技術】従来、例えばダイオード、トランジス
タ、IC等の素子が形成された半導体基板の表面に電極
配線層を形成する方法としては、一般的に図2(a)〜
(d)に示すように行われている。
2. Description of the Related Art Conventionally, as a method of forming an electrode wiring layer on the surface of a semiconductor substrate on which elements such as diodes, transistors and ICs have been formed, generally, FIG.
It is performed as shown in (d).

【0003】即ち、図2(a)に示すように、素子が形
成された半導体基板11の表面に、電極配線層を形成す
べき領域に窓孔12が設けられた酸化シリコン、窒化シ
リコン等の絶縁膜13を形成する。そして、図2(b)
に示すように、この窓孔12が形成された絶縁膜13上
に金、アルミニウム、チタン等の電極材料からなる電極
層14を蒸着した後、該電極層14上にフォトレジスト
膜15をパターンニングする。次に、図2(c)に示す
ように、この半導体基板11をヨウ素ヨウ化カリ溶液等
の所定のエッチング液に浸漬して絶縁膜13上の不要な
領域の金属層14を除去した後、図2(d)に示すよう
に、上記フォトレジスト膜15を所定の有機溶剤により
除去し、水洗して電極配線層のパターンニングをしてい
る。
That is, as shown in FIG. 2A, on the surface of a semiconductor substrate 11 on which elements are formed, a window hole 12 is provided in a region where an electrode wiring layer is to be formed. The insulating film 13 is formed. And FIG. 2 (b)
As shown in FIG. 5, after depositing an electrode layer 14 made of an electrode material such as gold, aluminum, titanium, etc. on the insulating film 13 having the window 12 formed therein, a photoresist film 15 is patterned on the electrode layer 14. To do. Next, as shown in FIG. 2C, after the semiconductor substrate 11 is immersed in a predetermined etching solution such as potassium iodine iodide solution to remove the metal layer 14 in an unnecessary region on the insulating film 13, As shown in FIG. 2D, the photoresist film 15 is removed by a predetermined organic solvent and washed with water to pattern the electrode wiring layer.

【0004】[0004]

【発明が解決しようとする課題】このように、上記のよ
うな従来の方法では、金属層をエッチングしてパターン
ニングすることで電極配線層を形成するために、金属層
上にフォトレジスト膜を形成し、これを精度良くパター
ンニングする等煩わしい工程が必須となっている。ま
た、金属層をエッチングするのに用いるエッチング液、
エッチング後にフォトレジスト膜を除去するのに用いる
有機溶剤等、特殊な溶液を複数用いる必要があるため
に、作業者に危険性が伴い、これら溶液類の管理等を厳
重にする必要もあった。
As described above, in the conventional method as described above, a photoresist film is formed on the metal layer in order to form the electrode wiring layer by etching and patterning the metal layer. A complicated process such as forming and patterning this with precision is essential. Also, an etching solution used for etching the metal layer,
Since it is necessary to use a plurality of special solutions such as an organic solvent used to remove the photoresist film after etching, there is a danger to the operator, and it is necessary to strictly manage these solutions.

【0005】本発明は、従来必須とされていたフォトレ
ジスト膜の形成、パターンニング及び除去等の工程の必
要なく、半導体基板上の電極配線層のパターンニングを
行う全く新しい方法を提供するものである。
The present invention provides a completely new method of patterning an electrode wiring layer on a semiconductor substrate without the steps of forming, patterning, and removing a photoresist film, which have been conventionally required. is there.

【0006】[0006]

【課題を解決するための手段】本発明者は、上記目的を
達成すべく鋭意研究を重ねた結果、窓孔を有する絶縁膜
が形成された半導体基板上に金属層を設けたとき、金属
層の半導体基板に対する密着性に比し、金属層の絶縁膜
に対する密着性が悪いことに着目し、殊にフッ酸溶液に
浸漬したときは、上記密着性(密着力)の差異がより明
確になることを見出した。
As a result of intensive studies to achieve the above object, the present inventor has found that when a metal layer is provided on a semiconductor substrate on which an insulating film having window holes is formed, the metal layer The adhesiveness of the metal layer to the insulating film is poorer than the adhesiveness to the semiconductor substrate, and the difference in the adhesiveness (adhesive force) becomes clearer, especially when immersed in a hydrofluoric acid solution. I found that.

【0007】即ち、本発明は、(イ)窓孔を有する絶縁
膜が形成された半導体基板上に金属層を形成する工程、
(ロ)上記金属層が形成された半導体基板をフッ酸溶液
に浸漬する工程、及び(ハ)上記フッ酸溶液に浸漬され
た半導体基板を水洗する工程を含むことを特徴とする半
導体装置の製造方法に係るものである。
That is, according to the present invention, (a) a step of forming a metal layer on a semiconductor substrate on which an insulating film having window holes is formed,
(B) Manufacture of a semiconductor device including a step of immersing the semiconductor substrate on which the metal layer is formed in a hydrofluoric acid solution, and (c) a step of rinsing the semiconductor substrate immersed in the hydrofluoric acid solution with water It relates to the method.

【0008】[0008]

【作用】電極配線層を形成すべき箇所に窓孔が形成され
た絶縁膜を半導体基板上に形成し、この半導体基板上に
金属層を形成し、この状態でフッ酸溶液に浸漬すると、
上記絶縁膜のみが僅かにエッチングされ、上記窓孔の部
分の金属層と半導体基板との密着力を良好に保持した状
態で、上記金属層と絶縁膜との密着力を低下させること
ができる。換言すれば、半導体基板上において、電極配
線層として必要な絶縁膜の窓孔部の金属層の密着力を良
好にして、除去すべき不必要な絶縁膜上の金属層の密着
力を一段と低下させることとなる。従って、これを水で
洗浄すれば、上記絶縁膜上の金属層のみが剥離除去さ
れ、上記窓孔部に形成された金属層が残り所定のパター
ンの電極配線層が形成されることとなる。
[Function] When an insulating film in which a window hole is formed at a place where an electrode wiring layer is to be formed is formed on a semiconductor substrate, a metal layer is formed on this semiconductor substrate, and the metal layer is immersed in a hydrofluoric acid solution in this state,
Only the insulating film is slightly etched, and the adhesive force between the metal layer and the insulating film can be reduced in a state where the adhesive force between the metal layer at the window hole portion and the semiconductor substrate is kept good. In other words, on the semiconductor substrate, the adhesion of the metal layer on the window portion of the insulating film required as the electrode wiring layer is improved, and the adhesion of the unnecessary metal layer on the insulating film to be removed is further reduced. Will be made. Therefore, if this is washed with water, only the metal layer on the insulating film is peeled and removed, and the metal layer formed in the window hole remains and an electrode wiring layer having a predetermined pattern is formed.

【0009】[0009]

【実施例】以下実施例を示すことにより、本発明の特徴
とするところをより詳細に説明するが、本発明がこれら
実施例に限定されることはない。
EXAMPLES The features of the present invention will be described in more detail by showing examples below, but the present invention is not limited to these examples.

【0010】図1(a)〜(d)に本発明の実施例を示
す。尚、本実施例では、金属層として金層を用いた。
1 (a) to 1 (d) show an embodiment of the present invention. In this example, a gold layer was used as the metal layer.

【0011】(イ)素子が形成された半導体基板1上
に、図1(a)に示すように、電極配線層を形成すべき
領域に窓孔2が形成された酸化シリコン、窒化シリコン
等の絶縁膜3(例えば、厚さ3.0μm程度)を形成
し、図1(b)に示すように、この半導体基板1上に金
層4(例えば、厚さ0.3μm程度)を蒸着法、スパタ
ッリング法等により形成する。このとき、上記金層4の
厚さを絶縁膜3の厚さの1/5程度以下とすることで、
上記金層4が絶縁膜3上と窓孔2の部分とで不連続とし
得るので、後の不要部(絶縁膜上)の金層4の除去を一
層容易とでき、より好ましい。尚、上記絶縁膜3とし
て、素子形成時に形成した絶縁膜を利用すればより効率
的である。
(A) As shown in FIG. 1A, on the semiconductor substrate 1 on which the element is formed, such as silicon oxide or silicon nitride having a window hole 2 formed in a region where an electrode wiring layer is to be formed. An insulating film 3 (for example, a thickness of about 3.0 μm) is formed, and a gold layer 4 (for example, a thickness of about 0.3 μm) is vapor-deposited on the semiconductor substrate 1 as shown in FIG. 1B. It is formed by the spattering method or the like. At this time, by setting the thickness of the gold layer 4 to about 1/5 or less of the thickness of the insulating film 3,
Since the gold layer 4 can be discontinuous on the insulating film 3 and the portion of the window 2, the removal of the unnecessary unnecessary gold layer 4 (on the insulating film) can be further facilitated, which is more preferable. It is more efficient to use an insulating film formed at the time of forming the element as the insulating film 3.

【0012】(ロ)次に、上記のようにして金層4を形
成した半導体基板1を、フッ酸溶液に浸漬(例えば、
0.5v/v%程度フッ酸水溶液に3分間程度浸漬)す
る。上記フッ酸溶液に浸漬された半導体基板1は、図1
(c)に模式図を示すように、その上面に形成された上
記絶縁膜3が僅かにエッチングされ、上記金層4下の上
記絶縁膜3が侵食された状態となり、上記絶縁膜上の上
記金層4が僅かに浮いた状態となり、上記絶縁膜3上に
形成された上記金層4のみ密着力が一段と低下し、剥離
し易くなる。このとき、上記金層4は、フッ酸溶液が比
較的低濃度のものなので殆ど影響を受けない。
(B) Next, the semiconductor substrate 1 on which the gold layer 4 is formed as described above is dipped in a hydrofluoric acid solution (for example,
Immerse in a hydrofluoric acid aqueous solution of about 0.5 v / v% for about 3 minutes). The semiconductor substrate 1 dipped in the hydrofluoric acid solution has the structure shown in FIG.
As shown in the schematic view in (c), the insulating film 3 formed on the upper surface of the insulating film 3 is slightly etched, and the insulating film 3 under the gold layer 4 is eroded. The gold layer 4 is slightly floated, and the adhesion force of only the gold layer 4 formed on the insulating film 3 is further reduced, and the gold layer 4 is easily peeled off. At this time, the gold layer 4 is hardly affected because the hydrofluoric acid solution has a relatively low concentration.

【0013】(ハ)そして、このように処理された半導
体基板1を水洗して、図1(d)に示すように、上記絶
縁膜3上の金層4のみが剥離除去され、所定のパターン
の電極配線層が形成される。本発明において、上記水洗
を超音波を用いて行えば、水洗時間を短縮でき、より効
果的である。
(C) Then, the semiconductor substrate 1 thus treated is washed with water, and as shown in FIG. 1 (d), only the gold layer 4 on the insulating film 3 is peeled and removed to form a predetermined pattern. The electrode wiring layer of is formed. In the present invention, if the above-mentioned water washing is performed using ultrasonic waves, the water washing time can be shortened, which is more effective.

【0014】尚、上記実施例は、金属層として金層を用
いた場合について示したが、本発明はこれに限らず、フ
ッ酸溶液により全くエッチングされない金属、或いはフ
ッ酸溶液に対するエッチングレートが絶縁膜のエッチン
グレートに比して1/20程度以下と低い金属であれば
金属層として用いることができる。
Although the above-mentioned embodiment shows the case where the gold layer is used as the metal layer, the present invention is not limited to this, and a metal which is not etched at all by a hydrofluoric acid solution or an etching rate for a hydrofluoric acid solution is insulated. Any metal that is as low as about 1/20 or less of the etching rate of the film can be used as the metal layer.

【0015】[0015]

【発明の効果】本発明によれば、従来に比してフォトレ
ジスト膜の形成、パターンニング及び除去等の工程を必
要なくして電極配線層を形成し得、製造工程を一段と削
減できる。
According to the present invention, the electrode wiring layer can be formed without the need for the steps of forming the photoresist film, patterning, and removing, as compared with the prior art, and the manufacturing steps can be further reduced.

【0016】また、フッ酸溶液を低濃度で用いるので、
従来のエッチング液、有機溶剤等の特殊な溶液と違い作
業の安全性を向上でき、しかも溶液管理が容易となる。
Since the hydrofluoric acid solution is used at a low concentration,
Unlike conventional etching solutions, special solutions such as organic solvents, work safety can be improved, and solution management becomes easier.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例の製造工程を示す説明図である。FIG. 1 is an explanatory diagram showing a manufacturing process of an example.

【図2】従来の製造工程を示す説明図である。FIG. 2 is an explanatory diagram showing a conventional manufacturing process.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 窓孔 3 絶縁膜 4 金層 1 semiconductor substrate 2 window hole 3 insulating film 4 gold layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 (イ)窓孔を有する絶縁膜が形成された
半導体基板上に金属層を形成する工程、 (ロ)上記金属層が形成された半導体基板をフッ酸溶液
に浸漬する工程、及び (ハ)上記フッ酸溶液に浸漬された半導体基板を水洗す
る工程 を含むことを特徴とする半導体装置の製造方法。
1. A step of forming a metal layer on a semiconductor substrate on which an insulating film having a window hole is formed, and a step of immersing the semiconductor substrate on which the metal layer is formed in a hydrofluoric acid solution. And (c) a method of manufacturing a semiconductor device, which comprises a step of washing the semiconductor substrate immersed in the hydrofluoric acid solution with water.
JP21279293A 1993-08-27 1993-08-27 Fabrication of semiconductor device Pending JPH0766153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21279293A JPH0766153A (en) 1993-08-27 1993-08-27 Fabrication of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21279293A JPH0766153A (en) 1993-08-27 1993-08-27 Fabrication of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0766153A true JPH0766153A (en) 1995-03-10

Family

ID=16628462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21279293A Pending JPH0766153A (en) 1993-08-27 1993-08-27 Fabrication of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0766153A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7291278B2 (en) 2003-09-17 2007-11-06 Seiko Epson Corporation Electrode forming method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7291278B2 (en) 2003-09-17 2007-11-06 Seiko Epson Corporation Electrode forming method

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