JPH0764903A - Serial data loading port extension circuit - Google Patents

Abstract

PURPOSE:To lower the price by reducing the number of the I/O ports of a data loading circuit for loading data to a lot of devices to be controlled by one microcomputer. CONSTITUTION:A shift register(SR) for converting serial data signals SER outputted front the microcomputer to parallel data by the unit of 8 bits corresponding to clock signals and a storage latch(SL) for obtaining the parallel output of 8 bits are provided and the output is allocated to a gate G and binary codes A, B, C and D for distributing it respectively to two decoders (DC(1)) and (DC(2), data output (DT) and clock output (CL) and loaded to 32 devices to be controlled. Thus, from the microcomputer, just 3 bits of clocks, data and latch signals are outputted from three I/O ports.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data loading circuit used in electronic equipment utilizing a microcomputer (central processing unit), and for example, it is necessary to load serial data such as an IC for tone squelch or an IC for PLL synthesizer. The present invention relates to a serial data loading port expansion circuit used in a multi-channel wireless communication device or the like that uses a large number of certain devices. In a microcomputer control system, it is general to devise to reduce the number of I / O ports in order to pursue economy. The present invention relates to a serial data loading port expansion circuit having a reduced number of I / O ports.

[0002]

2. Description of the Related Art FIG. 3 is an explanatory diagram of a conventional data loading I / O port. When a single chip computer with a limited number of I / O ports is used as shown in FIG. 3A, an expensive type single chip computer with a large number of I / O ports is selected. Also, FIG.
As shown in (b), I / O port can be expanded
When using a chip computer, a relatively expensive PPI (Proglamabl) is used to secure the required number of I / O ports.
e Pelipheral Interface) and PIA (Proglamable Inte)
It uses multiple I / O ICs called rface adapters).

[0003]

Generally, the serial data loading port is constructed by a set of a clock output, a data output, and a latch enable output (also referred to as a data strobe output). Therefore, if there are n devices that need to load serial data, simply n
× 3 I / O ports are required. Further, even if the clock output line and the data output line can be shared, the number of I / O ports of n + 2 is still required, which is a problem as a factor for increasing the manufacturing cost of the device.

The object of the present invention is to solve the problem of the prior art that the manufacturing cost rises due to the increase in the required number of I / O ports. 16 or 3 serial data loading ports
It is to provide a serial data loading port expansion circuit that can be expanded in units of two.

[0005]

The serial data loading port expansion circuit of the present invention comprises three I / Os of a central processing unit.
16 serial signals each having a common clock output, a common data output, and a latch enable output for a clock signal, a serial data signal, and a latch signal whose one cycle is eight cycles of the clock signal output from the O port In order to expand to the data loading port output, the serial data signal input to the data signal input terminal is converted into eight parallel data according to the clock signal input to the clock signal terminal 8
Bit-serial-in / parallel-out shift register, 8-bit storage latch that inputs eight parallel data from the shift register and outputs according to the latch signal input to the latch signal terminal, and output from the storage latch 1 of the 8-bit output that is set as the gate input and 4 as the binary code input
A decoder that decodes to an output of 6 among the 8-bit outputs output from the 8-bit storage latch,
The first bit is the common clock output of the 16 serial data loading ports, the second bit is the common data output of the 16 serial data loading ports, and the 16 outputs from the decoder are Each of the 16 serial data loading ports is configured to be a latch enable output.

Further, a clock signal output from each of the three I / O ports of the central processing unit, a serial data signal, and a latch signal having one period of 8 periods of the clock signal are used as a common clock output and a common clock signal, respectively. Data output and latch enable output to 32 serial data loading port outputs, the serial data signal input to the data signal input terminal is converted into eight serial data loading ports according to the clock signal input to the clock signal terminal. 8-bit serial-in parallel-out shift register that converts to parallel data,
Two of the 8-bit storage latch that inputs eight parallel data from the shift register and outputs according to the latch signal input to the latch signal terminal and the 8-bit output that outputs from the storage latch, respectively. The first and second decoders are provided as gate inputs and are decoded as 16 outputs with four common binary code inputs, and the first of the 8-bit outputs output from the 8-bit storage latch is provided. A bit is used as a common clock output of the 32 serial data loading ports, and a second bit is used as a common data output of the 32 serial data loading ports, and is output from the first and second decoders 32. Are used as the latch enable outputs of the 32 serial data loading ports, respectively. It is characterized in that it has configured.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a connection diagram showing the configuration of an embodiment of the present invention. It is assumed that the data signal, the clock signal and the latch signal sent from the central processing unit and applied to the respective signal terminals are synchronized. First, a data signal is input from the data signal terminal D ₀ , and an 8-bit signal is input according to the clock signal input from the clock signal terminal C _0.
The data is sequentially taken into the serial-in / parallel-out shift register SR. Then, 8 cycles of the clock signal are 1
Outputs Q _{A to} Q _H of the 8-bit storage latch SL appear depending on the latch signal of the cycle. That is, due to the arrival of the latch signal input from the latch signal terminal L ₀ ,
Serial data signal is converted into a parallel output of 8-bit Q _A to Q _H. And so that the serial data output, to generate a latch enable output of the clock output and the maximum number of 32 by operating states independently of the "1" or "0" of these outputs Q _A to Q _H. Decoder DC
(1) and the decoder DC (2) are the same, and the 4-bit binary code inputs A, B, C, D are output as 16 outputs Y.
Decode and convert to _{0 to} Y ₁₅ . Gate input G is "1" if the output Y ₀ to Y ₁₅ is permitted. As an operation example, G =
"1", A = "1", B = "1", C = "1", D =
When “0” is input, the output Y ₀ = “1” and the other outputs are “0”.

The function allocation of the eight outputs Q _{A to} Q _H of the 8-bit storage latch SL will be summarized and described below. Q _A is common to 32 serial data loading ports SDLP _{0 to} SDL _31. Clock output C
It is L. Q _B is a data output DT common to 32 serial data loading ports SDLP _{0 to} SDL ₃₁ .
Q _C becomes the gate input G of the decoder DC (1),
Serial data loading ports SDLP _{0 to} SDL ₁₅
Is an output for selecting. Q _D is the decoder DC
It becomes the gate input G of (2) and is an output for selecting the ₁₆ serial data loading ports SDLP _{16 to} SDL ₃₁ . Q _E is the binary code input A (2 ⁰ ) of the decoders DC (1) and DC (2). Q _F is the decoder D
Binary code input B (2 ¹ ) of C (1) and DC (2)
Is. Q _G is the binary code input C (2 ² ) of the decoders DC (1) and DC (2). Q _H is the decoder DC
It is the binary code input D (2 ⁴ ) of (1) and DC (2).

FIG. 2 is a time chart showing an operation example of the serial data loading port expansion circuit according to the present invention. This is, for example, the data loading port SDL
From P ₂₉ , the clock output CL, as shown in FIG.
It shows the contents of signals to be output by the central processing unit when the data output DT and the latch enable output LE ₂₉ are to be obtained. The forward edge trigger signal applied to the latch signal terminal L ₀ shown in FIG. 2A is the latch input RCK, and the data signal terminal D ₀ is serially connected to the data signal terminal D ₀ at the timing shown in FIG. 2C. Input SE
R, and clock input S at clock signal terminal C ₀
CK is applied. The contents of the serial input SER are shown in Fig. 2.
As shown in (b), the 8-bit data corresponding to Q _H is structured so that the head is the first, and the latch input R
It must be synchronized to the clock input SCK at a rate of 8 times CK. Of the latch input RCK (forward edge trigger signal) of FIG. 2A, the relationship between the serial input SER and the clock input SCK in the section indicated by A and B is shown in FIG. It can be easily understood that the content of the input SER is shown in FIG.

In the above embodiment, the three I / O port inputs are expanded to 32 ports.
When the O port input is expanded to 16 output ports, the decoder (2) may be omitted and the decoder may be configured by one decoder (1).

[0011]

As described in detail above, according to the present invention, a maximum of 32 serial data loading ports can be obtained by allocating only three I / O ports. Therefore, it is not necessary to select an expensive single-chip computer having a large number of I / O ports, and it is not necessary to add a plurality of relatively expensive I / O ICs in a multi-chip computer system. The cost can be reduced. Since the circuit of the present invention is realized by three general-purpose family ICs, an equivalent I /
It costs about half the price of I / O ICs with the number of O ports.

[Brief description of drawings]

FIG. 1 is a connection diagram showing a configuration of an embodiment of a circuit of the present invention.

FIG. 2 is an operation time chart in the present invention.

FIG. 3 is an explanatory diagram of a conventional method of securing a required number of I / O ports.

[Explanation of Codes] C ₀ Clock signal terminal from central processing unit D ₀ Data signal terminal from central processing unit L ₀ Latch signal terminal from central processing unit SR 8 bits Serial-in / parallel-out shift register SER 8 bits・ Serial input of parallel-in / parallel-out shift register SCK 8 bits ・ Clock input of serial-in parallel-out shift register Q _A 'to Q _H ' 8-bit ・ 8 outputs of serial-in parallel-out shift register SL 8-bit storage latch RCK 8-bit storage latch latch input D _{0 to} D ₇ 8-bit storage latch 8 inputs Q _{A to} Q _H 8-bit storage latch 8 outputs DC (1), DC (2) 4-bit Decoder G Deco that decodes Binar code input into 16 outputs Common Da gate input A, B, C, the serial data loading port of the serial data loading port DT 32 output SDLP ₀ ~SDLP ₃₁ 32 4-bit binary code of D decoder input Y ₀ to Y ₁₅ decoder 16 Data output CL Common clock output to serial data loading port of 32 LE _{0 to} LE ₃₁ 32 latch enable output of serial data loading port

Claims (2)

[Claims] 1. A common clock output, a common clock signal, a serial data signal output from each of three I / O ports of a central processing unit, and a latch signal whose one cycle is eight cycles of the clock signal. In order to expand to 16 serial data loading port outputs consisting of a data output and a latch enable output, the serial data signal input to the data signal input terminal is divided into eight according to the clock signal input to the clock signal terminal. An 8-bit serial-in / parallel-out shift register for converting to parallel data, and an 8-bit storage latch for inputting eight parallel data from the shift register and outputting according to the latch signal input to a latch signal terminal , 8 bits output from the storage latch A decoder for decoding one of the four outputs as a gate input and four as a binary code input into 16 outputs,
Of the 8-bit output from the bit storage latch, the first bit is the common clock output of the 16 serial data loading ports, and the second bit is the common clock of the 16 serial data loading ports. 16 output as data output from the decoder
The serial data loading port expansion circuit is configured so that each of the outputs is a latch enable output of the 16 serial data loading ports. 2. A common clock output, a common clock signal, a serial data signal output from each of three I / O ports of the central processing unit, and a latch signal whose one cycle is eight cycles of the clock signal. In order to expand to 32 serial data loading port outputs consisting of a data output and a latch enable output, the serial data signal input to the data signal input terminal is converted into eight serial data loading ports according to the clock signal input to the clock signal terminal. An 8-bit serial-in / parallel-out shift register for converting to parallel data, and an 8-bit storage latch for inputting eight parallel data from the shift register and outputting according to the latch signal input to a latch signal terminal , 8 bits output from the storage latch Output from the 8-bit storage latch. Two output signals are provided as gate inputs, and four are provided as common binary code inputs, and first and second decoders are provided to decode each to 16 outputs. Of the 8-bit output, the first bit is the common clock output of the 32 serial data loading ports, and the second bit is the common data output of the 32 serial data loading ports. , A serial data loading port expansion circuit configured such that 32 outputs output from the second decoder are respectively latch enable outputs of the 32 serial data loading ports.