JPH0764513A - Device for driving liquid crystal - Google Patents

Abstract

PURPOSE:To eliminate the need of a timing generation circuit by reading out the data generating a signal selecting a row stored in the same row address from a display, storage means and generating the signal (common output) selecting the row from the data. CONSTITUTION:A display pattern to repeat the lighting/putting-out for each row is written in a display RAM 113, and a row address showing a first row is outputted from a row address increment circuit 114, and the first row data (the display data and the common data) are read out from the display RAM 113. The display data S1-S32 are supplied to a segment output circuit 115, and segment signals are outputted as segment outputs S1-S32. On the other hand, the common data t1-t16 are supplied to a common output circuit 117. Then, the rows are scanned successively, and the display of one frame is ended by 16 times of scanning. In such a manner, by inputting the output of the display RAM 113 to the common output circuit 117, since common outputs H1-H10, are obtained, a common timing generation circuit is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive device which can be widely used in electronic equipment equipped with a liquid crystal display device.

[0002]

2. Description of the Related Art A liquid crystal display device is one of the display devices that has rapidly spread in recent years, and is used in many electronic devices in place of the conventional display devices such as cathode ray tubes and CRTs.

Various types of driving methods for such a liquid crystal display device are known. Among them, the driving method of performing AC driving in time division is widely used. This is for a liquid crystal display device including a row electrode group (scanning electrode group or common electrode group) and a column electrode group (signal electrode group or segment electrode group) that are arranged to face each other in a matrix with a liquid crystal layer interposed therebetween. Each common electrode is line-sequentially applied with a selection waveform, while the segment electrodes are applied with an ON waveform or an OFF waveform in synchronization with the selection waveform of the common electrode. By such an operation, all the pixels formed by the intersections of the common electrodes and the segment electrodes can be brought into an arbitrary display state.

A liquid crystal cell of 16 × 32 dots is shown in FIG.
A block diagram of a liquid crystal driving device for driving by a 6-level driving method which is one of such driving methods is shown.

In FIG. 3, a liquid crystal driving device 31 divides a reference clock signal CK ₀ input from a clock input CK to generate a plurality of divided clock signals CK _{1 to} CK ₄ , a frequency dividing circuit 311. 16 rows x 32 columns display RAM 31
3. A row address is generated when reading data from the data selector 312 and the display RAM 313, which writes the display data input from the data inputs D _{0 to} D ₇ to the display RAM 313 according to the address input from the address inputs A _{0 to} A _5. A row address increment circuit 314, a segment output circuit 315 that creates a segment signal from the display data read from the display RAM 313 for each row, and outputs the segment signal to the segment outputs S _{1 to} S _32. CK ₀ ~CK ₃ is input, the common timing signal from the common timing generation circuit 316 and the common timing generation circuit 316 generates a common timing signal t ₁ ~t ₁₆ is a scanning timing of each line based on this t ₁ ~t ₁₆ is inputted, co based on this The emission output H ₁ to H ₁₆ made from the common output circuit 317 for outputting the common signal. 32 is 16 x 32
This is a liquid crystal cell of dots, and segment outputs S _{1 to} S ₃₂ are connected to each column, and common outputs H _{1 to} H ₁₆ are connected to each row.

The clock signal CK ₀ given by the clock input CK is divided by the dividing circuit 311 to obtain divided clocks CK _{1 to} CK ₄ . Where clock CK ₁
CK ₄ are ½ frequency divided clock, ¼ frequency divided clock, ⅛ frequency divided clock, and 1/16 frequency divided clock, respectively. The data supplied from the data inputs D _{0 to} D ₇ is supplied to the address inputs A _{0 to} A by the data selector circuit 312.
_{According to 5} , written in the display RAM. Data input D ₀
Display R according to the value of ~ D ₇ and address input A ₀ ~ A _5.
1 bit of any row and column of 512 bits of AM is "0"
The line address increment circuit 314 receives the clocks CK ₀ and CK ₄ , and outputs the row address every time the clock CK ₀ is inverted. Increment,
To clear the row address on the rising or falling edge of the clock CK _4. As the row address is incremented, the data s _{1 to} s ₃₂ sequentially read from the display RAM in units of ₃₂ bits in each row are stored in the segment output circuit 315.
Are output to the segment outputs S _{1 to} S ₃₂ via. The common timing generation circuit 316 uses the clocks CK _{0 to} CK.
₃ decodes the generated common timing t ₁ ~t _16, the common timing t ₁ ~t ₁₆ common output circuit 11
Are converted into common signals via 7 and common outputs H _{1 to} H ₁₆
Is output to.

FIG. 4 shows divided clocks CK _{0 to} CK ₄ , common timing signals t ₁ and t ₂ , segment signal S ₁ in the case of outputting a display pattern in which lighting and extinction are repeated for each row in the above configuration. And common signals H ₁ and H
₂ is shown. In FIG. 2, one frame of display is completed in a half cycle of the divided clock CK ₄ . Also, display RAM
In the column corresponding to the segment signal S ₁ of the first row is “1”,
"1" and "0" are written alternately such that the second line is "0" and the third line is "0".
₁ turns on and off repeatedly for each row. In addition, V ₁ ~ V
₆ (V ₁ <V ₂ <V ₃ <V ₄ <V ₅ <V ₆ ) is a liquid crystal display voltage supplied from the outside to perform 6-level driving. In the first frame of display, the segment signal is V ₆ turns on, V ₄ turns off, common signal is V ₁ for row selection, V
₅ is unselected. In this case, the dot at the intersection of the column where the segment signal is V _{6 and} the row where the common signal is V ₁ is lit. Further, in the next frame, the segment signal indicates lighting at V ₁ and lights off at V ₃ , and the common signal at V ₆ selects the row, V selects
₂ is unselected. In this case, the dot at the intersection of the column where the segment signal is V _{1 and} the row where the common signal is V ₆ is lit.

[0008]

In the above-mentioned conventional liquid crystal drive device, it is necessary to provide a dedicated common timing generation circuit in order to generate a common output. For this reason, the circuit scale of the liquid crystal drive circuit is increased, and the circuit itself is complicated.

Therefore, an object of the present invention is to simplify the apparatus by eliminating the need for a timing generation circuit for generating a common output.

[0010]

According to the present invention, the above-mentioned object is to store the display data for one screen in the display storage means, read the display data row by row, and on the basis of this, drive signal for the liquid crystal. In order to generate a display data for one row and a signal for selecting a row at the same row address in the liquid crystal drive apparatus for supplying the liquid crystal display apparatus with the signal for selecting the row. Is stored, and a signal for selecting a row is generated from the data output of the display storage means.

In the above structure, the data for generating the signal for selecting the row includes bits for the number of rows,
It is desirable that one bit be sequentially set to a logical high level for each row.

[0012]

According to the above configuration, the display data is read from the display storage means for each row, and in association with this, a signal for selecting a row stored at the same row address is generated. Data is also read, and a signal (common output) for selecting a row is generated from this data.

As a result, the timing generation circuit for generating the common output is unnecessary, and the device is simplified.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the liquid crystal driving device of the present invention. In FIG. 1, the liquid crystal driving device 11
Divides the reference clock signal CK ₀ input from the clock input CK to obtain a plurality of divided clock signals CK _{1 to} C.
The frequency divider circuit 111 for generating K ₄ is supplied from the display RAM 113 of 16 rows × 48 columns in which the display data of ₁₆ × 32 dots and the common data t _{1 to} t _{16 of} each row are written, and the address inputs A _{0 to} A _6. The display RAM 113 displays the display data input from the data inputs D _{0 to} D ₇ according to the address.
A data selector 112 to be written to, a row address increment circuit 114 for generating a row address when reading data from the display RAM 113, a segment signal is generated from the display data read for each row from the display RAM 113, and a segment output S Segment output circuit 115 for outputting to _{1 to} S ₃₂ , display RAM 113
From the common data t _{1 to} t ₁₆ read out in association with the reading of the display data of each row, the common output circuit 117 outputs common signals to the common outputs H _{1 to} H ₁₆ based on the common data t _{1 to} t ₁₆ . Reference numeral 12 is a 16 × 32 dot liquid crystal cell in which the segment outputs S _{1 to} S ₃₂ are connected to each column and the common outputs H _{1 to} H ₁₆ are connected to each row.

The clock signal CK ₀ given by the clock input CK is divided by the dividing circuit 111 to obtain divided clocks CK _{1 to} CK ₄ . Where clock CK ₁
CK ₄ are ½ frequency divided clock, ¼ frequency divided clock, ⅛ frequency divided clock, and 1/16 frequency divided clock, respectively.

The data supplied from the data inputs D _{0 to} D ₇ are written in the display RAM by the data selector circuit 112 in accordance with the address inputs A _{0 to} A ₆ .

Each row of the display RAM is divided into 16 columns in the first half and 32 columns in the latter half, and the display data of each row is written in the 32 columns in the latter half. The segment data (s
_{1 to} s ₃₂ ) are supplied to the segment output circuit 115. According to the values of the data inputs D _{0 to} D ₇ and the address inputs A _{0 to} A ₆ , 16 rows of the display RAM × 32 columns of the latter half, that is, 5
One bit in any 12-bit row or column can be set to "0" or "1".

On the other hand, the data of the first half 16 columns (common data t _{1 to} t ₁₆ ) of each row of the display RAM is output to the common outputs H _{1 to} H ₁₆ via the common output circuit 117. At this time, 16 columns of data in the display RAM are written so that the common data t _{1 to} t ₁₆ become “1” sequentially for each row. That is, "100 ... 00" is written in the first line, "010 ... 00" in the second line, "001 ... 00" in the third line, and so on until "000 ... 01" in the 16th line.

As a result, an arbitrary line 48 of the display RAM is displayed.
By reading the bits, the common data t _{1 to} t ₁₆ and the segment data s _{1 to} s ₃₂ can be obtained at the same time.

Clocks CK ₀ and CK ₄ are input to the row address increment circuit 114, and the clock C
Each time K ₀ is inverted, the row address is incremented and supplied to the display RAM 113. After the data in the display RAM is written, the row address increment circuit 114
First, the row address representing the first row is output, and thereafter, each time the clock CK ₀ is inverted, the row address to be output is incremented, and the segment data s _{1 to} s are output from the display RAM.
₃₂ is read sequentially. The common data t _{1 to} t ₁₆ at the row address read at the same time are converted into common signals via the common output circuit 117 and supplied to the common outputs H _{1 to} H ₁₆ . It lights each row by the embodiment in FIG. 2 row address at the rising or falling edge of the clock CK ₄ is to be cleared, in the case of outputting a display pattern such as repeated off, divided clock CK ₀ ~CK _4, The common timing signals t ₁ and t ₂ , the segment signal S ₁ , and the common signals H ₁ and H ₂ are shown respectively.

The operation of each unit in the above case will be described in detail below.

First, a display pattern in which the display RAM repeatedly turns on and off for each row, that is, the 1st, 3rd, and 5th rows of 32 bits corresponding to the segment output,
.., 15th line are all written with "1", while 2nd, 4th line, ..., 16th line are all written with "0". Here, the common data of each row is displayed as described above in advance.
It is assumed that it is written in AM113.

Thereafter, first, the row address increment circuit 114 outputs the row address representing the first row,
Data of the first line from the display RAM 113 (display data s ₁
.About.s ₃₂ and common data t _{1 to} t ₁₆ ) are read. The display data s _{1 to} s ₃₂ obtained therefrom are supplied to the segment output circuit 115, and the segment signals are output to the segment outputs S _{1 to} S ₃₂ . All the segment signals at this time are on (V ₆ ) and only the segment signal S ₁ is shown in FIG. 2 as an example. On the other hand, common data t ₁ ~
t ₁₆ is supplied to the common output circuit 117. At this time,
Since t ₁ is “1”, the selection pulse (V ₁ ) is output to the common output H ₁ . Accordingly, the liquid crystal display device 12
All 32 dots in the first row are lit.

Next, the row address increment circuit 1
The row address representing the second row is output from 14 and the display RA
The data of the second line (display data s _{1 to} s ₃₂ and common data t _{1 to} t ₁₆ ) is read from M113. The display data s _{1 to} s ₃₂ obtained therefrom are the segment output circuit 1
15 and the segment signal is supplied to the segment output S ₁
Is output to S ₃₂ . At this time, all the segment signals are off (V ₄ ). On the other hand, common data t _{1 to} t ₁₆
Is supplied to the common output circuit 117. At this time, t ₂
There because it is "1", selection pulse (V ₁₎ to the common output H ₂ is outputted. As a result, all 32 dots in the first row of the liquid crystal display device 12 are turned off.

In this way, the sequential rows are scanned and 16
The display of one frame is completed by scanning once.

After this, the next display frame is started.
In this display frame, the lighting voltage of the segment signal is V
Display is performed in the same manner as in the previous frame except that ₁ , the turn-off voltage is V ₃ , the common signal selection pulse voltage is V ₆ , and the non-selection pulse voltage is V ₂ .

As described above in detail, according to the present embodiment, since the common output can be obtained by inputting the display RAM output to the common output circuit 117, the common timing generating circuit becomes unnecessary and the liquid crystal driving device The circuit configuration can be simplified.

Further, according to this embodiment, the difference between the common output and the segment output is only the difference between the respective output circuits. Therefore, since the common output and the segment output can be diverted more easily than before, the output terminal arrangement of the common output and the segment output can be changed, and the vertical / horizontal dot configuration of the driven liquid crystal can be easily changed.

[0030]

As described above in detail, according to the present invention, display data for one row and data for generating a signal for selecting a row are stored at the same row address in the display storage means. When the display data stored in the display storage unit is read out line by line, the data for generating a signal for selecting a line stored at the same line address is also read out. Then, since a signal (common output) for selecting a row is generated from this data, a timing generation circuit for generating the common output is unnecessary, and the device is simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a liquid crystal driving device of the present invention.

FIG. 2 is a diagram showing signal waveforms of respective parts of the liquid crystal driving device shown in FIG.

FIG. 3 is a block diagram of an example of a conventional liquid crystal driving device.

4 is a diagram showing signal waveforms of respective parts of the liquid crystal driving device shown in FIG.

[Simple explanation of symbols]

 11 liquid crystal drive device 111 frequency dividing circuit 112 data selector 113 display RAM 114 row address increment circuit 115 segment output circuit 117 common output circuit 12 liquid crystal display device

Claims (2)

[Claims] 1. Display data for one screen is stored in a storage means for display, the display data is read out row by row, and a drive signal for liquid crystal is supplied to a liquid crystal display device together with a signal for selecting a row based on the read data. A liquid crystal drive device, wherein the storage means stores display data for one row and data for generating a signal for selecting a row at the same row address. A liquid crystal drive device characterized by generating a signal for selecting a row from an output. 2. The data for generating a signal for selecting the row includes bits for the number of rows, and one bit is sequentially set to a logical high level for each row. The liquid crystal driving device described.