JPH0764470A - Programmable controller - Google Patents

Abstract

PURPOSE:To provide a programmable controller (PC) which can operate at higher speed against branching/confluence and control a wider sequence. CONSTITUTION:In analysis by PC10 in selective branching or confluence, if a translating origin step is inactive, ARG16 is fixed to OFF through NRG17 and the failure of a translation condition is informed to the succeeding process, on the other hand, if it is active, the ARG16 is fixed to ON and the realization possibility of the translation condition is informed to the succeeding process. The ON/OFF data as for translation is received into the ARG16 when the translation condition can be realized. The address of the translating origin step is stored in SADD18, and at realization of the translation condition, a translating destination step is activated and simultaneously the translating origin step of the address is deactivated. In parallel branching or parallel confluence, two kinds of processes, namely, detection of the translation condition and activation or deactivation of the step, are performed in time series by the same command, and this alternative flag is set on RPT, and the address of the command to be repeated is stored in PCMEM19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller that realizes a wider range and faster processing of branch instructions and merge instructions based on SFC description.

[0002]

2. Description of the Related Art Conventionally, in the field, various information to be controlled, for example, physical quantity information such as a predetermined quantity of products passing through the exit of a belt conveyor, or danger when a cutting machine is operating. There is logical information such as detection of a moving object in the area. A programmable controller (hereinafter referred to as a PC) is widely used as a device for performing a predetermined output control (sequence control) according to the various information.

This PC programming method is quite different from normal computer programming, and generally,
The developed connection diagram (ladder diagram) of the relay circuit using the symbol marks such as contacts (limit switches) and coils (relays) that have been used in the field before the PC was used. The program described in the ladder diagram is converted into an intermediate language, further translated into a machine language, and stored as bit information in word units in a memory such as a RAM in the order of addresses.

As a program description method for this PC, in recent years, an SFC capable of graphically displaying the control operation of the PC has been shown.
(Sequencial Function Chart), an international standard (IE
The description format of CSC 65A / WG6) is used.

The description format of this SFC is, as shown in FIG. 14 (a), a description part (S) called step (STEP).
0, S1, S2, ...) and transitions (TRA
The description part called "NSITION" (TN0, TN1,
...) are connected by a link (LINK), and are arranged alternately with S0, TN0, S1, TN1, S2, .... These graphics programs are stored as graphics as they are.

The above links connect the steps in a graphic representation of the SFC to show the path of transition between steps, the direction of the path always being from top to bottom. Further, a step (S0, S1, S2, ...) Means one process in a series of sequences (control program), and has two states, active and inactive. When activated, the input / output is calculated by the action belonging to that step. And the transition (TN0, TN1, ...
*) Always exists between steps and represents a transition condition from a certain step to a subsequent step, and ON / OFF of the transition condition indicates selection / non-selection of the subsequent step.

According to the SFC rules, the transition from the already selected step to the subsequent step is that the transition destination step is inactive, and the transition transition condition between the transition source step and the transition destination step is satisfied. It is done only when the two conditions of doing are met. Further, when the transfer is performed, the transfer destination step is activated and the transfer source step is deactivated.

In accordance with the structure of such a program and the above-mentioned convention, the flow of steps is represented by a mnemonic.
c: Codes or abbreviations that represent computer instructions), and the contents of steps and transitions in a ladder diagram.

FIG. 2B shows the above steps (S0, S1,
It is an example of description by a ladder diagram of S2) and transitions (TN0, TN1). The on / off (true / false) of the transition TN0 shown in FIG. 6 (a) is the logical product of the on / off of two contacts of the program a of the transition TN0 shown in FIG. The resulting on / off is determined by being output to the coil TN0.
When the transition TN1 is turned on / off (true / false) shown in FIG. 7 (a), the on / off logical sum of the two contacts of the program b of the transition TN1 shown in FIG. 7 (b) is calculated. The calculated result is turned on / off by the coil TN.
It is output to 1. Bit memories corresponding to these coils are prepared for the coils TN0, TN1 ..., And the output to the coils TN1, TN1 ... It is recorded as "1" / "0").

Further, a plurality of (0 or more and 16 or less) actions (ACTION) which are actual processing content programs are described in the steps. One action is
In this step, it represents the actual operation content for the devices to be controlled, and consists of a large number of instructions that perform a series of logical operations (for example, a series or parallel combination of a plurality of switches), and as a result generate one output or instruction. To do. All actions within a step are executed only when the step is active. A bit memory corresponding to each of the above steps is also prepared, and the activation / deactivation of each step is recorded as ON / OFF of the bit memory (usually called a step relay) corresponding to each step. .

In the flow of steps described above, as shown in FIGS. 15 (a) to (d), four step transition methods of selective branching, selective merging, parallel branching, and parallel merging are SFC conventions. Indicated by. Explaining this, first, in the selection branch shown in FIG. 3A, the selection between a plurality of steps is performed by selecting the transition symbols corresponding to the expandable steps S4, S5, ... Under the horizontal link. Described. In the figure, only when step S3 is active and the transition condition "a" is true, the process proceeds from step S3 to step S4. Further, only when the step S3 is active, the transition condition "b" is true, and the transition condition "a" is false, the step S3 is performed.
To step S5.

Next, in the selection merging shown in FIG. 1B, at the end of the step selection, transition symbols corresponding to the number of selectable end steps are described on the horizontal link. In the figure, only when step S6 is active and the transition condition "c" is true, the process proceeds from step 6 to step 8. Further, only when step 7 is active and the transition condition “d” is true, the process proceeds from step 7 to step 8.

Further, in the parallel branch shown in FIG. 1C, only one common transition symbol is described immediately above the horizontal double link indicating the branch. In the figure, only when step 9 is active and the transition condition "e" of the common transition is true, steps S9 to S10 and S1 are performed.
Transition to 1 ... Steps S10, S11, ...
Are activated at the same time, and then step execution progresses independently of each other.

In the parallel merging shown in FIG. 3D, only one common transition symbol is described immediately below the horizontal double link indicating the merging. In the figure, only when all the steps S12, S13, ... Connected to the horizontal double link are active and the transition condition “f” of the common transition is true, the steps S12, S13 ,. The process proceeds to step S14.

[0015]

By the way, at present, SF
A mnemonic that can appropriately deal with the branching and merging of the C description has not been established.

When the above branch or merge is described by a mnemonic, a method of expanding into a plurality of instructions corresponding to each start step of the branch line or each end step of the branch line, and one operand containing the above plurality of instructions Configuration 1
It can be considered as a method of developing into one instruction form. In either case, when branching or merging step transition, the on / off (true / false) states of all transition sources, all transition destinations, and all transitions related to these transitions are collected, and the SFC described above is collected. It is necessary to decide whether to execute the migration based on the rules.

When expanded into a plurality of instructions, the decision as to whether or not the migration can be executed based on the collected on / off state data is usually made at the final stage of the expanded plurality of instructions. Then, when the migration is executed, each step related to the migration is activated (in the case of the migration destination step) and inactivated (in the case of the migration source step). For this purpose, the address of each step to be activated or deactivated must be recorded. For this reason, the operation of the instruction at the final stage becomes extremely complicated, and therefore, there is a problem that the operation of the PC becomes slow with respect to branching and joining.

In this case, the maximum number of branches of the step corresponds to the memory capacity prepared in advance. For this reason, there is a problem that the maximum number of branches is restricted, and therefore complicated or large-scale or wide range sequence control cannot be applied.

In the case where the instruction is not expanded into a plurality of instructions as described above, that is, even when a plurality of instructions are described in one operand repeatedly and expanded into a single instruction,
There is no change in the complexity of the operation of the instruction, and the problem still remains.

An object of the present invention is to provide a programmable controller that operates at a higher speed for branch / merge and can perform a wide range of processing without being restricted by the memory capacity.

[0021]

The present invention is based on SF and
It is applied to a programmable controller that operates by executing a branch or merge program based on the C description.

In the programmable controller according to the first aspect of the invention (see the block diagram of FIG. 1), the storage means 1
Stores a branch or merge instruction. The means is, for example, a RAM (Random-Access-Memory) or the like.

The analysis unit 2 analyzes the branch or merge instruction read from the storage unit 1. The means is, for example, a microprocessor, a program ROM (Read-Only-Memor
y) etc.

The first register 3 stores the ON or OFF state data of the transition relating to the branching or joining instruction read by the analyzing means 2. The second register 4 interlocks the off state of the first register 3.

The third register 5 stores the address of the migration source step relating to the branch or merge instruction read by the analysis means 2. The fifth register 7 stores data for selecting the processing procedure of the branch or merge instruction read by the analysis unit 2.

When the instruction for declaring the start of the selective branch is read, the analyzing means 2 initializes the second register 4 to set the first register 3 in the settable state and to the fifth register 7. First instruction processing procedure
Set data to instruct selection of. Further, when an instruction for detecting the active / inactive state of the transition source step in the branch is read, when the detected state of the transition source step is inactive, the first register 3 is transferred via the second register 4. When the state of the detected transition source step is active, the address of the transition source step is stored in the third register 5. Further, when the instruction for detecting the on / off state of the transition is read, when the detected state of the transition is on, the data for setting the on state to the first register 3 is output, while the detected When the transition state is OFF, the data for setting the OFF state is output to the first register 3. Further, when the instruction for instructing the selective branch is read, when the first register 3 is in the ON state and the state of the transition destination step is inactive, the transition destination step is activated and stored in the third register 5. The source step of the assigned address is deactivated and the second register 4
Interlock the first register to the off state via
On the other hand, when the first register 3 is in the OFF state or the state of the transition destination step is active, the processing is ended. When the instruction declaring the end of the branch is read out, the second register 4 is initialized to set the first register 3 in the settable state, and then the data set in the fifth register 7 is processed by the instruction. After confirming that the first selection of the procedure is instructed, the processing is immediately terminated.

Further, the analyzing means 2 may be, for example, claim 2.
As described above, when the instruction declaring the start of selective merging is read, the first register 3 is set to the settable state by initializing the second register 4, and the fifth register 7 is set to the first instruction processing procedure. Data for instructing selection of 1 is set. Also, when an instruction to detect the active / inactive state of the transition source step in selective merging is read,
When the detected state of the transfer source step is inactive, the first register 3 is interlocked to the OFF state via the second register 4, while when the detected state of the transfer source step is active, The transfer source step address is the third
Store in register 5. In addition, the transition on
When the instruction for detecting the off state is read, when the detected state of the transition is on, the data for setting the on state to the first register 3 is output, while the detected state of the transition is off. At some time, data for setting the off state to the first register 3 is output. Further, when the command for instructing selective merging is read, the first
When the register 3 is in the ON state and the state of the transfer destination step is inactive, the transfer destination step is activated, the transfer source step of the address stored in the third register 5 is deactivated, and the second register 4 The first register 3 is interlocked to the off state via the, while the process is ended when the first register 3 is in the off state or when the state of the transition destination step is active. When the instruction declaring the end of the merge is read, the second register 4 is initialized to make the first register 3 settable, and then the data set in the fifth register 7 is processed by the instruction. After confirming that the first selection of the procedure is instructed, the processing is immediately terminated.

A programmable controller according to a third aspect of the present invention, in addition to the respective configurations of the storage means 1, the analysis means 2, the first register 3, the second register 4, the third register 5 and the fifth register 7, The analysis means 2 has a fourth register 6 for storing the program address of the branch or merge instruction read out, and the analysis means initializes the second register 4 when the instruction declaring the start of the parallel branch is read out. By setting, the first register 3 is set to a settable state, data for instructing the second selection of the instruction processing procedure is set in the fifth register 7, and the start program address of the next instruction is set in the fourth register 6. Set. Further, when an instruction for detecting the active / inactive state of the transfer source step in the parallel branch is read, when the detected state of the transfer source step is inactive, the first register 3 via the second register 4 Is interlocked to the off state, and when the detected state of the transition source step is active, the address of the transition source step is stored in the third register 5. Further, when the instruction for detecting the on / off state of the transition is read, when the detected state of the transition is on, the data for setting the on state to the first register 3 is output, while the detected When the transition state is OFF, the data for setting the OFF state is output to the first register 3. When the instruction for parallel branch is read, the first register 3 is in the OFF state when the data set in the fifth register 7 indicates the second selection of the instruction processing procedure. If the first register 3 is in the ON state and the state of the transition destination step is inactive, the process is terminated, and the first register 3 is in the ON state and the transition destination step When the state is active, the data for setting the OFF state to the first register 3 is output, while the data set to the fifth register 7 indicates the first selection of the instruction processing procedure. Activates the migration destination step and deactivates the migration source step of the address stored in the third register 5. When the instruction declaring the end of the branch is read out, the second register 4 is initialized to set the first register 3 in the settable state, and then the data set in the fifth register 7 is processed by the instruction. When the second selection of the procedure is shown, the processing is ended when the first register 3 is in the off state, and when the first register 3 is in the on state, the first register 3 of the instruction processing procedure is written in the fifth register 7. After setting data for instructing selection, the fourth register 6
When the data set in the fifth register 7 indicates the first selection of the instruction processing procedure, the processing is immediately terminated.

Further, the analyzing means 2 may be, for example, claim 4.
As described above, when the instruction declaring the start of parallel merging is read, the first register 3 is set to the settable state by initializing the second register 4, and the fifth register 7 is set to the first instruction processing procedure. The data instructing the selection of 2 is set and the leading program address of the next instruction is set in the fourth register 6. Further, when an instruction for detecting the active / inactive state of the transition source step in parallel merging is read, when the data set in the fifth register 7 indicates the second selection of the instruction processing procedure. At
When the state of the transfer source step is active, the processing is terminated, and when the state of the transfer source step is inactive, the first register 3 is interlocked to the off state via the second register 4, while the first 5 When the data set in the register 7 indicates the first selection of the instruction processing procedure, the transfer source step is deactivated. When the instruction for parallel merging is read, the first register 3 is in the OFF state when the data set in the fifth register 7 indicates the second selection of the instruction processing procedure. If the first register 3 is in the ON state and the state of the transition destination step is active, the process is terminated and the first register 3 is in the ON state and the state of the transition destination step is non-active. If it is active, the transition destination step is activated. On the other hand, if the data set in the fifth register 7 indicates the first selection of the instruction processing procedure, the processing is terminated. When the instruction declaring the end of the merge is read, the second register 4 is initialized to make the first register 3 settable, and then the data set in the fifth register 7 is processed by the instruction. When the second selection of the procedure is shown, the processing is ended when the first register 3 is in the off state, and when the first register 3 is in the on state, the first register 3 of the instruction processing procedure is written in the fifth register 7. After setting the data for instructing selection, jump to the program address set in the fourth register 6, while the data set in the fifth register 7 instructs the first selection of the instruction processing procedure. Immediately ends the process.

As a result, it is possible to perform branching / merging at a higher speed, and it is possible to set a desired number of branching steps and perform a wider range of sequence control without being restricted by the memory capacity.

[0031]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 is a block diagram showing the configuration of the PC according to the embodiment. As shown in the figure, PC
Reference numeral 10 denotes a CPU (Central-Processing-Unit) 11 and a ROM (Rea) to the CPU 11 via a bus line 12.
d-Only-Memory) 13, RAM (Random-Access-Memory) 1
4 and an I / F (input / output interface) 15 are connected. Further, the bus line 12 has a register ARG.
16, a register NRG17, a register SADD18, a register PCMEM19, and a register RPT20 are connected.

The ROM 13 stores a program for controlling the entire system. The RAM 14 stores mnemonics for sequence control transferred from a program loader described later. Various input / output devices that constitute the controlled system are connected to the I / F 15 via a system line (not shown).

The CPU 11 sequentially reads out the mnemonic instructions stored in the RAM 14 and outputs the read instructions as R.
Analysis is performed based on the program stored in the OM 13, calculation is performed based on the analysis result, and the calculation result is output to the I / F 15.

In the analysis / calculation processing by the CPU 11, the register ARG 16 stores the ON / OFF state data of the transition relating to the branch or merge instruction processed by the CPU 11. Register NRG17 interlocks the off state of register ARG16. The register SADD18 stores the address of the transition source step related to the above branch or merge instruction. Register PCME
M19 stores the address of the branch or merge instruction program. The register RPT20 stores data for selecting one of the processing procedures of the branch or merge instruction.

FIG. 3 shows the relationship between the register ARG16 and the register NRG17. As shown in the figure, both the registers ARG16 and NRG17 are flip-flops having the same configuration, and each has a data input terminal D, a clock input terminal, an inverting reset terminal R, and an output terminal Q. The output NRG of the register NRG17 is input to the inverting reset terminal R of the register ARG16. The register NRG17 is reset by "L" level ("0") input to the inverting reset terminal R output from the CPU 11, and reset by "H" level ("1") input. The register ARG16 is reset by inputting the output NRG from the register NRG at the "L" level ("0") to the inverting reset terminal R thereof. That is, the output AGR is fixed to "0". When the output NRG of the register NRG17 is input at "H" level ("1"), the reset is released, and the ARG input data (transition on / off information) input to the data input terminal D is latched. , This latched data as output ARG to CPU
Output to 11.

FIG. 4 schematically shows the arrangement of the program stored in the RAM 14 after the SFC description is converted into mnemonics. As shown in the figure, R
In the AM 14, a transition group program is stored at the top, a line group program is stored next, and an action section program is stored at the end.

The CPU 11 of the PC 10 shown in FIG. 2 first executes the program of the transition group with respect to the program stored as shown in the figure, and based on the input data (information), each transition TN0, TN
Outputs on (true) / off (false) information of 1, ...
Next, the program of the line group is executed, and a step transition instruction is output (the step relay is updated) based on the information on the on / off of the transition and the activation / inactivation of the transition source step and the transition destination step. Then, the program of the action unit is sequentially read, and it is determined whether or not to execute the action based on the step transition instruction, and the process is performed. That is, the actions belonging to the transition destination step (active step) are processed, and the actions that do not belong are treated as unprocessed and reach the end point of the action part. Then, returning to the program of the transition group again, the processing from the beginning of the transition group to the end point of the action section is repeated.

Generally, the above-mentioned one round of processing is called one scan, and this one scan forms one process. 1
A process is a unit of control processing such as one machine or one line, and normally the entire sequence control is configured by an SFC program group by a plurality of processes. The user determines where to divide the whole sequence control as one process.

In this way, one process forms a series of sequence control delimiters, and also forms branch lines for branching and merging described below. FIG. 5A shows an example of selective branch of SFC description. This description shows the case where the step S000 is selectively branched to any one of the three steps S001, S002 and S003 via the transition TN000, TN001 or TN0010, respectively.

The above branching condition based on the SFC protocol is shown in FIG.
As described in 5, the following selective merging, parallel branching,
The same applies to the case of parallel merging. FIG. 3B shows an example of selective merging, and three steps S010, S011 and S
012 selectively, transition TN00 respectively
0, TN001 or TN0010, step S
The case of joining 013 is shown.

Further, FIG. 6A shows an example of parallel branching. This description starts from step S000 and goes through three steps S001 and S0 via a common transition TN000.
It shows the case of branching to 02 and S003 at the same time.

FIG. 6 (b) shows an example of parallel merging.
The case where three steps S020, S021, and S022 are merged into step S023 via the common transition TN000 at the same time is shown.

In this embodiment, in order to process the above-mentioned branching and merging programs at a higher speed, and also to enable processing of a large-scale sequence regardless of the number of branches. The mnemonics shown on the right side of FIGS. 5 (a) and (b) and FIGS. 6 (a) and 6 (b) are developed corresponding to the branching and merging of the SFC description as described above. This mnemonic can be automatically converted by the program loader described later from the graphics (SFC description) shown on the left of FIGS. 5 (a), (b) and 6 (a), (b), or manually. It is also possible to input to the program loader while transcribing (converting).

In the mnemonic shown in FIG. 5 (a), the start of the selected branch is first declared by the instruction D-SLC, then the active state of the branch source step S000 is read by the instruction STL, and then the instruction Read on / off state of transition TN000 with LD, and with command SLCT,
The active state of the branch source step S000 and the on / off state of the transition TN000, and the branch destination step S
If it is possible to branch based on the state of 001, it is instructed to branch to step S001. Subsequently, the instruction LD and the instruction SLCT are similarly changed to the transition TN0.
01 and step S002 are repeated, and the instruction LD and instruction SLCT are changed to transition TN002.
And step S003 are repeated for the instruction E-
TRA declares the end of the above selection branch.

Further, in the mnemonic shown in FIG.
First, the start of selective merging is declared by the instruction C-SLC, then the active state of the merging source step S010 is read by the instruction JUNC, and then the transition T is made by the instruction LD.
After reading the ON / OFF status of N000, set SET
Then, when it is possible to merge based on the active state of the merge source step S010, the on / off state of the transition TN000, and the state of the merge destination step S013, it is instructed to merge to step S010. Then, the instructions JUNC, LD, and SET are further added in step S01.
1, transition TN001 and step S013 are repeated in the same manner as above, and the instruction JUN is continued.
After repeating C, LD and SET in the same manner as described above for step S012, transition TN002 and step S013, the instruction E-TRA declares the end of the selective merging.

Further, the mnemonic shown in FIG. 6 (a) is
First, the start of parallel merging is declared by the instruction D-SIM, then the active state of the branch source step S000 is read by the instruction STL, and then the transition TN is issued by the instruction LD.
Read the ON / OFF status of 000 and execute the instruction SI
In the MUL, when it is possible to branch based on the active state of the branch source step S000, the ON / OFF state of the transition TN000, and the state of the branch destination step S001, the MUL is instructed to branch to step S001. Subsequently, similarly to the above, the instruction SIMUL is repeated for step S002, and the same instruction SIMUL is repeated for step S003, and then the instruction E-TRA is executed.
The end of the parallel branch is declared.

Then, the mnemonic shown in FIG.
First, the command C-SIM declares the start of parallel merging, and then the command SYNL is repeated three times to read the active states of the merging source steps S020, S021, and S022, respectively, and then the command LD, Transition TN0
After reading the ON / OFF state of 00, the command SYNC
Then, the above-mentioned merge source step active state and transition T
ON / OFF state of N000, and merge destination step S02
When it is possible to merge based on the state of No. 3, step S0
23 at the same time, and finally command ET
RA has declared the end of the parallel merging.

FIG. 7 shows a list of 13 mnemonic instructions used for branching and merging. The instructions shown in the figure will be described below. The instruction D-SLC declares the start of a taken branch. The instruction STL instructs reading of the step active state in the selected branch or the parallel branch.
The instruction LD gives an instruction to read the on / off state of the transition. The instruction SLCT points to a selected branch. The instruction C-SLC declares the start of selective merging. Command JUNC
Indicates reading of the step active state in selective merging. The command SET instructs selective merging. Command D-SI
M declares the start of a parallel branch. The instruction SIMUL indicates a parallel branch. The instruction C-SIM declares the start of parallel merging. The instruction SYNL instructs reading of the step active state in parallel merging. The instruction SYNC instructs parallel merging. The instruction E-TRA then declares the end of the branch or merge.

FIG. 8 shows an SFC programming device (program coder) for converting the above-mentioned SFC description graphic into the above mnemonic. As shown in the figure,
The program coder 30 includes an input unit 31, an instruction storage unit 3
2, graphic conversion unit 33, graphic storage unit 34, display conversion unit 3
5 and a display unit 35.

When a program is created by the program coder 30, first, the operator designates the graphic information representing the SFC graphic or the symbol of the ladder diagram through the input unit 31. The graphic storage unit 34 stores this graphic information, and the display conversion unit 35 reads the specified graphic information from the graphic storage unit 34, converts it into a display format, that is, an SFC graphic or a ladder diagram, and converts it into this display format. Is displayed on the display device or the like of the display unit 35. As a result, the operator successively creates a program while checking the graphic displayed on the display.

Next, the graphic conversion unit 33 reads the program created as the graphic information from the graphic storage unit 34, converts it into a mnemonic, and stores the mnemonic in the instruction storage unit 32. From the instruction storage unit 32, the data is transferred to the RAM 14 of the PC 10 shown in FIG. 2 via a data transfer interface (not shown), and a program as shown in FIG. 4 is stored.

The program code (mnemonic) stored in the PC 10 is not a language (machine code) that can be executed in the PC 10 as is generally called a programming language, but an intermediate code format that is easy for the user to understand. I am taking it. Of course, the mnemonics may be analyzed and converted into an executable program code before being stored. In that case, the CPU 11 performs a process corresponding to the executable program code.

In the following description, it is assumed that the mnemonic (intermediate code) is stored. Then, the stored mnemonic is further converted into a machine language (machine code) in sequence and the sequence control by the PC 10 is executed.

In the present embodiment having the above-mentioned configuration, the 13 instructions shown in FIG. 7 of the mnemonic are replaced by the 5 instructions shown in FIG.
By using each register and analyzing based on the algorithm described below, a branching or merging program by SFC description is processed at high speed so as to be compatible with a large-scale system. The instruction processing operation in this embodiment will be described with reference to the flowcharts shown in FIGS. As a concrete example, the mnemonics shown on the right side of FIGS. 5 and 6 are referred to.

First, the case of selective branching will be described as an example. In the selected branch, as shown in the mnemonic in FIG. 5A, the start declaration instruction D-SLC of the selected branch, the branch source step active state read instruction STL, the transition on / off state read instruction LD, the instruction of the selected branch Command SLC
Processing is performed by T and a branch end declaration instruction E-TRA.

The instruction D-SLC has two registers NRG and RPT as shown in the flowchart of FIG.
Is initialized and the process ends. In this initialization, first, "1" is set in the register NRG (step S1).
In this process, the latch signal is input to the clock input terminal of the register NRG and the NRG input data “1” is input to the input terminal D to be latched.
This is a process for canceling the reset of the RG. Further, in this initialization, "0" is set in the register RPT (also step S1). As a result, the content of the register RPT is set to "0" which is the initial state.

Next, in the instruction STL, as shown in the flow chart of FIG. 9B, the active state of the transition source (branch source) step (see step S000 of FIG. 5A) is read to determine whether it is active. It is determined (step S11). With this determination,
If the transfer source step is active, it means that the transfer condition of the transfer source step is satisfied. At this time, next, "1" is set in the register NRG (step S12). This processing sets the register ARG to the set state in preparation for the case where the register ARG has been reset (interlocked to "0"), and the transition condition is satisfied when the transition is active in the next subsequent instruction. This is a process that enables setting what is being done in the register ARG.

Then, following the above, the address of the transfer source step is stored in the register SADD (step S1).
4), the process ends. If the transfer source step is inactive in the determination in step S11, it means that the transfer condition of the transfer source step is not satisfied. In this case, register N
"0" is set in RG (step S13), and the process ends. The process of the procedure 13 is a process of inputting a latch signal to the clock input terminal of the register NRG and inputting NRG input data “0” to the input terminal D to latch it. As a result, the output NRG of the register NRG becomes "0", the register ARG is reset, and the output ARG of the register ARG is fixed (interlocked) to "0". As a result, even if the transition transition condition to be described later is "OK" (ON, that is, active), the "OK" is ignored.

Then, in the instruction LD, as shown in the flow chart of FIG. 10A, the transition on the link to the transition destination (branch destination) step (see the transition TN000, TN001 or TN002 in FIG. 5A). ), The active state is read to determine whether it is active (step S2).
1). If it is active, the register ARG is set to "1".
Is set (step S22), and the process ends. The process of step S22 is a process of inputting a latch signal to the clock input terminal of the register ARG and inputting ARG input data “1” to the input terminal D. As a result, when the register ARG is in the set state (when the transition source step is active), the ARG input data "1" is latched and the output ARG becomes "1". Meanwhile, the register ARG
Is in an interlocked state (when the source step is inactive), the ARG input data "1" is ignored and the output ARG remains fixed at "0".

If it is determined in step S21 that the transition is inactive, "0" is set in the register ARG (step S23) and the process ends. This step S2
The process of 3 is a process of inputting “0” to the input terminal D of the register ARG in the same manner as described above. In this case, the result is the same whether the register ARG is set or interlocked, and the output ARG is "0".

Next, in the instruction SLCT, as shown in the flowchart of FIG. 10 (b), the contents of the register ARG are first checked (step S31). This process is performed by register ARG
Is a process for determining whether or not the output ARG of "1" is "1". If the output ARG is "1", it is determined that the transition source step is active and the transition is also active. In this case, the transition destination step (FIG. 5 (a)) is continued.
(See step S001, S002, or S003) of (1) is determined (step S32). If the transition destination step is inactive in this determination, it is determined that the transition condition is satisfied, and the transition destination step is activated (step S33),
Then, the transfer source step is deactivated (step S34).
In this processing, the step of the address stored in the register SADD is deactivated by the processing of the above-mentioned instruction STL. Thereafter, "0" is set in the register NRG (step S35). As a result, the register ARG is reset and the output ARG is fixed to "0". For this reason, after that, all the processing results by the instructions LD and the instructions SLCT executed for each transition destination step of the remaining options become invalid, so that the transition destination step where the transition condition is first established is fixed as the branch destination step. -It will be selected.

By the determination in the above step S31, the register ARG
If the output ARG of “1” is “0”, one or both of the transition source step and the transition are inactive, it is determined that the transition condition is not satisfied, and the process is immediately terminated. Further, in the determination of the above step S32, it is determined that the transition condition is not satisfied even when the transition destination step is active, and the process is immediately terminated.

Then, the instruction E-TRN sets "1" in the register NRG as shown in the flowchart of FIG. 11 (step S41). As a result, the register AR
If G is in the reset state, the reset is released, and if G is the set state, the set state continues. Then register R
The contents of PT are checked (step S42). In the case of the selective branch, the register RPT is set to "0" by the processing of the start declaration instruction D-SLC. When this "0" is confirmed, the processing is immediately terminated.

By the above-mentioned processing, the detection of the migration destination step satisfying the migration condition in the selected branch and the update processing of the active / inactive state data of the migration source step and the migration destination step after the migration decision are not limited to the number of branches. And it is done at high speed.

Next, the case of selective merging will be described as an example. In the selective merging, as shown in the mnemonic of FIG. 5B, the selective merging start declaration instruction C-SLC, the active state read instruction JUNC of the selective merging source step, the transition on / off state read instruction LD, the selective merging instruction. Command S
Processing is performed by the ET and the merge end declaration instruction E-TRA.

The instruction C-SLC performs processing in the same procedure as the instruction D-SLC of the selected branch, as shown in the flowchart of FIG. 9 (a). The instruction JUNC also performs processing in the same procedure as the instruction STL of the selected branch, as shown in the flowchart of FIG.

The instruction LD performs the same processing as in the case of the selective branch. The instruction SET performs processing in the same procedure as the instruction SLCT of the selected branch, as shown in the flowchart of FIG. At this time, if the register ARG is "1" in step S31 and the transition destination step is active in step S32, that is, the transition condition is satisfied, the register NRG is set to "0" in step S35 as in the case of the selective branch. Is set, whereby the register ARG is reset and its output ARG is fixed to "0". Therefore, after this, the instruction L to be executed at each of the transfer source steps of the remaining options is executed.
All the processing results by D and SET are invalid, and therefore the transfer source step where the transfer condition is first established is fixed and selected as the merge source step.

Then, the instruction E-TRN is a common procedure as shown in the flowchart of FIG. 11, and as in the case of the selective branch, "0" set in the register RPT is confirmed in step S42, Immediately ends the process.

By the above processing, the detection of the migration source step satisfying the migration condition in the selective merge and the update processing of the active / inactive state data of the migration source step and the migration destination step after the migration decision are not limited to the number of branches. And it is done at high speed.

Next, the case of parallel branching will be described as an example. In the parallel branch, as shown in the mnemonic of FIG. 6A, the parallel branch start declaration instruction D-SIM, the branch source step active state read instruction STL, the transition on / off state read instruction LD, the parallel branch instruction instruction SIMU.
Processing is performed by L and a branch end declaration instruction E-TRA.

The instruction D-SIM has two registers NRG and RP as shown in the flow chart of FIG.
The initialization of T is performed and the processing is terminated. In this process, the register NRG is set to "1" and the register RPT is also set to "1" (step S51). As a result, as described above, the reset of the register ARG is released and the flag is set in the register RPT.

Then, the head program address of the next instruction is stored in the register PCMEM (step S52), and the process is terminated. The process of step S52 is a process of storing the start program address of the instruction STL next to this instruction. As a result, the flag of the register RPT is discriminated by the processing described later, and the processing function of the instruction SIMUL is doubly utilized.

Next, the instruction STL is the same as in the case of the selective branch. That is, the transfer source (branch source) step (see FIG. 6).
The active state of (a) (see step S000) is determined (step S11), and if active (transition condition is satisfied), register N
RG is set to "1" to set the register ARG to the set state (procedure 12), the address of the transition source step is then stored in the register SADD (procedure S14), and the process is terminated. On the other hand, if it is inactive (the transition condition is not satisfied), "0" is set in the register NRG to interlock the output ARG of the register ARG to "0" (step S1).
3), the process ends.

The instruction LD is similar to the case of the selective branch. That is, the active state of the transition (see common transition TN000 in FIG. 6A) is determined (step S21), and if active, "1" is set in the register ARG (step S22). In this case also, the register ARG
Is set (when the source step is active)
"1" is latched, and in the interlock state (the transition source step is inactive), "1" is not latched and the output ARG remains "0".

Then, in the instruction SIMUL, FIG.
As shown in the flowchart of (1), first, the flag of the register RPT is determined (step S61). Here, after confirming the flag "1" set in step S51, the content (output) of the register ARG is subsequently checked (step S6).
2). If the output ARG of the register ARG is "1", the transition source step (step S000) is active and the transition (common transition TN000)
Is also active, and subsequently, the transition destination step (see FIG. 6) is performed.
(See step S001, S002 or S003 in (a))
The active state of is determined (step S63). In this determination, if the transition destination step is inactive, it is determined that the transition condition is satisfied for this step, and the process is immediately terminated. On the other hand, if the transfer destination step is active, "0" is set in the register ARG (step S64). As a result, the migration destination step S001, S002 or S003
If any one of these is active, the output ARG of the register ARG becomes "0".

In step S62, if the output ARG of the register ARG is "0", the processing is immediately terminated. As a result, if any one of the preceding branch destination steps (see steps S001 and S002 in FIG. 6A) is active, the subsequent branch destination step (steps S002 and S0).
(See No. 03), the active state is not discriminated, and the process ends immediately.

The case where the flag of the register RPT is "0" in the above step S61 will be described later. And instruction E
-In TRN, as shown in the flowchart of FIG.
The process of step S41 is performed similarly to the case of the selective branching / merging, and in step S42, "1" set in the register RPT is determined. In this case, the process proceeds to step S43 and the output ARG of the register ARG is "1". It is determined whether or not it is ".
If the output ARG is "0" in this determination, it is determined that the transition condition is not satisfied, and the processing is immediately terminated.

On the other hand, if the output ARG is "1", it is determined that the transition condition is satisfied for all branch destination steps, and in this case, the same instruction is repeated in the register RPT to perform another processing. After setting the flag "0" indicating (step S44), the process jumps to the address indicated by the register PCMEM (step S45). As a result, the process is restarted from the instruction STL (see FIG. 6 (a)).

In this restarted processing, the instruction STL
And LD, the same processing as the previous time is performed. And the command S
In IMUL, the flag “0” of the register ARG is discriminated, and in this case, the process proceeds to step S65, and the transfer destination step is activated. As a result, all steps at the branch destination are activated (see the mnemonic shown on the right side of FIG. 6 (a)). Succeedingly, in the step S66, the transfer source step, that is, the step of the address indicated by the register SADD is deactivated. Finally, in the instruction E-TRN, the process of step S41 is performed, and in step S42, "0" of the register RPT is discriminated and the process is immediately terminated.

By the above processing, when the migration condition is satisfied in the parallel branch, the update processing of the active / inactive state data of the migration source step and the migration destination step after the migration is determined can be performed at high speed without limitation to the number of branches. Done.

Next, the case of parallel merging will be described as an example. In the parallel merging, as shown in the mnemonic of FIG. 3B, the parallel merging start declaration instruction C-SIM, the active state read instruction SYNL of the parallel merging source step, the transition on / off state read instruction LD, the parallel merging instruction. Processing is performed by the instruction SYNC and the merge end declaration instruction E-TRA.

As shown in the flow chart of FIG. 12 (a), the instruction C-SIM performs processing in the same procedure as the merge branch instruction D-SIM. Then, in the command SYNL, as shown in FIG.
As shown in the flowchart of 3 (a), first, the register R
The PT flag is determined (step S71). Here, after confirming the flag "1" set in the procedure 51 of the processing by the instruction C-SIM, the active state of the migration source step (see step S020, S021 or S022 in FIG. 6B) is determined. (Procedure S72). If the step is inactive in this determination, "0" is set in the register NRG, and the output ARG of the register ARG is set as described above.
Is fixed to "0" (step S73). As a result, if any one of the transfer source steps is inactive, the output ARG of the register ARG is fixed to "0". If the step is active in step S72, nothing is done,
Immediately ends the process. The case where the flag of the register RPT is "0" in the above step S71 will be described later.

Then, in the instruction LD, as in the case of the parallel branch, the active state of the transition (see the common transition TN000 in FIG. 6B) is determined in step S21,
If it is active, "1" is set in the register ARG in step S22. In this case, in the processing for all the transition source steps by the above-mentioned instruction SYNL (see the mnemonic in FIG. 6B), if all the transition source steps are active, the register ARG is in the set state, and therefore the above "1" ”
Is latched. On the other hand, if any one of the transfer source steps is inactive, the register ARG is interlocked with "0" and the above "1" is not latched.

In the following instruction SYNC, first, the register R
Confirm that the PT flag is "0" (step S8).
1), determine the output ARG of the register ARG (step S
82). Then, if the output ARG is "1", it is determined that all the transition source steps and the common transitions show the merging possible state, and in this case, the activation state of the transition destination step is subsequently determined (step S83). . If it is inactive, it is determined that the transition condition for parallel merging is satisfied, and this transition destination step is activated (step S8).
4).

In step S83, if the transfer destination step is active, it is determined that the parallel merge transfer condition is not satisfied, and the process is immediately terminated. In step S82 above,
When the output ARG is "0", it is determined that all the transition source steps or the common transitions do not indicate a mergeable state, and in this case also, the processing is immediately terminated. In step S81, when the flag of the register RPT is "0", it is determined that the non-processing is instructed in the restart processing described later, and in this case also, the processing is immediately terminated.

Then, the instruction E-TRN performs the same processing as in the case of the parallel branch, and immediately ends the processing when the transition condition is not satisfied. On the other hand, when the transition condition is satisfied, as described above, the register R
After setting the flag "0" in PT, register PCMEM
Jump to the address indicated by. As a result, the instruction C-
The processing is restarted from the instruction SYNL following the SIM (FIG. 6).
(See (b)).

In this restarted process, the instruction SYN
In L, the flag "0" of the register RPT is discriminated in step S71, and in this case, the process proceeds to step S74 to deactivate the migration source step. As a result, all the merge source steps are inactivated (see the mnemonic shown on the right side of FIG. 6 (b)).

Then, the instruction LD is executed in the same manner as the previous time, and in the instruction SYNC, as described above, the non-processing is judged by the "0" of the register RPT, the processing is immediately terminated, and the last instruction E-TRN is executed. Also, after performing the process of step S41, "0" of the register RPT is determined in step S42, and the process is immediately terminated.

By the above processing, when the migration condition is satisfied in parallel merging, the update processing of the active / inactive state data of the migration source step and the migration destination step after the migration determination can be performed at high speed without any limitation on the number of branches. Done.

In this embodiment, a mnemonic instruction, for example, an instruction declaring the start of a selective branch is called "DS".
Although it is represented by "LC", any form of code may be used as long as it defines that the start of the selective branch is declared. This also applies to other instructions.

[0091]

According to the present invention, in merging / branching,
The process of deactivating the transfer source step and the process of activating the transfer destination step can be distributed without being concentrated in the final stage instruction, and therefore the process can be performed at high speed. Further, since it is possible to recognize whether or not the transition conditions of a plurality of transition source steps and a plurality of transitions are satisfied from the contents of one register, the addresses of each transition source step and each transition destination step are recorded in the memory. There is no need, which reduces memory costs. Similarly, since the setting of the number of branch steps is not restricted by the memory capacity, large-scale or complicated sequence control that requires multiple branches can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a configuration block diagram of a programmable controller according to an embodiment.

FIG. 3 is a diagram illustrating a relationship between a register NRG and a register ARG.

FIG. 4 is a schematic diagram showing an arrangement of SFC programs stored in a RAM.

5A is a diagram showing a description example of a mnemonic of selective branching, and FIG. 5B is a diagram showing a description example of a mnemonic of selective merging.

6A is a diagram showing a description example of a parallel branch mnemonic, and FIG. 6B is a diagram showing a description example of a parallel merging mnemonic.

FIG. 7 is a table for explaining mnemonic instructions used in this embodiment.

FIG. 8 is a configuration block diagram of a programming device (program loader).

9A is a flowchart showing the operation of an instruction D-SLC or an instruction C-SLC, and FIG. 9B is an instruction STL or an instruction J.
It is a flowchart which shows operation | movement of UNC.

10A is a flowchart showing an operation of an instruction LD, and FIG. 10B is a flowchart showing an operation of an instruction SLCT or an instruction SET.

FIG. 11 is a flowchart showing an operation of an instruction E-TRN.

12A is a flowchart showing the operation of an instruction D-CIM or instruction C-CIM, and FIG. 12B is a flowchart showing the operation of an instruction SIMUL.

13A is a flowchart showing an operation of an instruction SYNC, and FIG. 13B is a flowchart showing an operation of an instruction SYNC.

14A and 14B are schematic diagrams illustrating the program structure of SFC.

15 (a), (b), (c), and (d) are diagrams for explaining SFC branching and merging.

[Explanation of symbols]

 1 storage means 2 analysis means 3 first register 4 second register 5 third register 6 fourth register 7 fifth register

Claims (4)

[Claims] 1. A programmable controller operated by a program based on an SFC description, a storage means (1) for storing a branch or merge instruction, and an analysis for analyzing the branch or merge instruction read from the storage means (1). A means (2), a first register (3) for storing the on / off state data of a transition relating to a branch or merge instruction read by the analyzing means (2), and an off state of the first register (3) A second register (4) for interlocking the state, and a third register for storing the address of the transfer source step relating to the branch or merge instruction read by the analyzing means (2).
(5) and a fifth register (7) for storing data for selecting one of the branching or merging instruction processing procedures read by the analyzing means (2), the analyzing means ( When the instruction for declaring the start of the selective branch is read, 2) initializes the second register (4) to make the first register (3) settable and the fifth register (7). ) Is set to the data for instructing the first selection of the instruction processing procedure, and when the instruction for detecting the active / inactive state of the transfer source step in the branch is read, the detected state of the transfer source step is When it is inactive, the first register (3) is interlocked to the off state via the second register (4), while when the detected state of the transition source step is active, the transition source step Store the address of the above into the third register (5) When the instruction to detect the on / off state of the transition is read, when the detected state of the transition is on, the data for setting the on state to the first register (3) is output, and on the other hand, it is detected. When the state of the transition is off, data for setting the off state to the first register (3) is output, and when the instruction instructing the selective branch is read, the first register (3) is output.
When the register (3) is on and the state of the transfer destination step is inactive, the transfer destination step is activated and the transfer source step of the address stored in the third register (5) is deactivated. And interlocking the first register to the off state via the second register (4),
On the other hand, when the first register (3) is in the OFF state or when the state of the transition destination step is active, the processing is terminated, and when the instruction declaring the end of the branch is read, the second register After setting the first register (3) to the settable state by initializing (4), the fifth register
A programmable controller characterized in that the processing is immediately terminated after confirming that the data set in (7) indicates the first selection of the instruction processing procedure. 2. The analysis means (2) sets the first register (3) in a settable state by initializing the second register (4) when an instruction declaring the start of selective merging is read. In addition, when data for instructing the first selection of the instruction processing procedure is set in the fifth register (7) and an instruction for detecting the active / inactive state of the transition source step in the selection merge is read out, The second register when the state of the detected transition source step is inactive
The first register (3) is interlocked to the off state via (4), while when the detected state of the transfer source step is active, the address of the transfer source step is set to the third register (5). ) And read the instruction to detect the on / off state of the transition, output the data to set the on state to the first register (3) when the detected state of the transition is on. On the other hand, when the detected state of the transition is OFF, the data for setting the OFF state to the first register (3) is output, and when the instruction to instruct the selective merging is read,
When the register (3) is on and the state of the transfer destination step is inactive, the transfer destination step is activated and the transfer source step of the address stored in the third register (5) is deactivated. Also, the first register (3) is interlocked to the off state through the second register (4), while the first register (3) is in the off state or the state of the transition destination step is active. When the instruction for declaring the end of merging is read, the second register (4) is initialized to set the first register (3) to the settable state. The fifth register
The programmable controller according to claim 1, wherein the processing is immediately terminated after confirming that the data set in (7) instructs the first selection of the processing procedure of the instruction. 3. The analysis means (2) further comprises a fourth register (6) for storing the program address of a branch or merge instruction read by the analysis means (2), and the analysis means (2) detects the start of a parallel branch. When the instruction to be declared is read, the second register (4) is initialized so that the first register (3) can be set and the fifth register (7) receives the second instruction processing procedure. When the data for instructing the selection of is set, the start program address of the next instruction is set in the fourth register (6), and the instruction for detecting the active / inactive state of the migration source step in the parallel branch is read. Is the second register when the state of the detected transition source step is inactive.
The first register (3) is interlocked to the off state via (4), while when the detected state of the transfer source step is active, the address of the transfer source step is set to the third register (5). ) And read the instruction to detect the on / off state of the transition, output the data to set the on state to the first register (3) when the detected state of the transition is on. On the other hand, when the detected state of the transition is off, the data for setting the off state to the first register (3) is output, and when the instruction for parallel branch is read,
When the data set in the register (7) is instructing the second selection of the instruction processing procedure and the first register (3) is in the OFF state, the processing is terminated, and the first register (3) is terminated. Even when the 1 register (3) is in the ON state and the state of the transition destination step is inactive, the processing is terminated and the first
When the register (3) is in the ON state and the state of the transition destination step is active, the data for setting the OFF state to the first register (3) is output, while the fifth register is output.
When the data set in (7) indicates the first selection of the instruction processing procedure, the migration destination step is activated and the migration source of the address stored in the third register (5) is also activated. When the step is deactivated and the instruction declaring the end of branch is read, the second register (4) is initialized to make the first register (3) settable, and then the fifth register (5) is set. register
When the data set in (7) indicates the second selection of the instruction processing procedure, the processing is terminated when the first register (3) is in the off state, and the first register (3) is When in the ON state, after setting data for instructing the first selection of the instruction processing procedure in the fifth register (7), jump to the program address set in the fourth register (6), while The programmable controller according to claim 1, wherein when the data set in the fifth register (7) indicates the first selection of the instruction processing procedure, the processing is immediately ended. 4. The analysis means (2) sets the first register (3) in a settable state by initializing the second register (4) when reading an instruction declaring the start of parallel merging. In addition, the data for instructing the second selection of the instruction processing procedure is set in the fifth register (7), and the start program address of the next instruction is set in the fourth register (6). When the instruction for detecting the active / inactive state of the transition source step in
When the data set in (7) indicates the second selection of the instruction processing procedure, if the state of the transfer source step is active, the processing is terminated and the state of the transfer source step is deactivated. If it is, the first register (3) is interlocked to the off state via the second register (4), while the data set in the fifth register (7) is the first in the instruction processing procedure. When instructing to select 1,
When the source step is deactivated and the instruction for parallel merging is read,
When the data set in the register (7) is instructing the second selection of the instruction processing procedure and the first register (3) is in the off state, the processing is terminated and the first
Even when the register (3) is in the ON state and the state of the transition destination step is active, the processing is terminated and the first register
When (3) is in the ON state and the state of the transition destination step is inactive, the transition destination step is activated, while the data set in the fifth register (7) is the first in the instruction processing procedure. When the instruction to select 1 is given, the processing is ended, and when the instruction declaring the end of the merge is read, the first register (3) is set by initializing the second register (4). After enabling, the fifth register
When the data set in (7) indicates the second selection of the instruction processing procedure, the processing is terminated when the first register (3) is in the off state, and the first register (3) is When it is in the ON state, the fifth register (7) is set to the data for instructing the first selection of the instruction processing procedure, and then the program address set in the fourth register (6) is jumped to. 4. The programmable controller according to claim 3, wherein when the data set in the fifth register (7) indicates the first selection of the instruction processing procedure, the processing is immediately ended.