JPH06259583A - Connecting method for data driving type processor - Google Patents

Abstract

PURPOSE:To provide a connecting method for a data driving type processor capable of inputting/outputting a data packet between all the processors and shortening a packet transmission route selected at that time in a system where plural data driving type processors are coupled in multi-network shape. CONSTITUTION:Routers 5, 6 are provided at the input stage and output stage of a system, respectively, and the router inputs the data packet, and selects a transmission route so as to shorten the route on which an input packet arrives at the processor by which it is to be processed, and supplies the input packet to the processor in the system via a selection path. Each processor inputs the data packet and processes it and sends it out selectively to the transmission path where the route on which the data packet obtained as a result of processing arrives at the processor by which it is to be processed can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting data driven processors, and more particularly to a method for connecting a plurality of data driven processors in a multi-network form.

[0002]

BACKGROUND OF THE INVENTION AND PROBLEMS TO BE SOLVED BY THE INVENTION Applicants propose a method of connecting a data driven processor disclosed in Japanese Patent Application No. 4-117406. In this connection method, it becomes possible to change the destination of data in a programmable manner without changing the wiring of the connection between the data driven processors. However, when the number of data-driven processors to be connected increases, the path between the processors becomes long, and a processor pair that cannot directly exchange data occurs. Then, as a secondary problem from the latter problem, an additional burden is placed on the processor used for relaying indirect data exchange, and a program to be given to the processor becomes complicated.

Therefore, an object of the present invention is to allow data packets to be exchanged between any of the processors when each of the plurality of data driven processors is connected in a multi-network form using a transmission line. It is an object of the present invention to provide a method of connecting a data driven processor which shortens the transmission path of a data packet selected at that time.

[0004]

According to a first aspect of the present invention, there is provided a data-driven processor connecting method, wherein a plurality of data-driven processors are connected in a multi-network form using inter-processor transmission lines. By transmitting a data packet storing processor designation information that designates the processor that should process itself,
A connection method for mutually connecting each processor,
The system further has an input path selection unit at its input stage, and this selection unit inputs a data packet given from the outside of the system, and sets a predetermined first condition and processor designation information of the input packet. It is configured to send the input packet to the interprocessor transmission path selected based on the above.

Each processor inputs a data packet provided from the input path selection unit or another processor through the interprocessor transmission path and processes the information, and the obtained data packet is predetermined as the processor designation information. It is configured to be transmitted to the outside of the system or another processor via the interprocessor transmission path selected based on the second condition.

The first path set in the input path selection section
The condition and the second condition set for each processor are set so that the path for the data packet to reach the processor to be processed is shortened.

According to a second aspect of the present invention, there is provided a method of connecting a data driven processor, wherein the above system is connected to another system via an intersystem transmission line.
The system is configured to further include an output path selection unit at its output stage. Then, each processor transfers the data packet obtained by the information processing to another processor or an output path selection unit via the interprocessor transmission path selected based on the processor designation information and the second condition. The data packet is transmitted, and the output path selection unit inputs the data packet given via the interprocessor transmission path, and is selected based on the predetermined third condition and the processor designation information of the input packet. It is configured to send the data packet to the intersystem transmission line.

Then, the third set in the output path selection section
The conditions are set such that the path taken by the data packet to reach the processor to be processed is short.

[0009]

In the method of connecting a data driven processor according to claim 1 or 2, an input path selection unit is provided at an input stage of a system in which a plurality of data driven processors are connected in a multi-network form, and the input path selection unit is connected to the system. The selected data packet is selectively transmitted to a transmission path that shortens the path to reach the processor to be processed based on the processor designation information and the first condition of the input path selection unit, and the data packet is transmitted within the system. Given to the processor. Further, each processor in the system receives a given data packet, processes the information, and shortens the path for the data packet to reach the processor to be processed based on the processor designation information and the second condition. It is sent to such a transmission line.

Therefore, the movement route of the data packet is shortened in this system. Furthermore, each time the input route selection unit and each processor output a data packet, the route that can reach the processor to which the packet is to be processed is selected, so that data can be exchanged between any of the processors in the system. It is possible to input and output packets.

Further, in the method of connecting a data driven type processor according to a second aspect, when the above-mentioned system is mutually connected to another system through an inter-system transmission line, it is provided in an output stage of each system. A system in which the output route selection unit shortens the route until the data packet reaches the processor to be processed based on the processor designation information of the data packet output from the system and the third condition. The packet is sent to the inter-transmission path and given to another system. Therefore, even when the above-mentioned systems are connected in multiple, the movement route of the data packet is shortened, and further, the input route selecting unit and the output route selecting unit of each system, and each time the data packet is output in each processor. Since a path that can reach the processor to process the packet is selected, the data packet can be input / output between any of the processors in the multiplexed system.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a conventional Neumann computer, various instructions are stored in a program memory in advance as a program, and the instructions of the program memory are sequentially read out by sequentially designating the addresses of the program memory, and the instructions are executed. It

On the other hand, the data driven processor is a kind of non-Neumann computer that does not have the concept of sequential instruction execution by a program counter. For such a data driven processor, an architecture based on parallel processing of instructions is adopted. In the data-driven processor, instructions can be executed as soon as the data to be operated are prepared, and a plurality of instructions are driven simultaneously by the data, so that the programs are executed in parallel according to the natural flow of data. . As a result, it is considered that the time required for the calculation is significantly reduced.

FIG. 1 is a diagram showing the configuration of a system including a plurality of data driven processors according to an embodiment of the present invention. This system consists of data driven processors 1-
4 and routers (route selectors) 5 and 6, each data driven processor and each router having inputs A and B.
And outputs C and D. Also, the system of FIG. 1 has inputs IN1 and IN2 and output OUT1.
And OUT2.

FIG. 2 is a block configuration diagram of a data driven type processor according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of contents stored in the program storage unit of FIG. 2, and FIG. It is a field block diagram of the data packet processed in the processor of FIG. The data packet of FIG. 4 has an instruction field 79 for storing an instruction code,
It includes a generation field 80 for storing a generation number, a data field 81 for storing data, a processor number field 82 for storing a processor number PN, and a node number field 83 for storing a node number.

Referring to FIG. 2, the data driven processor receives the data packets and inputs the data packets, and merges the data packets. The data packets are input and the contents of the data packets are set in the internal memory in advance. Branching units 62, 6 for comparing the input data packet to the output destination selected according to the comparison result.
7 and 70, a program storage unit 64 for storing a data flow program as shown in FIG. 3, a pair data detection unit 65, an arithmetic processing unit 66, and an internal data buffer unit 68.

The merging unit 61 inputs the data packet given from the input A or B and sequentially outputs it to the branching unit 62.
The branching unit 62 stores a processor number for uniquely identifying the data driven processor in the memory 621 in advance, inputs a given data packet, and sets the processor number PN of the input packet and the memory 621. It is determined whether the processor numbers match. When both numbers match, the branching unit 62 outputs the input packet to the merging unit 63, and the merging unit 63 gives the input packet to the program storage unit 64. On the other hand, when the processor numbers do not match, the input data packet is merged by the merging unit 69.
Is output to the merging unit 69 and the supplied data packet is input to the branching unit 70. The branching unit 70 sends the input data packet to one of the outputs C and D according to the processor number PN of the input data packet and the branching condition preset in the memory 701.

As shown in FIG. 3, the program storage unit 64 stores in advance a data flow program consisting of a plurality of instruction codes, a plurality of node numbers and a plurality of processor numbers. The program storage unit 64 inputs a given data packet, and reads the next node number, instruction code and processor number from the data flow program by addressing based on destination information of the input packet, that is, generation number or node number. The read node number, instruction code, and processor number are stored in the node number field 83, instruction field 79, and processor number field 82 of the input data packet, respectively, and the input data packet is paired with the data detection unit 65.
Is output to.

The data pair detector 65 waits for the data packet output from the program memory 64.
That is, two different data packets having the same destination information (information consisting of a node number or a generation number) are detected, and the content of the data field of one of the data packets is changed to the data field of the other data packet. And the other data packet is output to the arithmetic processing unit 66.

The arithmetic processing unit 66 inputs the data packet output from the paired data detection unit 65, performs arithmetic processing based on the instruction code of the input packet, and stores the result in the data field of the input packet. The input data packet is output to the branch unit 67.

The branching unit 67 inputs the data packet output from the arithmetic processing unit 66, determines whether the processor number PN of the input packet matches the processor number of the processor preset in the memory 671, and matches the same. If so, the input packet is output to the internal data buffer unit 68. If they do not match, the input data packet is merged into the merging unit 6.
Output to 9.

The internal data buffer unit 68 inputs the supplied data packets and sequentially outputs them to the merging unit 63.

In the data driven processor, the data packet is stored in the program storage unit 64 based on the program, the pair data detection unit 65 → arithmetic processing unit 66 → internal data buffer unit 68 → merging unit 63 → program storage unit 64. → It is processed by continuing to rotate in order. Then, the data packet output from the branch unit 70 of the data driven processor to the outside of the processor is given to the data driven processor connected to the next stage and processed in the same manner.

Whether the processor number or branch condition set in each memory of the branch units 62, 67 and 70 is set prior to program execution using an external terminal (not shown) connected to the processor. , Also set using software.

FIG. 5 is a block diagram of a router according to an embodiment of the present invention. The router includes input control units 71 and 72 for connecting inputs A and B, respectively, and a branching unit 7.
3 and 74, merging points 75 and 76, and output C
Output control sections 77 and 7 for connecting respectively
Including 8. The input control units 71 and 72 input data packets given from outside the router, and sequentially branch the data packets.
3 and 74 respectively.

The branch units 73 and 74 include memories 731 and 741, respectively. Memories 731 and 74
An external terminal or software is used for 1 to set a branch condition in advance. The branching units 73 and 74 selectively output the input data packet to one of the merging units 75 and 76 based on the processor number PN of the input packet and the branching condition preset in the memory. For example, the branch condition set in the memory 731 or 741 is that if the least significant bit of the processor number of the input data packet is 0, the input packet is output to the merging unit 75,
If it is 1, the input packet may be output to the merging unit 76. The setting of this branch condition is set so that the path until the input data packet reaches the data driven processor to be processed is the shortest.

The merging units 75 and 76 sequentially input the supplied data packets and output them to the output control units 77 and 78, respectively, and the output control units 77 and 78 successively output the supplied data packets to the output units C and D, respectively. To do.

Here, in the system constructed on the multi-network of FIG. 1, the data packet given to the system from the input IN2 is processed by the data driven processor 1 and then processed by the data driven processor 4. , It is assumed that the output OUT2 is output to the outside of the system, and the route of the data packet in this case is considered. However, the data driven processors 1, 2, 3 and 4 have processor numbers of 0000 and 00, respectively.
It is assumed that 01, 0010, and 0011 are set, respectively, and further, that the data-driven processors (not shown) connected to the outputs OUT1 and OUT2 are set to processor numbers 1000 and 1100, respectively. To do.

Further, the data driven processors 1 and 2 and the router 5 send the packet to the output C when the least significant bit of the processor number PN of the data packet is 0, and when the least significant bit is 1, the packet is sent. A branch condition for sending to the output D is set in advance, and the data driven processors 3 and 4 are the top 2 of the processor number PN of the data packet.
If the bit is 00, send the packet to output C,
In other cases, it is assumed that a branch condition for sending the packet to the output D is set. In addition, the router 6 is 2 from the top of the processor number PN of the data packet.
It is assumed that a branch condition is set in advance such that the data packet is sent to the output C when the bit is 0, and the packet is sent to the output D when the bit is 1.

First, a data packet having a processor number PN of 0000 is input from the system input IN2 to the router 5
Input B of The router 5 inputs the given data packet, and the processor number PN of the input packet
= 0000 and the branch condition that the least significant bit is 0, the input data packet is sent to the output C and given to the input B of the data driven processor 1.

The data driven processor 1 inputs the data packet given to the input B, internally processes it and rewrites the processor number PN of the input data packet to 0011. In rewriting the processor number, the next processor number read from the program storage unit 64 by addressing based on the content of the input data packet is stored as the processor number PN in the processor number field 82 of the input data packet. It is done by The input data packet in which the processor number PN is rewritten to 0011 is sent to the output D based on the branch condition that the least significant bit is 1, and is given to the input A of the data driven processor 4.

The data driven processor 4 inputs and processes the data packet whose processor number PN given to the input A is 0011. In this process, the processor number PN is rewritten to 1100 by the next processor number read from the program storage unit 64 so that the data packet is sent to the output OUT2, and the upper two of the processor numbers PN of the data packet. Based on the condition that the bit is not 00, the data packet is sent to the output D of the data driven processor 4.

The data packet sent to the output D of the data driven processor 4 is given to the input B of the router 6,
The router 6 determines the processor number PN of the input data packet
= 1100 and the branch condition that the second bit from the top is 1, the input data packet is sent to the output D.
Then, the data packet is given to the external data-driven processor (not shown) whose processor number is 1100 via the output OUT2 of the system.

FIG. 6 is a block diagram showing the system of FIG. 1 with the router removed. In the system of FIG. 6, the same operation as described above (a data packet is input from the input IN2 of the system, and after the data packet is processed by the data driven processor 1, the data packet is processed by the data driven processor 4, Then the system output OU
It is assumed that the data is output from T2 to a data driven processor outside the system having a processor number of 1100).

First, when a data packet whose processor number PN is 0000 is input to the system from the input IN2, the input data packet is given to the input A of the data driven type processor 2. The data driven processor 2 inputs and processes a given data packet, and since the least significant bit of the processor number PN is 0, the input data packet is input to the data driven processor 3 via the output C of the processor 2. Given to B. The data driven processor 3 inputs and processes the given data packet, and the upper 2 of the processor number PN of the input data packet.
Since the bit is 00, the input data packet is given to the data driven processor 1 via the output C of the data driven processor 3.

The data driven processor 1 inputs and processes a data packet via input A. In this processing, the processor number PN of the input data packet is 001.
Rewritten to 1. Since the least significant bit of the rewritten processor number PN is 1, the input data packet is given to the input A of the data driven processor 4 via the output D of the processor 1. The data driven processor 4 inputs and processes the data packet given to the input A. In this process, the processor number PN of the input data packet is rewritten to 1100. Since the upper 2 bits of the processor number PN of the data packet are not 00, the data packet is sent to the output D of the data driven processor 4 and the processor number outside the system is 1100 via the output OUT2. Given to.

As described above, when the same processing contents are executed in the system having the router shown in FIG. 1 and the system having no router shown in FIG. 6, the moving route of the data packet being processed is that shown in FIG. It can be seen that it is significantly shorter than that of 6. That is, in the system of FIG. 1 in which a router is attached, when a data packet is given to the system, the router first causes the processor number P of the data packet.
Based on N, a route that allows the data packet to reach the processor to be processed by the shortest route is selected, and the data packet is sent to the selected route side. It can be greatly shortened.

FIG. 7 is a block diagram of a large-scale system including four systems of FIG. 1, and FIG.
FIG. 7 is a block configuration diagram of a large-scale system including four systems of FIG. 6.

The system having the multi-network configuration shown in FIG. 7 includes groups 36 to 39 having the same configuration as the system shown in FIG. Each processor in the system is assigned a processor number as shown.
Focusing on the upper 2 bits of the processor number, the group 36 is the 00 group, the group 37 is the 01 group, the group 38 is the 10 group, and the group 39.
Are uniquely classified into 11 groups. Hereinafter, it is assumed that group numbers 00, 01, 10 and 11 are sequentially assigned to each group in order to individually identify the groups 36 to 39.

Each group has a router on each of the input side and the output side of the group, and further has two processors connected to the input side router and two processors connected to the output side router. The branching conditions set in the input side router and the output side router of each group are shown in Fig. 1.
1 is the same as that set in each of the routers 5 and 6 shown in FIG. 1, and the branching conditions set in the two processors connected to the input side router are also the branch conditions set in each of the processors 1 and 2 shown in FIG. Is assumed to be the same as that set for. Further, the two processors connected to the output side router of each group send the input data packet to the output C if the upper 2 bits of the processor number PN of the input packet match the group number of the group, and if they do not match. If there is, it is assumed that the branch condition for sending the data packet to the output D is set. The same branching condition as that of the router 6 is set in the router 35.

The system of FIG. 8 is configured by excluding the router of the system shown in FIG. 7, and the branch condition and processor number set for each processor are as shown in FIG.
Same as those of.

In the multi-network system shown in FIG. 7 and the system shown in FIG. 8 having the above-mentioned settings, the data driven processor 15 (processor number 0100) to the data driven processor 23 (processor number 1100). It is assumed that a process of sending a data packet is performed.

In the case of the system of FIG. 7 in which the router is attached, the data packet processed by the data driven processor 15 and the processor number PN of which is rewritten as 1100 has the least significant bit of 0, so that the processor 15 From the output C to the input A of the processor 17.

The following processing is performed inside the processor 17. The data packet provided from the input A to the merging unit 61 is sequentially output to the branching unit 62. In the branching unit 62, the processor number PN of the data packet and the processor number (011
This data packet is sent to the merging unit 69 because it is detected that 0) does not match. The merging unit 69 sequentially sends the sent data packets to the branch unit 70, and the branch unit 70 sends the sent data packets through the output D on the condition that the group number is not 01.

By the procedure as described above, the processor 17
The data packet given to the input A of the same is sent out from the output D of the same processor and given to the input A of the router 30. The router 30 sends the supplied data packet from the output D to the input B of the router 33 based on the condition that the second bit from the top of the processor number PN is 1. The router 33 inputs the given data packet, and based on the least significant bit of the processor number PN of the input packet being 0, gives the input data packet to the processor 23 via the output C.

In contrast to the system of FIG. 7 as described above, the system of FIG.
The data packet sent from the processor 17 is processed by the processor 17 and is the same as that from the output D of the processor 17 to the output D, but the data packet sent from the output D of the processor 17 is given to the input A of the processor 20. It will be. The processor 20 inputs the given data packet and sends the input data packet from the output C based on the least significant bit of the processor number PN of the input packet being 0.
To input B of. The processor 21 inputs the given data packet, and sends the input packet from the output D to the input B of the processor 11 on the condition that the upper 2 bits of the processor number PN of the input data packet is not the group number (10). give. Since the processor number PN of the data packet given to the input B of the processor 11 is 1100, the data packet should be circulated in the loop of processor 11 → processor 13 → processor 19 → processor 21 → processor 11 → ... Forever. Then, the data packet does not reach the intended data driven processor 23, and the processing in the system stagnates.

In the router-less system of FIG. 8, in order to solve the above problem, the processor 24 (processor number 1101) is used as a relay point, that is, the processor number of the data packet sent from the processor 15. It is necessary to set PN to 1101 first, and to rewrite the processor number PN of the data packet to 1100 when it is given to the processor 24.

As described above, in the system equipped with the router shown in FIG. 7, the data packet can be freely moved from one processor to another processor.
On the other hand, in a multi-network system without a router as shown in FIG. 8, for example, a data packet can be sent directly from the data driven processor 15 (processor number 0100) to the data driven processor 23 (processor number 1100). As impossible,
The movement target of the data packet is limited. In addition, if another processor is used as a relay point in order to prevent the data packet from circulating forever in the loop as described above, the load on the processor used as the relay point increases and the program It gets complicated.

Therefore, by using the router, even when a large-scale multi-network system is constructed, data packets can be moved between all processors, and the program supplied to the data driven processor is not complicated. Therefore, it is possible to increase the processing speed. Moreover, the algorithm for route selection may be the same as that shown in FIG.

When a process that does not require the routers 5 and 6 is executed, the router is removed as shown in FIG.
It can have the same structure as.

[0051]

According to the method of connecting a data driven processor according to the first or second aspect of the present invention, in a system in which a plurality of data driven processors are coupled in a multi-network form, the input path selection unit at the input stage of the system is Data packets input to the system are selectively transmitted to a transmission path such that a path for reaching the processor to be processed is short, and each processor inputs a given data packet, Information processing and data packets obtained as a result of processing are selectively transmitted to a transmission path that shortens the path for reaching the processor to be processed. The moving path of the data packet of is shortened.

Further, in the method of connecting a data driven processor according to the first or second aspect, the input route selecting unit and each processor provide a route which can reach the processor to be processed each time a data packet is output. As a result of selection, data packets can be input / output between any processors in the system.

According to the data-driven processor connection method of the second aspect, even when the above-mentioned systems are connected in a multiple manner, the output path selectors provided in the output stages of the respective systems are Since the packet is selectively transmitted to the inter-system transmission path such that the moving path of the data packet output from the system is shortened and given to another system,
The movement path of data packets between systems or between data-driven processors can be shortened, and the input path selection unit and the output path selection unit and each processor reaches the processor to be processed each time the data packet is output. Since a possible route is selected and transmitted, data packets can be input / output between any of the processors and between any of the systems even when the systems are connected in multiple as described above.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a system including a plurality of data driven processors according to an embodiment of the present invention.

FIG. 2 is a block diagram of a data driven processor according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of stored contents of a program storage unit of FIG.

4 is a field configuration diagram of a data packet processed in the data driven processor of FIG. 2. FIG.

FIG. 5 is a block diagram of a router according to an embodiment of the present invention.

FIG. 6 is a block diagram of the system of FIG. 1 excluding a router.

7 is a block calibration diagram of a large scale system including four of the systems of FIG.

8 is a block calibration diagram of a large scale system including four of the systems of FIG.

[Explanation of symbols]

 1 to 4, 1 to 26 data driven processor 5, 6, 27 to 35 router 36 to 39, 56 to 59 group 61, 63, 69, 75, 76 merging part 62, 67, 70, 73, 74 branching part 64 Program storage unit 65 Pair data detection unit 66 Arithmetic processing unit 68 Internal data buffer unit 71,72 Input control unit 77,78 Output control unit 82 Processor number field 621, 671, 701, 731, 741 Memory PN Processor number Note that each figure The same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] 1. In a system in which a plurality of data driven processors are mutually coupled using an inter-processor transmission path, a data packet storing processor designation information designating a processor to process itself is transmitted. A method of connecting data-driven processors, wherein the respective processors are connected to each other by communication, wherein the system further has an input path selection unit at an input stage of the system, and the input path selection unit is the system. The data packet provided from the outside of the processor, and outputs the input packet to the inter-processor transmission path selected based on a predetermined first condition and the processor designation information of the input packet, Is given from the input path selection unit or another processor via the interprocessor transmission path. Information processing by inputting the data packet to be processed, and the data packet obtained by the information processing is selected as the interprocessor transmission path based on the processor designation information and a predetermined second condition. To the outside of the system or to another processor via, and the first and second conditions are set so that the path for the data packet to reach the processor to be processed is shortened. A method of connecting a data driven processor. 2. The system further includes an output path selection unit at an output stage of the system when the system is mutually connected to another system via an inter-system transmission path, and each processor is The output path selection unit or another processor via the interprocessor transmission path selected based on the processor designation information of the data packet obtained by information processing and the predetermined second condition. A data packet is transmitted, and the output path selection unit inputs the data packet given via the interprocessor transmission path, and selects based on a predetermined third condition and processor designation information of the input packet. The input data packet is transmitted to the inter-system transmission path that has been processed, and the third condition is that the processor reaches the processor where the data packet is to be processed. Wherein the route to is set to be shorter, the connection method for data driven processor of claim 1.