JPH0761015B2 - A / D conversion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In the A / D conversion method, in order to eliminate an error in a digital value after A / D conversion at a discontinuous point of an analog signal, a digital value is converted into a digital value at the discontinuous point. By using the boundary value of the input range of the / D converter, the error is eliminated.

[Industrial application field]

The present invention relates to an A / D conversion method for converting an analog signal (A) into a digital signal (D), and particularly, an error is removed when converting an analog signal into a digital signal at a discontinuous point.
Regarding A / D conversion method.

[Problems to be Solved by Prior Art and Invention]

For example, in head position control of a magnetic disk device, control of a servo system for positioning the head is performed by a computer after converting an analog signal indicating the head position into a digital value. Figure 5 is conventional
1 is a schematic configuration diagram of an A / D conversion system, showing an analog signal A
Is inputted to the A / D converter ADC and then sampled to be converted into a digital signal D, which is taken into the central processing unit CPU via the bus line B. In this case, the signal input to the A / D converter is usually used in a range not exceeding the maximum width of the allowable input range in consideration of the performance of the A / D converter. Therefore, the gain of the input analog signal is limited to the input range of the A / D converter and a discontinuity occurs. On the other hand, the type of temporal fluctuation of the analog signal input to the A / D converter is shown in FIG.
There are various types as shown in (f). That is, there are sawtooth waves as shown in (a), triangular waves as shown in (b), and random waveforms as shown in (c) to (f). Here, R is the input range of the A / D converter as described above. That is, in actual use, analog signals in this range are converted into digital values.

By the way, the conversion time to the digital value in the A / D converter is determined by the conversion performance of the A / D converter. However, in the recent A / D converter which is made into an LSI, the logical signal BUSY indicates “0”. It is output as the time at the state value of. Here, in a system in which the A / D conversion is repeated at a certain fixed cycle and the converted digital signal is read by the CPU, if the input analog signal is not synchronized with the sampling frequency, A / D conversion is performed.
If the D conversion timing coincides with the discontinuous point of the analog signal, the A / D converted digital value may include a large error.

FIG. 7 is a diagram for explaining the error of the digital value at the time of sampling described above. In FIG. 7, the sawtooth waveform shown in FIG. 6 (a) is adopted to simplify the explanation. In FIG. 7, S is the sampling period, T is the A / D conversion time,
Black points P ₁ and P ₂ are discontinuities of the analog signal generated by the input range R of the A / D converter, and R is the input range of the A / D converter. As can be seen from the figure, the digital value can be uniquely obtained by the digital conversion of the sampling (white circles) of the part where the analog signal is continuous, but the digital conversion of the sampling at the discontinuity points P ₁ and P ₂ . Then P
_A large error occurs when the digital signal conversion value of ₁ is adopted and when the P ₂ 2 digital conversion value is adopted, and the accuracy of the entire system deteriorates if signal processing in the subsequent stage is performed using a digital value that includes this error. Will come.

In order to solve such a problem, a circuit that avoids the sampling timing of A / D conversion and the discontinuous change of the analog signal is conceivable, but such a circuit is very complicated and costly. Has not reached. An object of the present invention is to eliminate the error of the digital conversion value at the discontinuity point of the analog signal by adding a simple circuit to the conventional A / D conversion circuit and processing it by software.

[Means and Actions for Solving Problems]

In the present invention, means for generating a pulse by comparing with a reference value at the timing when the analog signal causes a discontinuous change, and means for counting the pulse are added in parallel to the A / D converter, and the CPU Every time the / D conversion value is read, the count value of the counter is also read at the same time, and the routine that determines the discontinuous change in the analog signal based on the change in the counter value is used instead of adopting the digital value obtained at that time. As the correct digital value, the maximum value of the A / D input range, or remarkably the minimum value (that is, the boundary value) is adopted. That is, the A / D conversion method according to the present invention includes means for generating a pulse (CMP) that synchronizes with the timing at which the analog signal changes discontinuously near the boundary value of the allowable input range of the A / D converter, and the pulse. An analog that includes a means for counting (CNT), the CPU reads the count value of the counter at the start and end of A / D conversion, and changes discontinuously when the count value is different at the start and end. Signal
It is determined that A / D conversion has been performed, and the boundary value is adopted as the A / D conversion value.Furthermore, the CPU reads the count value of the counter at the start of the A / D conversion, and reads the read value. An analog signal that changes discontinuously when the previous read value is compared and the comparison result is the same value and the difference between the current A / D converted value and the previous A / D converted value is negative. A / D
It is determined that the conversion is performed, and the boundary value is adopted as the A / D conversion value.

〔Example〕

FIG. 1 is a block diagram of an embodiment of an A / D conversion system according to the present invention. In FIG. 1, the same components as those of the related art are designated by the same reference numerals. CMP is a comparator, which is a circuit that compares the analog signal A with the reference voltage V _ref to obtain the output S ₁ . In this case, V _ref is 0 (V). CNT is a counter, which increments under the constant condition of the comparator output S ₁ to obtain a digital output S ₂ . The digital value D from the A / D converter and the counter output S ₂ are simultaneously read by the CPU via the bus line B, and S ₂ as described below.
At the trailing edge of, the digital value D is replaced with a boundary value to obtain a correct conversion value.

FIG. 2 is a diagram for explaining the relationship between the analog signal A and the comparator output S ₁ . When the analog signal A is a sawtooth wave as shown, discontinuities P ₁ and P ₂ occur at the boundary of the allowable input range R as described above. When such an analog signal A is compared with the reference voltage V _ref (= 0V) by the comparator CMP, the output pulse is S ₁ synchronized with the analog signal.
become that way. As is clear from the figure, the analog signal A
When changes from the point P ₁ to the point P ₂ , the output pulse S ₁ falls. The counter CNT counts up at this falling edge to detect the discontinuity point of the analog signal.If the counter value does not change, it means that the analog signal changes to the continuous point on the upper right slope. However, if there is a change, then the digital value contains an error because it is a discontinuity point of the analog signal, and the boundary value is adopted as the correct conversion value.

FIG. 3 shows a processing flowchart of the CPU of FIG. First, the CPU reads the initial value C ₁ of the counter CNT (step 31), then the CPU starts digital conversion by the A / D converter ADC (step 32), and after waiting for a predetermined time (step 33), A Read the / D conversion value (step 34). CPU
Waits until A / D conversion is completed, and then repeat the counter value C ₂
Is read (step 35), and the initial counter value C ₁ is compared with the current counter value C ₂ (step 36). here,
If C ₁ = C ₂ , it means that the counter value has not changed and therefore the analog signal continuously changes, and the CPU directly adopts the converted digital value (step 37). If C ₁ ≠ C ₂ , that is, if the counter value has changed, it means that the trailing edge has been counted, indicating that the analog signal is a discontinuity point. The input range boundary value is adopted instead of the digital value including (step 38).

This method is effective in (a), (d), and FIG.
This is the case of an analog signal waveform that changes only in one direction, such as (e). This is because, as is clear from the figure, in this case, the pulse always shows a trailing edge at the discontinuous point.
Therefore, as described above, the counter may count the falling edges. On the other hand, for analog signal waveforms that change in both positive and negative directions such as (b), (c), and (f), unlike the above-described counter, a pulse generation circuit that does not count up below the signal discontinuity point is used. It is necessary to provide.

FIG. 4 is a processing flowchart of another embodiment. This method can be adopted when an analog waveform as shown in FIGS. 6 (a) and 6 (d) is used. In FIG. 4, CA is the counter value at the start of A / D conversion, CB is the counter value at the time of the previous reading, AA is the A / D conversion value read this time, and AB is the previous reading value. First, the CPU reads the counter value CA (step 41) and starts A / D conversion (step 4).
2) Wait until A / D conversion is completed (step 43), then
The D conversion value AA is obtained (step 44). The CPU then compares the previous counter value CB with the previous counter value CA (step 45), and if the same value does not change, the previous A / D conversion value AB and the current A
The / D conversion AA is compared (step 46). In this case, as indicated by the white dots on the analog signal in Fig. 2, when the value of AA is smaller than the value of AB, AA-AB becomes a negative value, indicating that the point has passed through the discontinuity point. Adopt a value (step 47). When AA-AB is positive, the analog signal continuously changes as indicated by the black dots, so AA is adopted as the read value (step 49). On the other hand, if the previous counter value CB and the current counter value CA are different and AAAAB indicates that the analog signal is continuously changing as shown by the black dots, the read value AA can be used as it is. (Step 49) Then the counter is initialized (Step 48) and the routine is repeated again. As is apparent, this method has an advantage that the operation of reading the counter value is sufficient for each cycle.

It should be noted that when the boundary value is adopted, which of the positive and negative boundary values is used may be determined in relation to the subsequent stage, and it is clear that the boundary value is adopted.

〔The invention's effect〕

As described above, according to the present invention, the error of the digital value caused by the discontinuous change of the analog signal at the maximum value or the minimum value which is the boundary value of the A / D converter input range is replaced with the boundary value. By doing so, it is possible to provide a highly accurate change value to the subsequent stage, and the accuracy of the entire digital system is improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment according to the present invention, FIG. 2 is a diagram for explaining a relationship between an analog signal and a counter output, FIG. 3 is a processing flowchart of an embodiment according to the present invention, and FIG. FIG. 5 illustrates a conventional configuration diagram, FIG. 6 (a) to FIG. 6 (f) illustrate various analog signal waveforms, and FIG. 7 illustrates an A / D conversion error. It is a figure. (Description of symbols) ADC: A / D converter, CPU: central processing unit, CMP: comparator, CNT: counter, B: bus line.

Claims (1)

[Claims] 1. An analog signal (A) which continuously changes within a permissible input range of an A / D converter and which changes discontinuously near a boundary of the input range is converted into a digital signal (D).
In the A / D conversion method for converting to, means for generating a pulse that is synchronized with the timing at which the analog signal changes discontinuously near the boundary of the input range, and from the conversion start time of the A / D converter to the conversion end Means for detecting a pulse synchronized with the discontinuity point by the time, when a pulse synchronized with the discontinuity point is detected between the conversion start time and the conversion end time of the A / D converter, An A / D conversion method comprising: a unit that adopts a boundary value of the input range as an A / D conversion value.