JPH0116004Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a circuit that detects a pulse signal from a signal having a fluctuating DC component.

There is an 8 called pilot on the rotation axis of the water meter.
A pyramidal reflector is provided, and a photoelectric element converts the reflected light from the pilot into an electrical signal, and detects eight pulse signals included in this electrical signal per revolution of the rotating shaft. Automatic verification of meters has been carried out, but because the pilot is not accurately attached concentrically to the rotating shaft, the electric signal from the photoelectric element contains a fluctuating DC component with the same period as one revolution of the rotating shaft. is mixed in. When inspecting water meters using a pilot, the flow rate ranges from small to large, and the signal pulse frequency ranges from 0 to several hundred Hz.
In addition, in older water meters, the pilot's reflective surface is dirty, so the fluctuating DC component mentioned above may be mixed in.The pulse signal obtained from the reflected light from the eight reflective surfaces of the octagonal pyramid is detected. It is difficult to do so. Conventionally, there are various ways to extract pulse signals contained in signals with fluctuating DC components.
For example, a method using a differentiating circuit using CR has also been used, but it is undetectable at extremely low frequencies.

In view of the above, the purpose of this invention is to propose a new electric circuit that reliably detects a pulse signal from a signal having a fluctuating DC component over a wide frequency range.

Next, it will be explained based on the drawings.

FIG. 1 shows the pulse output B detected by the detection circuit of this invention from the input electrical signal A from the octagonal pyramidal pilot of the water meter. T is the time (period) of one rotation of the pilot, and the input electrical signal A includes a fluctuating DC component with period T.

Fig. 2 shows an outline of the relationship between signal A and pulse output B. At time _t1 when signal A rises by a certain minute amount ΔV from the minimum point _P1 , the output becomes "H" level.
At time _t2 when the output has decreased by a minute amount ΔV from the maximum point P2, the output becomes _the "L" level, and similarly at time _t3 when the output has increased by a minute amount ΔV from the next minimum point _P3 , the output becomes the "H" level. The circuit is activated. That is, the point where the input signal A shifts to rise or fall is detected and the output level is changed to "H" or "L" level to obtain a pulse output.

The circuit of this invention, as shown in FIG. connected and configured. A specific example of analog adders 1 and 2 is shown in Figure 3. When the control input is "H", a constant value ΔV is added to the signal input and output, and when the control input is "L", the signal input is It has a function to output as is. (This example is a case where ΔV ₁ =ΔV and ΔV ₂ =0.) This adder ΔV can be determined by selecting the resistance value of the circuit.

The maximum/minimum value hold circuit 3 functions as a maximum value hold circuit when the control input is "H", and functions as a maximum value hold circuit when the control input is "L", and a specific example thereof is shown in FIG. . In FIG. 4, a clock oscillator 31 is a square wave oscillator with a very high frequency compared to the frequency of the signal input, and is connected to one input of an AND gate 32. The output of the exclusive OR 33 is connected to the other input of the AND gate 32, the output of the comparator 37 is connected to one of the inputs of the exclusive OR 33, and the control input is connected to the other input of the inverter 34. Connected via. The control input is connected to the U/ terminal of the up-down counter 35, and when the control input is "H", the up-down counter 35 functions as an up counter, and when it is "L", it functions as a down counter, and the voltage is applied to the CL terminal. Count the clock pulses. The count value of the up-down counter is converted into an analog voltage by a digital-to-analog converter 36 and compared with the input voltage by a comparator 37. Control input is “H”
(or "L"), the counter 35 operates as an up counter (or down counter), and the input voltage from the non-inverting input of the comparator 37, that is, the input voltage from the input terminal 30, is the input voltage from the inverting input of the comparator 37, that is, the digital analog signal. When the output voltage of the converter 36 is higher (or lower) than the output voltage of the converter 36, the output of the comparator 37 becomes "H" (or "L"), and at this time, the output of the exclusive OR 33 becomes "H" and the clock signal is output. The clock signal of the counter 31 is sent to the counter 3 via the AND gate 32.
Applied to the CL terminal of 5. Therefore, counter 35
counts up (or down) and the analog output voltage of the digital-to-analog converter goes up (or down) and reaches the input voltage from the input terminal 30 (strictly speaking, it becomes slightly larger or smaller than the input voltage). The output of the comparator 37 is inverted and becomes “L” (or “H”), and the AND gate 32
is closed, and the counting operation of the counter 35 is stopped. In this way, the voltage at the inverting input of the comparator 37, that is, the output terminal 39 of the maximum value/minimum value hold circuit 3 changes in accordance with the voltage at the input terminal 30, and when the control input 38 is at the "H" level, The maximum value is held at the "L" level, and the minimum value is held at the "L" level.

Next, using Figure 6, ΔV ₁ =ΔV, ΔV ₂ =0
The operation of the circuit shown in FIG. 5 will be described with respect to an embodiment in which: A in Figure 6 is an enlarged view of the signal input, and this signal input voltage is the signal input terminal in Figure 5.
IN, the input terminal 10 of the first analog adder 1 and the input terminal 2 of the second analog adder 2
Applied to 0. When the input signal is rising and the output of comparator 4 (that is, the voltage at output terminal OUT) is "H", control inputs 18 and 28 of adders 1 and 2 become "H" and "L", respectively. Therefore, a voltage A+ΔV higher than the signal input A by ΔV is generated at the output terminal 19, and a voltage the same as that of the signal input A is generated at the output terminal 29. At this time, the counter 3 is operating as an up counter, and the voltage at the output terminal 39 is equal to A. This state continues until the minimum point (maximum point) _P2 is reached, and the output of comparator 4 becomes “H”.
As it is, output B is at "H" level. When the signal input A starts to fall after passing the _P2 point, the voltage at the output 19 of the adder 1 becomes V+, where the signal input is expressed as V.
The voltage at the output terminal 39 of the hold circuit 3 is held at the voltage at the _P2 point, so the voltage at the output ₁₉ changes as shown by curve C in Figure 6 with ΔV.
At the time _t2 when the voltage drops to the point, the output of the comparator 4 is inverted and changes to the "L" level. and adders 1 and 2,
The control input of hold circuit 3 is reversed.
Therefore, the output terminal 19 of the adder 1 outputs the same voltage V as the signal input, the output terminal 29 of the adder 2 outputs the voltage V+ΔV which is the sum of ΔV added to the signal input, and the hold circuit 3 counts down and outputs the voltage V+ΔV. is output, and when the point _P'3 is reached, the minimum value V+ΔV at that time is held. When the signal input passes the _P3 point and starts rising and reaches the _t3 point, the output of the adder 1 becomes larger than the output of the hold circuit 3, the comparator 4 is inverted, and the output OUT becomes "H". level.

Figure 6 shows that for a constant positive voltage ΔV, ΔV ₁ =
This is an example in which ΔV, ΔV ₂ = 0, but if ΔV ₁ −ΔV ₂ = ΔV is satisfied for a constant positive voltage ΔV, then
A similar output pulse can be obtained for signal A even if one or both of ΔV ₁ and ΔV ₂ are negative (if negative, it is actually a subtraction rather than an addition). FIG. 7 shows the signal relationship when both ΔV ₁ and ΔV ₂ are negative.
Furthermore, this circuit ignores fluctuations below ΔV (V), so if the value of ΔV is taken appropriately, it does not malfunction due to noise carried in the signal.

According to this invention, it is possible to invert the output level by detecting a slight drop or rise in the signal input from the maximum point (local maximum point) and minimum point (minimum point), so that fluctuation DC components are not mixed in. It is possible to reliably detect the original pulse signal from the current signal, and the frequency range is not limited, and it is possible to realize a detection circuit that responds from almost 0 Hz.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of the signal input waveform and output signal waveform of the detection circuit of this invention, Fig. 2 is a diagram for explaining the outline of the operation of the circuit of this invention, and Fig. 3 is a diagram of an analog adder. As an example, FIG. 4 is an example of a maximum value/minimum value hold circuit, FIG. 5 is a diagram showing the configuration of the detection circuit of this invention, FIG. 6 is an operation explanation diagram, and FIG. 7 is an operation explanation diagram of another embodiment. It is. 1, 2...Analog adder, 3...Maximum value/minimum value hold circuit, 4...Comparator, 5...Inverter, IN...Input terminal, OUT...Output terminal.

Claims (1)

[Scope of utility model registration request] When the control input is "H", a constant voltage ΔV ₁ is added to the signal input and output, and when the control input is "L", a constant voltage that satisfies ΔV ₁ - ΔV ₂ = ΔV for the positive voltage ΔV is added to the signal input. Adders 1 and 2 that add and output voltage ΔV ₂ function as a maximum value hold circuit when the control input is “H”,
It consists of a maximum/minimum value hold circuit 3 that functions as a minimum value hold circuit when the control input is "L", a comparator 4, and an inverter 5, and the signal input is connected to the input terminal 10 of the adder 1 and the input terminal of the adder 2. 20, the output end 19 of the adder 1 is connected to the non-inverting input of the comparator 4, the output end 29 of the adder 2 is connected to the input end 30 of the maximum value minimum value hold circuit 3,
The output end 39 of the maximum value minimum value hold circuit 3 is connected to the inverting input of the comparator 4, and the output end of the comparator 4 is connected to the input end 18 of the adder 1 and the maximum value minimum value hold circuit.
and 38 directly and connected to the control input terminal 28 of the adder 2 via the inverter 5,
A pulse signal detection circuit that extracts a detection signal from the output of a comparator 4.