JPH0760596B2 - Dynamic memory device - Google Patents

Description

The present invention relates to a dynamic memory device in which an address accessed by a memory is determined by two signals called RAS (overbar) and CAS (overbar), and more particularly, The present invention relates to control of activation / deactivation of an activation signal of an internal column system at the time of refreshing.

[Prior Art] Conventionally, in this type of dynamic memory, row and column addresses are responded to in response to a row address strobe {abbreviated as RAS (overbar) hereinafter} and a column address strobe {abbreviated as CAS (overbar) hereinafter}. To access the memory. Further, in recent years, regarding the refresh control, an address counter is provided inside the memory, and as shown in FIG. 4, when CAS (overbar) is 0 and RAS (overbar) is activated, the address counter is output. It has been used as an address and has an operation to execute refresh (hereinafter abbreviated as CBR refresh). Naturally, the address counter is incremented by "1" every 1 CBR refresh cycle so that the refresh address changes.

To test that such an internal counter works properly, first start CBR refresh as shown in Fig. 5, then set CAS (overbar) to "1" level, and then set CAS (overbar) again. When the level is set to "0", the column address can be fetched, and the data at the address determined by the row given by the address counter and the fetched column address can be read, and the read-modify-write operation can be performed to read the read data to the address. And write the data of the opposite level and test that the address counter is operating normally.

However, recently, a function called first page or static column has been introduced.
As shown in FIG. 6, when the row address is fetched by RAS (overbar), the column activation signal φCA is generated after a predetermined time from RAS (overbar) to fetch the column address. If the address changes, the selection is changed to the changed address, and the CAS
When the (overbar) becomes “0”, external output and external write become possible. By doing so, the skew between the column address and CAS (overbar) signal can be absorbed, and the system performance is improved. Even such a memory naturally has a CBR refresh and naturally requires an address counter test,
It is controlled by the circuit shown in FIG.
The operation is such that the RAS timing generator 1 (abbreviated as TG below) that inputs RAS (overbar) generates various internal signals, but first the inverter three that inputs CAS (overbar) for the judgment of CBR refresh. Step I
Signal φ generated from TG and CAS signal obtained from V1, IV2, IV3
Two NAND circuits NA1 and NA in which 1 is flip-flop coupled
Input to 2 and judge the CBR cycle. If CAS (overbar) is "0", the output of NAND NA1 is at "1" level, and if CAS (overbar) is "1", it is at "0" level. Then, the signal φ2 is output from the TG and the output of the NAND NA1 and the AND A of the signal φ2.
By taking 1, the CBR signal CBR 10 is determined.

On the other hand, as shown in FIG. 8, the column activation start signal φ is output from TG.
The column activation signal φCA is obtained by taking AND A2 of the signal obtained by connecting the ST and CBR signals by the inverter IV1. If CBR
If the signal is "1", the column activation signal φCA is not generated. However, when the CAS (overbar) changes from "0" level to "1" level, the CBR signal becomes "0" and the column activation signal is generated. However, when CAS (overbar) becomes "0" again, the counter shown in FIG. 5 can be tested without generating the CBR signal by the flip-flop.

[Problems to be Solved by the Invention] The conventional CBR refresh determination circuit described above is a counter for a memory such as a first page static column in which a column type access path operates statically and its start cannot be controlled by a CAS type. For testing, if the CAS (overbar) goes to "1" level, there is a drawback that the column-related operation is performed even though it is a refresh cycle and power consumption is increased.

On the other hand, in order to prevent this, a circuit example as shown in FIG. 9 can be shown in the conventional example. This is CB when compared with FIG.
It is judged as CBR by the R judgment circuit and it is judged as CBR by inserting the final stage of the ingress three-stage inverter of the CAS (overbar) system into the opposite phase of the judgment signal of CBR and NAND NA3 and F / F. After that, even if CAS changes thereafter, CBR does not change and the column access does not start.

However, such circuits have the disadvantage that the counter cannot be tested.

[Means for Solving Problems] The dynamic memory of the present invention is configured so that the CAS (overbar) and the write control signal (hereinafter abbreviated as WE (abbreviation)) when the RAS (overbar) level changes. It has a circuit to judge the status, and CBR refresh when CAS (overbar) is "0" and WE (overbar) is "0" (hereinafter W
RCBR is distinguished by distinguishing between CBR refresh (abbreviated as CBR refresh) and CBR refresh (hereinafter abbreviated as RCBR refresh) when CAS (overbar) is "0" and WE (overbar) is "1".
It has a signal control that does not generate the column activation signal φCA only at the time of refreshing.

In a memory device, WE (overbar) is normally set to "0" level only during writing, so WE is used during CBR refresh.
(Overbar) is used because it often becomes "1" level.

EXAMPLES Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. Nando NA1
It is detected that the level of CAS (overbar) is “0” from φ1 and φ2 which change from “0” to “1” generated by T.G1 of RAS in the F / F consisting of Nand NA2, and Hold and detect 1/0 of WE (overbar) by the signal φ3 to the two inverters INV7,8 and hold. Then, by taking the held CBR signal and the WE (overbar) held signal NAND NA7, a signal that becomes "1" at WCBR and its opposite phase signal are obtained, and the opposite phase of WCBR and the signal of CBR are obtained. Nando NA6
The column activation signal is obtained by taking the AND signal A2 between the signal and the column activation start φST. The CAS (overbar) detection and holding circuit is the same as in FIG. 9 of the conventional example, and the WE (overbar) detection and holding circuit is a signal φ that changes from TG to 0-1.
The NAND NA4 of 3 and WE (overbar) is taken and amplified by the inverter IV6 to detect WE (overbar). N by the signal φ3 and its inverted signal by the inverter IV5
Channel transistor Q1 and P-channel transistor
Both Q1s are turned on to determine a flip-flop composed of two inverters IV7 and IV8. Signal φ3 is again
By changing to 0V, the state of WE (overbar) when RAS (overbar) changes from "1" to "0" is held. Then, the NAND of the inverted signal of the above-mentioned held CBR is taken by the inverter IV7 and inverted by the inverter IV9 to obtain the signals WCBR and WCBR (overbar) indicating whether or not the WCBR is refreshed. Then, by taking the NAND NA6 of the CBR signal and the WCBR (overbar), a signal that becomes "0" only in the RCBR cycle is obtained and this and the column activation start signal φST
The column activation signal φCA is generated by taking AND A2 of and.
By doing this, the column activation signal φ
The CA is not generated, and the column activation signal φCA is generated in the other RAS / CAS cycle WCBR refresh cycle.

In recent years, with the increase in capacity of memories, the function of a test mode has been incorporated in the memories.
This is because in test mode, the memory is accessed in parallel with 4 bits or 8 bits, and if the same data can be written and the same data can be read, if one path is different, the file judgment is made to correspond to 1/0 of the output and the test time 1/4 or
It is intended to be 1/8. In such a memory, the F / F for determining the test mode is set, and the value is determined by the CBR refresh, the test mode is set for the WCBR refresh, and the test mode is reset for the RCBR refresh. If the test mode is set, the parallel test described above is performed, and if it is reset, the normal function is performed.

In such a first embodiment, the counter cannot be tested. The second embodiment of the present invention solves this problem. FIG. 2 is a circuit diagram of the second embodiment of the present invention. First
Latch circuit that holds the test mode compared to the embodiment
WCBR to D1 becomes 1 in WCBR cycle and its inverted signal WCBR
When CBR refresh is performed with (overbar) as data input, AND signal A4 is set to the signal that is "1" and the test mode latch signal φ4 generated from TG, and CBR refresh is input as the clock of the latch circuit D1. To W
The CBR cycle and RCBR cycle are distinguished and the test mode is set and reset. However, in the WCBR cycle, because the test mode is suspended, the WCBR cycle judgment signal reverse phase WCBR
(Overbar) and AND 3 of the latch output are taken, and the test mode signal TEST is generated, so that the column activation signal φCA is released from the test mode in the WCBR cycle and has a normal function as in the first embodiment. Once generated, the counter can be tested. Especially for the memory that sets the test mode in WCBR, be sure to use WE
(Overbar) is guaranteed to be at "1" level.

As described above, according to the present invention, the column activation signal φCA is generated in the WCBR refresh cycle by detecting and holding the levels of CAS (overbar) and WE (overbar) in the CBR refresh cycle, and RCBR is generated. Since the same signal is not generated in the refresh cycle, the power of CBR refresh in which the normal WE (overbar) is at "1" level can be reduced, and the counter test equivalent to the conventional one can be performed with the input waveform shown in Fig. 3. There is an effect that can be done. This effect is particularly effective in a memory having a test mode (parallel measurement mode).

In memory that is released even in ROR refresh in test mode, if the latch circuit is set by RAS reset, the WCBR after ROR refresh is ROR refresh and WCB because the test mode is reset.
A counter test can be performed by repeating the R refresh test cycle, and it is not necessary to take the logic of the output of the latch signal and WCBR.

[Brief description of drawings]

1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment, FIG. 3 is an input waveform diagram of a counter test,
FIG. 4 is an input waveform diagram of CBR refresh, FIG. 5 is an input waveform diagram of a conventional counter test, FIG. 6 is a waveform diagram showing a generation order of column activation signals, FIGS. 7 and 9 are conventional waveforms. FIG. 8 is a circuit diagram showing a circuit example, and FIG. 8 is a waveform diagram showing generation of a column activation signal during conventional CBR refresh. 1 …… RASTG, NA1, NA2, NA3, NA4, NA5, NA6, NA7 …… Nand gate, IV1, IV2, IV3, IV4, IV5, IV6, IV7, IV8, IV9 …… Inverter, A1, A2, A3 …… AND gate, D1 …… Latch circuit, Q1, Q2 …… Transistor.

Claims (1)

[Claims] 1. When a row address strobe, a column address strobe, and a write control signal are supplied and the column address strobe is in a 0 level state and the row address strobe is in a 0 state, the row address is read, and then the row address strobe is responded to. Is a memory capable of generating a column address activation signal to take in a column address and changing the column selection according to a change in the column address. When the column address strobe is in the 0 level state and the row address strobe is in the 0 state, the internal address is changed. In a dynamic memory device that selects a row address according to the address of a counter, when the write control signal is at the 1 level, the column address strobe is at the 0 level, and the row address strobe is in the 0 state, the column address activation signal is deactivated and the write operation is performed. If the control signal is 0 level, the column address Bed dynamic memory device characterized by having means for the row address strobe is generated the column address activation signal becomes zero state at the zero level.