JPH0760430B2 - Parallel data processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention is an SI system in which a plurality of basic arithmetic elements of the same type (hereinafter referred to as PE) perform the same operation under the control of one control unit.
The present invention relates to a processing method for executing a floating point operation in an MD (Single-Instruction-Multi-Dsta stream) type parallel data processing device.

[Prior Art] This kind of parallel data processing device has an arithmetic unit 14 controlled by one control unit 13 as shown in FIG. 11, and the arithmetic unit 14 is composed of a plurality of PEs 1 of the same type. Has been done. All PE1s perform the same operation under the control of the control unit 13. The connection method for data transfer between the PEs 1 is not particularly limited here.

Figure 12 is from the literature, KE Batcher “Design of a Massively
Parallel Processor ", IEEE Transactions on Comput
FIG. 8 is a block diagram showing the internal configuration of one PE of the conventional parallel data processing device shown in ers, Vol. C-29, No. 9, Sep. 1980, pp. 836-840. In the figure, 15 to 20 are 1-bit registers for holding data, 15 is an A register, and 16 is a register.
Is a B register, 17 is a C register, 18 is a P register, 19 is a G register, and 20 is an S register. Reference numeral 21 is a shift register having an arbitrary bit length, 22 is a 1-bit full adder, 23 is a data bus, and 24 is a memory.

Next, the operation will be described. A register 15, P register 18
And the values of the C register 17 are added by the 1-bit full adder 22, and the sum of the results is stored in the B register 16 and the carry is stored in the C register 17. In some cases, the value of the B register 16 is shifted by the shift register 21 and stored in the A register 15. As shown in FIG. 11, generally, the PE1s are connected in a two-dimensional grid pattern,
Data transfer between these PE1s is performed by the P register 18. The G register 19 is inspected for a value match or a value mismatch with the P register 18, and the result is sent to the data bus 23. Data is exchanged with the memory 24 using the data bus 23. Input / output of data to / from the outside is performed through the S register 20 of each PE1.

Since control of each PE1 is performed by the control signal given from one control unit 13, all PE1 perform the same operation. Each P
To perform different processing for E1 units (the data shift for digit alignment in floating point addition and subtraction and the data shift for normalization differ depending on the data value),
The shift amount of each PE1 unit is changed using the shift register 21.

[Problems to be Solved by the Invention] Since the conventional parallel data processing device is configured as described above, when the operation is changed by data such as digit alignment and normalization of floating point addition / subtraction, There was no other method than using the shift register 21, and the processing took a very long time.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a parallel data processing system capable of processing floating point arithmetic in each PE at high speed.

[Means for Solving the Problems] A parallel data processing method according to the present invention is such that an addressable register file is provided in each PE, and an address register for determining an address to the register file for each PE. A 2-bit flag register for indicating the state in each PE, a function of returning the content of the address register by +1 or -1 and returning it to the address register again, and whether or not the value of the address register is "0". Determination circuit that has the function of inverting the 1-bit value of the flag register when it is '0' and the value of the address register based on each value of the flag register and read from the register file. Data is output as it is, each bit is inverted and then output, or all bits are "0".
Equipped with a selector for selecting whether to output the value of all bits or the value of all bits '1', and an arithmetic circuit for inputting the data read from the register file by the address input from the outside and the data via the selector. , If the exponent value of the operand is different in floating point addition / subtraction in each PE, the value based on the difference is stored in the above address register, and the value of the mantissa part of the operand with the small exponent value is set to the exponent value. By reading from the register file in accordance with a large operand, the digit matching processing of the address read from the above register file is executed according to the data in each PE, and in the floating-point operation, the digit of "0" is placed above the mantissa part of the operand. If there is, the value based on that number is stored in the above address register, and the mantissa part "0" is stored.
By reading from the register file from the highest digit that is not, normalization processing of different addresses read from the register file is executed according to the data in each PE.

[Operation] In the parallel data processing method according to the present invention, by using each of the above means in each PE, in floating-point addition / subtraction, the value of the mantissa part of the operand with a small exponent value is changed to the operand with a large exponent value. The digit alignment processing in each PE can be executed at a high speed by extracting it according to the above, and in floating-point arithmetic, the most significant digit '0' in the mantissa part is removed and the most significant digit other than '0' is removed. By extracting from the digit, the normalization processing in each PE is executed at high speed.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. The overall structure is the same as that shown in FIG.

FIG. 1 is a block diagram showing the internal configuration of each PE 1 in the embodiment. In the figure, 2 is an addressable register file, for example, 4 as shown in FIG.
It consists of bits x 32 words (however, the address is shown in hexadecimal notation in Fig. 2). This register file 2
Can read and write a value corresponding to an address given from the outside. Further, in reading, a value corresponding to each of two addresses given at the same time can be read at the same time, and also for writing, the value can be written simultaneously to the given address at the same time. Is. In FIG. 1, the write address is the ARA supplied from the outside.
Thus, the reading is also performed by the ARB and the ARC or the value of the address register 6 described later selected by the selector 7. Reference numerals 3 and 4 denote an RB register and an RC register respectively storing two values read out simultaneously from the register file 2, and an RA register 5 stores a value to be written in the register file 2. When the register file 2 has the configuration shown in FIG. 2, the RA register 5 and the RB register described above are used.
3, RC registers 4 are all 4-bit width registers. 6
Is an address register used when the address of the value read from the register file 2 to the RC register 4 is determined for each PE unit, and is a 5-bit register when the register file 2 shown in FIG. 2 is used. 7 is an external address that determines the value to be read to RC register 4.
Selector to select from the value of ARC and address register 6,
8 is a function of returning the content of the address register 6 by +1 or -1 to the address register 6 again, and judging the value of the address register 6, and if the value is "0", the flag F1 of the flag register 9 described later is set. A determination circuit having a function of setting to "1", 9 is a 2-bit flag register having a flag F1 and a flag F2 for giving a control signal of a selector 10 described later, and 10 is for determining one data input of an ALU 12 described later There are four possible values of the RC register 4, a value obtained by inverting each bit of the RC register 4 via the NOT gate 11, and all '0' and all '1'. The control of the selector 10 is performed by the flags F1 and F2 of the flag register 9 based on the truth table shown in FIG. Reference numeral 12 is an ALU (arithmetic logical operation circuit), which executes addition, subtraction, logical operation, etc. on the input data. When the register file 2 shown in FIG. 2 is used, it is a 4-bit ALU.

The operation of each PE 1 of the parallel data processing device configured as described above will be described in detail below.

First, FIG. 4 shows the format of the floating point number used in this embodiment. The whole is 32 bits wide, and the sign of the mantissa part (S; 1 bit), the exponent part (E; 7 bits), and the mantissa part (M; 24 bits) are arranged in order from the highest order. The exponent part is given a weight of 64 to the actual value, the mantissa part is expressed as an absolute value, and the radix is
16 As a result, the value N of the floating point number shown in FIG. 4 becomes N = M × 16 ^(E-64) .

In the present invention, since digit alignment processing and normalization processing in floating point addition / subtraction with different shift amounts for each data are performed at high speed by a SIMD type parallel data processing device,
The digit alignment process and the normalization process will be separately described below.

(1) Digit alignment processing When adding or subtracting two floating point numbers, it is necessary to align the mantissa so that the exponents have the same value (see FIG. 5). In order to perform this digit alignment, one mantissa part must be shifted according to the difference between the exponent parts of the two numbers to perform the operation. The conventional SIMD type parallel data processing device cannot perform this processing or must use the shift register 21 to shift each data.

In the present invention, it is as follows. Now, as shown in FIG. 6 (b), the mantissa part of two numbers to be added (subtracted) is X0.
~ X5, Y0 to Y5 (4 bits each of Xi and Yi). Of the mantissa part, the value with the smaller exponent part (the value to be shifted) is stored in order from address '0' to '5' of the register file 2 as shown in FIG. The other mantissa is stored in another area of the register file 2 (here, the addresses are "1A" to "1F"). Further, the difference between the exponents of the two is set to 2. Then, from the point that the radix is 16, the addition of these two mantissas is performed by adding 8-bit '0' to the upper part of the numbers Y0 to Y5 and adding 8 bits to the right, as shown in FIG. 6 (b). It will be shifted and added. Addition should start from the digit X5 + Y3 and go to the highest place.

Since the numbers that do not need to be shifted (values represented by X0 to X5 in this case) may be added in order from the lower order, the register file 2 to the RB register 3 can be changed by the address ARB from the outside shown in FIG. Every 4 bits are read in order from the lower order and sent to the ALU12. The number to shift (Y in this case)
For 0 to Y5), first calculate the address of the digit to start addition from the difference between the exponents of the two numbers, store this in the address register 6, and then use this value to read from the register file 2
Read to RC register 4. In the example of FIG. 6, the value initially stored in the address register 6 is '3' which is the address corresponding to Y3. After that, the value of the address register 6 is decremented by 1 by the judgment circuit 8, and the value is decreased by RC.
It is used as the address of the value read to the register 4.

FIG. 7 shows a time chart of this processing. The flags F1 and F2 of the flag register 9 are initially set to "0" as shown in FIG.
It is set to select the value of the register 4. As described above, at t = 1, the address read to the RB register 3, that is, ARB is '1F', the address read to the RC register 4, that is, the value of the address register 6 is '3', and as a result, both registers 3 , 4 read X5 and Y3, respectively, and at t = 2, X5 + Y3 is executed by the ALU12. In the following order, X4 + Y2 is performed at t = 3, and X3 + Y1 is performed at t = 4. By the way, at this t = 4, the value of the address register 6 becomes "0". As a result, the determination circuit 8 detects this, and the value of the flag F1 of the flag register 9 changes from "0" to "1". That is, the selector 10 has been the RC register 4 until now.
What was sent to ALU12 by selecting the value of is to select the value of all bits '0'. As a result, the value of the address register 6 is further decremented by 1 from "0", resulting in "1F",
Even if the value indicated by the address of "1E", ... Is read to the RC register 4, the value of all bits "0" is sent to the ALU12. Therefore, the addition in ALU12 is X2 when t = 5.
After + Y0 is performed, X1 + '0' at t = 6, X0 + '0' at t = 7
Therefore, the addition of the number of "0" is added to the high order of Y0 to Y5 shown in FIG.

In the case of subtraction, in order for the selector 10 to send the value (1's complement) obtained by inverting the value of the RC register 4 to the ALU 12,
From FIG. 3, since the flags F1 and F2 of the flag register 9 are set to "0" and "1", respectively, the address register 6
Is changed to "0" and the flag F1 is changed from "0" to "1", all the bits "1" are selected in the selector 10, and the subtraction shown in FIG. 5 (b) is executed. .

(2) Normalization processing Normalization processing for floating-point numbers with a radix of 16 means removing the upper 4-bit unit "0" of the mantissa part as shown in FIG. It means to add 0 '(In this case, it is necessary to update the exponent part by the shift amount).

This normalization process is also a weak point of the SIMD type parallel data processing device because the shift amount changes depending on the data.

In the present invention, it is as follows. Now, it is assumed that the mantissa part of the floating point number to be normalized is represented by Z0 to Z4 below with the upper 4 bits being "0" as shown in FIG. 9 (b).
First, the target mantissa part is stored at addresses '1A' to '1F' of the register file 2 as shown in FIG. The address register 6 searches for "0" in 4-bit units, which is stored in advance in "1A" to "1F", in the upper part of the mantissa part, and finds the highest address (4th bit) where all 4 bits are not "0". In FIG. 9A, "1B") is stored. After that, the value of the register file 2 is read into the RC register 4 by the address indicated by the address register 6, and the ALU12 and RA register 5 are read.
It is sent to the area for storing the result of the register file 2 via. The value of the address register 6 is sequentially incremented by 1 by the decision circuit 8, and the ALU12 input on the RB register 3 side is set to "0".

A time chart of this process is shown in FIG. The flags F1 and F2 of the flag register 9 are initially set to "0" as shown in FIG.
Is set to select the value of. At t = 1, the value of the address register 6 is “1B”, Z0 is read from the register file 2 into the RC register 4, and is output from the ALU 12 at t = 2. Below, at t = 3,4,5,6, Z
1, Z2, Z3, Z4 are output. Further, at t = 6, the value of the address register 6 becomes "0". Therefore, the flag F1 of the flag register 9 changes from "0" to "1" as in the case of the digit alignment process, and thereafter, all bits of the ALU 12 are input to "0". Therefore, the output of the ALU12 also becomes "0", and as shown in FIG. 9 (b), the necessary number of "0" in 4-bit units is added to the lower order of Z0 to Z4.

With the method described above, digit alignment processing and normalization processing are SIMD.
Type parallel data processing device can be executed efficiently and at high speed.

In the above embodiment, the digit matching process and the normalizing process are performed according to the floating point number format shown in FIG. 4, but the present invention is not necessarily limited to this. The bit width of each field in the floating point number may be changed arbitrarily. Although the case where the radix is 16 is dealt with, a case where the radix is 2 can be sufficiently dealt with. However, 2
When the radix of is used, it is necessary to change the register file 2, ALU12, etc. so as to handle 1-bit width data.

[Effects of the Invention] As described above, according to the present invention, in each PE, an addressable register file, an address register for determining an address to this register file for each PE, and in each PE 2 bit flag register for indicating the state of the above and the contents of the above address register are +1 or -1.
And a function of returning to the address register again and a function of judging whether the value of the address register is "0" and inverting the 1-bit value of the flag register when the value is "0". And, based on each value of the above flag register, the data read from the register file is output as it is according to the value of the above address register, each bit is inverted and then output, or the value of all bits '0'. A selector for selecting whether to output the value of all bits '1' or an arithmetic circuit for inputting the date read from the register file by the address input from the outside and the data via the selector. When the exponent value of the operand is different in floating point addition / subtraction in PE, the value based on the difference is stored in the above address register, and the value of the exponent value is small. By reading the mantissa value of the command according to the operand with a large exponent value from the register file, the digit alignment processing for different addresses read from the register file is executed according to the data in each PE. If there is a digit of "0" in the upper part of the mantissa part of, the value based on that number is stored in the above address register and
By reading from the register file from the highest digit that is not, the normalization processing of the address read from the above register file is performed differently depending on the data in each PE, so that floating point can be used in each PE in the SIMD parallel data processing device. There is an effect that the digit matching process and the normalizing process of the operation can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an internal configuration of each PE in a SIMD type parallel data processing device according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a configuration of a register file in each PE, and FIG. FIG. 4 is a diagram showing a truth table of operation states of selectors controlled by respective flags of the flag register and respective values thereof in the embodiment. FIG. 4 is a diagram showing a format of floating point numbers used in the embodiment. FIGS. 6 (a) and 6 (b) are diagrams showing digit alignment processing in floating point addition / subtraction, and FIG. 6 (a) and FIG.
FIG. 9B is a diagram showing the position of data in the register file and the processing at the time of addition when digit alignment processing is performed in the embodiment;
FIG. 7 is a time chart showing the operation of the digit matching process,
FIG. 8 is a diagram showing the normalization process of floating point numbers, and FIGS. 9A and 9B are diagrams showing the position of data in the register file and the process when the normalization process is performed in the embodiment. FIG. 10 is a time chart showing the operation of the above normalization processing, FIG. 11 is an overall configuration diagram of a SIMD type parallel data processing device, and FIG. 12 is an internal configuration of each PE in the conventional SIMD type parallel data processing device. It is a block diagram showing. 1 is PE (basic arithmetic element), 2 is register file, 3 is
RB register, 4 RC register, 5 RA register, 6 address register, 7 address selector, 8
Is a decision circuit, 9 is a flag register, 10 is an ALU input switching selector, 11 is a not gate, 12 is an ALU (arithmetic logic operation circuit), 13 is a control unit, and 14 is an operation unit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A parallel data processing device having a plurality of basic arithmetic elements of the same type controlled by the same instruction from the outside, wherein an addressable register file is provided in each basic arithmetic element, and An address register for determining an address for each basic operation element, a 2-bit flag register for indicating the state in each basic operation element, and the contents of the address register are incremented by +1 or -1 and returned to the address register again. A determination circuit having a function and a function of determining whether or not the value of the address register is "0" and inverting the 1-bit value of the flag register when the value is "0"; Based on the value
Whether the data read from the register file is output as it is according to the value of the above address register, each bit is inverted and then output, or the value of all bits "0" or the value of bit "1" is output. And an arithmetic circuit for inputting the data read from the register file by the address input from the outside and the data via the selector, and the exponent part of the operand in the floating point addition / subtraction in each basic arithmetic element. When the values of the two differ, the value based on the difference is stored in the address register, and the mantissa value of the operand with a small exponent value is read from the register file according to the operand with a large exponent value. Digit matching processing for different addresses read from the above register file depending on the data in each basic operation element When executing, and when there is a digit of "0" in the upper part of the mantissa part of the operand in floating-point arithmetic, store the value based on that number in the above address register. By reading from the register file,
A parallel data processing method characterized in that normalization processing of different addresses read from the register file is executed by data in each basic operation element.