JPH0329068A - Parallel data processing system - Google Patents

Abstract

PURPOSE:To perform the digit matching and normalizing processes of a floating point arithmetic at a high speed by carrying out the normalizing processes of different addresses read out of a register file based on the data on each PE (basic arithmetic element). CONSTITUTION:A register file 2 is prepared together with an RB register 3, an RC register 4, an RA register 5, an address register 6, an address switching selector 7, a deciding circuit 8, a flag register 9, an arithmetic logic unit ALU input switching selector 10, a NOT gate 11, and an ALU 12. Then these means 2 - 12 are used in each PE 1. Thus the value of the mantissa part of an operand having the small value of the exponent part is taken out in accordance with an operand having the large value of the exponent part in the addition/ substraction of floating points. In a floating point arithmetic state, the digit '0' of the highest rank of the mantissa part is excluded and the highest rank digit except '0' is taken out. As a result, the digit matching and normalizing processes are carried out at a high speed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is an S I system in which a plurality of basic computing elements of the same type (hereinafter referred to as PEs) perform the same operation under the control of one control unit. M D (Single-Instruction)
This paper relates to a processing method for executing floating point operations in an on-Multi-Data stream type parallel data processing device. [Prior Art] This type of parallel data processing device has a calculation unit 14 controlled by one control unit 13, as shown in FIG.
This calculation unit 14 is composed of a plurality of PEIs of the same type. All PEIs perform the same operation under the control of the control unit 13. Note that the connection method for data transfer between each PEI is not particularly limited here. Figure 12 is from the literature, κ. E. Batcher “De
sign ofa Massively Parallel
elProcessor', IEEETr
ansactions on Computers, V
ol. C-29, No. 9, Sep. 1980, pp.
836-840 is a block diagram showing the internal configuration of one PE of the conventional parallel data processing device shown in FIG. In the figure, ■5 to 20 are 1-bit registers that each hold data, 15 is the A register, 16 is the B register, 1
7 is a C register, 18 is a P register, 19 is a G register, and 20 is an S register. 21 is a shift register of arbitrary bit length, 22 is an l-bit full adder, 23 is a data bus, and 24 is a memory. Next, we will explain the operation. The values of the A register 15, P register 18 and C register 17 are stored in the 1-bit full adder 2.
2, and the resulting sum is stored in B register 16, and the carry is stored in C register 19.
In some cases, the value of the B register 16 is shifted by the shift register 21 and stored in the A register 15.

As shown in Figure 11, PEIs are generally connected in a two-dimensional grid, and data transfer between these PEIs is
This is done by register 18. The G register 19 is checked for match or mismatch with the P register 18, and the result is sent to the data bus 23. Data is exchanged with the memory 24 using the data bus 23. Also,
Data input/output to/from the outside is performed through the S register 20 of each PEI. Since each PEI is controlled by a control signal given from one control unit 13, all PEIs operate in the same way. To perform different processing for each PEI unit (data shift for digit alignment and data shift for normalization in floating point addition/subtraction, the shift amount differs depending on the data value), use the shift register 2l for each PEI unit. Change the shift amount in PEI units. [Problems to be Solved by the Invention] Since the conventional parallel data processing device is configured as described above, when changing its operation depending on data, such as digit alignment or normalization in floating point addition/subtraction, it is necessary to There was no other way but to use the shift register 21, and the process took a very long time. This invention was made to solve the above-mentioned problems, and aims to provide a parallel data processing method that can process floating point operations at high speed in each PE.

[Means for Solving the Problems] The parallel data processing method according to the present invention includes, in each PE, an addressable register file, an address register for determining the address to this register file for each PE, Determines whether the value of the 2-bit flag register to represent the state in each PE and the above address register is 'O', and if it is '0', inverts the value of the t bit of the above flag register. A determination circuit, based on each value of the flag register (2), outputs the data read from the register file as is, inverts each bit, or outputs all bits a. A selector that selects whether to output the value of Ot or the value of all bits '1', and an arithmetic circuit that manually inputs the data read from the register file according to the address input from the outside and the data via the above selector. When the values of the exponent parts of operands differ in floating point addition and subtraction in each PE, the value based on the difference is stored in the above address register, and the value of the mantissa part of the operand with the smaller value of the exponent part is stored in the exponent part. By reading from the register file according to the operand with the larger value,
The data in each PE performs different digit alignment processing for the address read from the register file, and in floating point arithmetic, t is added to the upper part of the mantissa of the operand.
If there is Hj of O y, store the value based on that number in the above address register, and read it from the register file starting from the most significant digit that is not '0'' of the mantissa. Normalization processing is performed for different read addresses. [Operation] The parallel data processing method of the present invention uses the above-mentioned means in each PE, so that in floating point addition and subtraction, the exponent part is By extracting the mantissa value of the operand with a small value according to the operand with a large exponent value, digit alignment processing within each PE can be executed at high speed. By removing a certain '0' digit and extracting from the most significant digit that is not 'O', normalization processing in each PE is executed at high speed.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. The overall configuration is the same as that shown in FIG. 11 above.

FIG. 1 is a block diagram showing the internal configuration of each PEI in the embodiment. In the figure, reference numeral 2 denotes an addressable register file, which has, for example, a 4-bit x 32 word configuration as shown in FIG. 2 (however, addresses are shown in hexadecimal notation in FIG. 2). This register file 2 can read and write values corresponding to addresses given from the outside. Furthermore, for reading, it is possible to read the values corresponding to two addresses given at the same time, and for writing, it is also possible to read and write to a given address at the same time. It is. 1st
In the figure, the W write address is performed by ARA given from the outside, and the read is performed by the same <ARB and ARC or the value of address register 6, which will be described later, selected by selector 7. 3.4 is R that stores two values read simultaneously from register file 2 above.
B register, RC register, and 5 are RA registers that store values to be written to register file 2. If the register file 2 has the structure shown in FIG.
A register 5, RB register 3, and RC register 4 are all 4-bit wide registers. 6 is register file 2
This is an address register used to determine the address of the value to be read from the RC register 4 to the RC register 4 for each PE, and becomes a 5-bit register when the register file 2 shown in FIG. 2 is used. 7 is a selector that selects the address that determines the value to be read into the RC register 4 from the external address ARC and the value of the address register 6; 8 is a function that adds 1 or -1 to the contents of the address register 6 and returns it to the address register 6; , a determination circuit having a function of determining the value of the address register 6 and, if the value is i 0 +, setting a flag F1 of a flag register 9 to be described later to 11'; 9 is for providing a control signal for a selector 10 described later; A 2-bit flag register having a flag F1 and a flag F2, 10 is a selector for determining one data input of the ALU 12, which will be described later.As a candidate, the value of the RC register 4 and each bit of the register are set to the not gate 11. The value inverted through , all bits are all I O + and all '
There are four ways of 1'. This selector 10 is controlled by the third
Based on the truth table shown in the figure, this is performed using flags F1 and F2 of the second flag register 9. 12 is ALU
(arithmetic and logic operation circuit), which performs addition, subtraction, logical operations, etc. on input data. When using register file 2 shown in Figure 2, 4 bits A L
It becomes U. The operation of each PEI of the parallel data processing device configured as above will be explained in detail below. First of all, FIG. 4 shows the format of floating point numbers used in this embodiment. The entire width is 32 bits, and starting from the most significant one,
The sign of the mantissa part (S; 1 bit), the exponent part (E; 7 bits), and the mantissa part (M; 24 bits). The exponent part is given a weight of 64 to the actual value, the mantissa part is expressed as an absolute value, and the base number is 16. As a result, the value N of the floating point number shown in FIG. Since the processing is performed at high speed using a SIMD type parallel data processing device, digit alignment processing and normalization processing will be explained separately below. When subtracting, it is necessary to align the mantissas so that the values of the exponent parts of each number are equal (see Figure 5). The operation must be performed by shifting the mantissa part of one number.
IMD type parallel data processing devices either cannot perform this processing or have had to shift each data using a shift register 21. In the present invention, the following steps are performed. Now, the mantissa parts of the two numbers to be added (subtracted) are as shown in Figure 6 (bl.
``Y5 (Xi and Yi are each 4-bit numbers).
Among these mantissa parts, the value whose exponent part is smaller (the value to be shifted) is stored in order from address '0' to '5' in register file 2, as shown in ta+ in the figure.
The other mantissa part is stored in another area of register file 2 (in this case, addresses 'IA' to 'IF' are used).Also, assume that the difference between the exponent parts of both is 2.Then, the base number is 16. From the point, the addition of these two mantissas is the sixth
As shown in the figure (bl), add 8 bits of 'O e to the upper part of the number YO-Y5, shift the whole thing to the right by 8 bits, and then add it.The addition starts from the X5+Y3 digit and goes up to the most significant digit. For numbers that do not need to be shifted (in this case, the values represented by XO to Read every 4 bits in register 3 sequentially from the lowest order and send it to ALtJ12.For the number to be shifted (YO-Y5 in this case), first calculate the address of the digit to start addition from the difference between the exponent parts of the two numbers. Keep it,
This is stored in the address register 6, and this value is read from the register file 2 to the RC register 4. In the example shown in FIG. 6, the value initially stored in address register 6 is '3', which is the address corresponding to Y3. Thereafter, the value of the address register 6 is decremented by 1 by the determination circuit 8, and the values are sequentially used as the address of the value to be read into the RC register 4. Figure 7 shows a time chart of this process. Note that the flags Fl and F2 of the flag register 9 are each initially set to t O + as shown in the figure, and the selector 10
Is the value of RC register 4 from Figure 3? is set to select. As mentioned above, at t=1, RB
The address read into register 3, that is, ARB is 'I
F'. The address read to the RC register 4, that is, the value of the address register 6, is 13', and as a result, X5 and Y3 are read to both registers 3 and 4, respectively, and t=
2, X5+Y3 is executed by ALU12. In the following order: X 4 + Y 2 at t=3, X3+ at t=4
Y1 will be held. By the way, at t=4, the value of address register 6 becomes I.sub.P. As a result, this is detected by the determination circuit 8, and the flag register is set. The value of flag Fl of star 9 changes from J O l to '1'. That is, the selector 10 has so far selected the value of the RC register 4 and sent it to the ALU 12, but all bits 'O j
The value of will be selected. As a result, the value of address register 6 is further subtracted by 1 from "0" and becomes 'IF'.
Even if the value indicated by the address of IE', . . . is read to the RC register 4, all bits t
The value of Op will be sent. For this reason, ALU1
For addition at 2, after X2+YO is performed at t=5, t=6
At t=7, it becomes x1+'0', and at t=7, it becomes xo+'o'.
Addition of the number YO-Y5 shown in Figure 6 with '0' added to the upper part is executed. In the case of subtraction, each flag Fl,
Since F2 is set to JQ# and JP, respectively. The value of address register 6 becomes '0' and flag F1 becomes '0'
→ '1', all bits 'J' are selected in the selector 10, and the subtraction shown in Figure 5 ('b) is executed. (2) Normalization process Floating point number with base 16 As shown in Figure 8, the normalization process involves removing the upper 4 bits of 'O' from the mantissa, shifting it to the left, and filling the lower bits with '0' (in this case, the shift amount (need to update the exponent part) This normalization process is also a weak point of SIMD type parallel data processing devices because the amount of shift varies depending on the data. In the present invention, it is done as follows. Now, the mantissa part of the floating point number to be normalized is divided into the top 4 as shown in Figure 9.
The bit is t O p and the following Z O − 7. 4. First, the mantissa part to be considered is shown in the same figure (a
Address 'IA' of register file 2 as shown in l
~ Store in 'IF'. The address register 6 contains the 4 characters above the mantissa stored in advance in 'IA' to 'IF'.
Search for bitwise ``0'', all 4 bits are ``O''
('IB' in Figure 9 ta+)
Store it. Thereafter, the value of the register file 2 is read into the RC register 4 using the address indicated by the address register 6, and sent to the area where the result of the register file 2 is stored via the ALU 12 and the RA register 5. In addition,
The value of the address register 6 is sequentially added by 1 by the judgment circuit 8, and the value of the ALU 12 on the RB register 3 side is '0'.
'. A time chart of this process is shown in Figure 1O. Note that the flags Fl and F2 of the flag register 9 are each initially set to t O y as shown in the figure, and the selector 10
is set to select the value of RC register 4. At t=1, the value of address register 6 is 'IB', ZO is read from register file 2 to RC register 4, and output from ALU 12 at t=2.
Below, at t=3.4 and 5.6, Zl, Z2, Z3,
Z4 is output. Furthermore, at t=6, the value of address register 6 becomes t O j . Therefore, the flag F1 of the flag register 9 changes from '0' to '1', as described in the section of the digit alignment process, and from this point on, the ALU1
The input of 2 becomes all bits '0'. Therefore, ALU1
The output of 2 is also ``Ol'', and as shown in Figure 9), Z
The required number of t O t in 4-bit units is added to the lower part of O to Z4. With the method described above, digit alignment processing and normalization processing can be performed using SI.
It can be executed efficiently and at high speed even in an MD type parallel data processing device.

In the above embodiment, a case has been described in which digit alignment and normalization processing are performed according to the floating point number format shown in FIG. 4, but the present invention is not necessarily limited to this. The bit width of each field in the floating point number may be changed arbitrarily. Also, although we have dealt with the case where the base number is 16, it is also possible to deal with the case where the base number is 2. however,
When using radix 2, register file 2, AL
It is necessary to change U12 etc. so that it can handle 1-bit width data. [Effects of the Invention] As described above, according to the present invention, each PE includes an addressable register file, an address register for determining the address to this register file for each PE, and an addressable register file in each PE. a 2-bit flag register for representing the state of the address register, and a determination circuit that determines whether the value of the address register is j O l and inverts the value of 1 bit of the flag register when it is '0''. , Based on each value of the flag register above, determine whether the data read from the register file by the value of the address register is output as is, each bit is inverted and output, or the value of all bits t O t. It is equipped with a selector that selects whether to output the value of all bits Ill, and an arithmetic circuit that inputs the data read from the register file according to the address input from the outside and the data via the above selector. When the exponent values of operands differ during decimal point addition and subtraction, the value based on the difference is stored in the above address register, and the mantissa value of the operand with the smaller exponent value is adjusted to match the value of the mantissa with the larger exponent value. By reading from the register file,
The data in each PE performs different digit alignment processing for the address read from the register file, and in floating point operations, the upper part of the mantissa of the operand is
' If there is a digit, store the value based on that number in the address register above, and read from the register file starting from the most significant digit that is not '0' in the mantissa, and read from the register file using the data in each PE. Since the normalization processing is performed for different addresses, each PE in the SIMD type parallel data processing device has the effect of speeding up the digit alignment processing and normalization processing of floating point operations.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the internal configuration of each PE in a SIMD type parallel data processing device according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of a register file in each PE, and FIG. Figure 4 shows a truth table of the operating states of the selector controlled by each flag of the flag register and its value in the example, Figure 4 shows the format of floating point numbers used in the example, and Figure 5 shows the format of the floating point number used in the example. Figure fa+, (bl is a diagram showing digit alignment processing in floating-point addition and subtraction, Figure 6 (
a) and ('b) are diagrams showing the position of data in the register file and the processing at the time of addition when performing digit alignment processing in the embodiment, FIG. 7 is a time chart showing the operation of the digit alignment processing, and FIG. Figure 8 shows the normalization process for floating point numbers.
9(a) and 9(b) are diagrams showing the position of data in the register file and its processing when normalization processing is performed in the embodiment, FIG. 10 is a time chart showing the operation of the normalization processing, and FIG. Fig. 11 is an overall configuration diagram of a SIMD type parallel data processing device, and Fig. 12 is a block diagram showing the internal structure of each PE in a conventional SIMD type parallel data processing device. 1 is a PE (basic calculation element). , 2 is the register file, 3
is the RB register, 4 is the RC register, 5 is the RA register, 6 is the address register, 7 is the address switching selector, 8 is the judgment circuit, 9 is the flag register, and 10 is the AL
Selector for U input switching, 11 is not gate, 12
is an ALU (arithmetic logic operation circuit), 13 is a control unit, 14
is the calculation part. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. v! J1 Diagram ARA ARB ARC Sei Harada Sengo

Claims (1)

[Scope of Claims] In a parallel data processing device having a plurality of basic arithmetic elements of the same type that are controlled in the same way, each basic arithmetic element has an addressable register file and an address to this register file. An address register for determining each basic operation element, a 2-bit flag register for representing the state within each basic operation element, and a 2-bit flag register for determining whether the value of the address register is '0' or not. ', a determination circuit that inverts the value of 1 bit of the flag register, and based on each value of the flag register, outputs the data read from the register file as it is based on the value of the address register, or outputs each bit of the data as is. or all bits'
A selector that selects whether to output a value of 0' or a value of all bits '1', and an arithmetic circuit that inputs data read from the register file based on an externally input address and data via the selector. If the values of the exponent parts of the operands differ in floating point addition and subtraction in each basic calculation element, the value based on the difference is stored in the above address register, and the value of the mantissa part of the operand with the smaller value of the exponent part is used as the exponent. By reading from the register file according to the operand with a large part value, the data in each basic calculation element performs different digit alignment processing of the address read from the register file, and in floating point calculations, the upper part of the mantissa part of the operand is read from the register file. If there is a '0' digit, the value based on that number is stored in the above address register and read from the register file starting from the most significant digit that is not '0' in the mantissa. A parallel data processing method characterized by executing normalization processing for different addresses read from a register file.