JPH0758714B2 - Method for manufacturing GaAs semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for manufacturing a self-aligned Schottky gate GaAs semiconductor device.

[Technical background of the invention and its problems] The figure of merit of a _GaAs FET is described by C _gs / gm. Where C _gs is the gate-source capacitance and gm is the FET transconductance. Furthermore, the actual gm is gm = g _mo / (1 + g _mo
・ R _s ). Here, g _mo is the intrinsic transconductance determined by the characteristics of the operating layer of the FET, and R _s is the source-gate resistance. This g _mo is the maximum g _m that can be drawn,
In the conventional MESFET as shown in FIG. 4, there is a series resistance R _s between the source and the gate, which makes g _m smaller than g _mo . Therefore, reducing the series resistance R _s is the key to improving the performance of GaAs FETs.
As one of the methods, a method of introducing a high-concentration ion implantation layer into the source / drain regions in a self-aligned manner is known. A typical example of this self-alignment method is shown in FIG. This is a high-concentration ion implantation using the gate electrode 24 as a mask,
7 is formed close to the gate electrode 24. However, in the MES FET having such a structure, during the activation heat treatment of the high-concentration ion-implanted layer, the impurity ions in the implanted layer may diffuse and the expanded source / drain regions may come into contact with the gate electrode. When the high-concentration ion-implanted layer comes into contact with the gate electrode in this way, the breakdown voltage decreases to 1 to 2 V, which causes fluctuations in threshold voltage and deterioration of Schottky characteristics. To avoid such an effect, the distance between the high-concentration ion-implanted layer and the gate electrode may be increased, but if this distance is set too large, R _s
And the advantage of the self-alignment method is diminished. This separation distance depends on the method of forming the source / drain regions, but a separation distance of 2000 to 3000Å is suitable. Conventionally, for this separation, structures such as dry etching using a chemical reaction that isotropically etches and side walls such as SiO ₂ film were taken, but all of them are controllable, reproducible, and complicated in process. There are problems such as
Therefore, there is a need for a method of forming the source / drain region and the gate electrode with good reproducibility and accuracy.

[Object of the Invention] It is an object of the present invention to provide a method for manufacturing a GaAs semiconductor device that enables the realization of a high-speed GaAs IC.

[Summary of the Invention] In the process of forming a Schottky barrier on a GaAs substrate and forming a gate electrode used as an ion implantation mask for source / drain, when the gate electrode is processed by RIE using a resist pattern as a mask To
By changing the reaction gas pressure, the side etch amount is controlled, the gate electrode and the source / drain regions are separated, and a high breakdown voltage and high performance FET can be uniformly formed in the plane. This is because when the gas pressure is low, the mean free path of the particles is long, so the particles enter the surface without losing their kinetic energy, resulting in anisotropic etching. Particles with are lost their directionality due to collisions between particles in the discharge space,
This is because the etching is isotropic.
Further, damage to the GaAs substrate due to high self-bias such as low gas pressure discharge can be reduced by increasing the gas pressure. FIG. 3 shows the relationship between the reaction gas pressure and the self-bias. As described above, according to the manufacturing method of the present invention, an FET having a high breakdown voltage and a high g _m can be formed uniformly in the wafer surface with good reproducibility, and is suitable as a MESFET manufacturing method for a GaAs integrated circuit.

[Advantages of the Invention] By applying the processing method of the present invention to the formation of the gate electrode of the self-aligned GaAs MESFET, a higher performance FE is obtained.
T can be uniformly obtained within the wafer surface.

[Embodiment of the Invention] FIG. 1 is a specific embodiment of a method of manufacturing a GaAs integrated circuit composed of a self-aligned GaAs MESFET using WN as a gate metal, which uses the processing method of the present invention.

First, Si ⁺ ions are implanted into the semi-insulating GaAs substrate 21 using the mask 22 at 2 × 10 ¹² cm ^{-2 at} 50 KeV and heat treatment is performed at 850 ° C. for 15 minutes to activate the ion-implanted layer (first). Figure (a)).

Next, WN24 as a gate metal is deposited on the entire surface of the wafer by reactive sputtering. A gate pattern 25 is formed by photoresist (FIG. 1 (b)).

Next, WN24, which is the gate metal, is processed by RIE using the photoresist as a mask. Figure 2 shows the gas pressure dependence of the side etch rate. From these results, in order to maintain anisotropy in the first half of processing, the reaction gas pressure was set to 5 Pa, and in the second half of processing, the reaction gas pressure was set to 30 Pa to offset the source / drain regions. It was also confirmed that the processing shape and the side etching amount can be controlled easily and with good reproducibility by changing the magnitude of the gas pressure and the timing of changing the gas pressure (Fig. 1 (c)).

Self-aligned to this gate electrode, Si ⁺ ions are implanted into the source 26 and drain 27 regions at 120 KeV, 3 × 10 ¹³ cm ^-2 , and P
The SG film 28 is activated by cap annealing at 800 ° C. for 10 minutes (FIG. 1 (d)).

An ohmic electrode 29 of AuGe / Au is formed in the source / drain region by lift-off method, and heat treatment is performed at 420 ° C. for 2 minutes (FIG. 1 (e)).

The transconductance of the GaAs MESFET prototyped in the manufacturing process according to the present invention is extremely excellent at 250 mS / mm at a gate length of 1.0 μm, and the breakdown voltage is high at 7 V or higher, and not only the DCFL circuit but also a BFL circuit using a normally-on type FET. It was confirmed that a high-performance FET that can also be applied to the wafer can be obtained uniformly in the wafer surface.

[Brief description of drawings]

FIG. 1 is a process sectional view for explaining an embodiment of the present invention, FIGS. 2 and 3 are drawings for explaining the technical contents of the present invention in detail, and FIGS. 4 and 5 are It is a figure for demonstrating the technical background of this invention. 21 ... GaAs substrate, 22 ... Mask 23 ... Operating layer, 24 ... Gate electrode 25 ... Resist pattern, 26 ... Source 27 ... Drain, 28 ... PSG film 29 ... Ohmic electrode, d ... Gate, source spacing

Continuation of the front page (56) Reference JP-A-51-97369 (JP, A) JP-A-53-143177 (JP, A) JP-A-57-128071 (JP, A) JP-A-58-123728 (JP , A)

Claims (1)

[Claims] 1. A step of forming a gate electrode on a GaAs substrate by using a reactive ion etching apparatus with a gate electrode processing pattern of a predetermined width as a mask, and impurity implantation using the gate electrode processing pattern as a mask. A step of activating the impurities by a post heat treatment to form source and drain regions, and when forming the gate electrode, the reaction gas pressure is changed after a predetermined time to perform anisotropic etching. A method for manufacturing a GaAs semiconductor device, characterized in that isotropic etching is performed to form a width of a bottom portion of the gate electrode smaller than that of the gate electrode processing pattern having the predetermined width.