JPH075843A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To obtain a liquid crystal display device which suppresses delicate variation of display gradation affected by pixel capacity and improves the quality of display by arranging many data bus lines on the other glass substrate facing a glass substrate on which many pixel electrodes are arranged and compensating voltage of data bus lines in accordance with voltage of adjacent data bus lines. CONSTITUTION:Voltage compensating means 21a-21c apply compensation in accordance with an input voltage of both side terminals R, L to an input voltage of a central terminal C and output it from a terminal 0. Voltage inputted to the central terminal C of this voltage compensating means 21a-21c are output of the final stage amplifier 20a-20c of a data driver 13U, and data voltage of pixel (a), (b) or (c) being adjacent in the horizontal direction on the screen. For example, data voltage of the pixel (b) is inputted to the central terminal of the voltage compensating means 21b located in the center, data voltage of the pixel (a) is inputted to the left side terminal L, and data voltage of the pixel (c) is inputted to the right side terminal R. Thus, liquid crystal voltage applied to an object pixel is compensated in accordance with liquid crystal voltage applied to an adjacent pixel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix liquid crystal display device, and more particularly to a counter drive type liquid crystal display device. Although it is said that the liquid crystal display device is inferior to the CRT type display device in terms of response speed and display quality, it has reached a practically sufficient level with the advent of an active matrix liquid crystal display device using a TFT (thin film transistor). I feel like I've reached it.

However, the yield is still low,
As far as the screen size is concerned, only up to 10-inch class has been put into practical use, and it cannot be said that the recent demands for larger screens of personal computers, TVs, etc. are sufficiently satisfied. Therefore, a "opposed drive" liquid crystal display device has been proposed which has a simpler display panel structure than the conventional "common electrode" liquid crystal display device and can improve the yield.

[0003]

2. Description of the Related Art FIG. 9 is a structural diagram of a display panel of an opposed drive type liquid crystal display device. FIG. 9 is a plan view representatively showing three pixels. 1a to 1c are pixel electrodes, and 2a to 2c are TFTs.
Semiconductor layers for 3a to 3c are reference electrodes,
Reference numerals a to 4c are data bus lines wired in the vertical direction of the screen, 5 and 6 are reference bus lines wired in the horizontal direction of the screen, and 7 is a gate bus line similarly wired in the horizontal direction.

When a predetermined voltage is applied to the gate bus line 7 to turn on the TFT, the reference bus line 5 and the pixel electrodes 1a to 1c are connected, and the pixel electrodes 1a to 1 are connected.
c and the reference bus line 5 become equipotential. In this state, for example, when an appropriate display voltage is applied to the data bus line 4a, the liquid crystal portion sandwiched between the data bus line 4a and the pixel electrode 1a has a difference voltage between the display voltage and the reference bus line 5 voltage. A corresponding voltage (hereinafter referred to as "liquid crystal voltage") is written.

In the opposed drive type, as shown in the AA sectional view of FIG. 9 in FIG. 10, the pixel electrode 1c, the semiconductor layer 2c, the reference electrode 3c, the insulating layer 8, the reference bus line 5 and the gate bus line 7 are provided. The data bus line 4c is formed on one glass substrate 9 and on the other glass substrate 11 facing the glass substrate 9 with the liquid crystal layer 10 in between.

According to this, since the liquid crystal layer 10 is interposed between the vertical data bus line 4c and the horizontal reference bus line 5 (and the gate bus line 7),
The distance between the two (that is, the distance between the intersecting bus lines) can be increased by the thickness of the liquid crystal layer 10, which is far larger than that in the common electrode type in which the bus lines are arranged in an intersecting manner on the same glass substrate. Manufacturing is facilitated and the yield can be improved.

[0007]

However, in such a counter drive type liquid crystal display device, the parasitic capacitance (hereinafter referred to as "pixel capacitance") between adjacent liquid crystal electrodes is considerably large, and the adjacent pixel due to capacitive coupling is used. There is a problem that the liquid crystal voltage of the pixels for which writing has already been completed slightly changes due to the influence of 1.

FIG. 11 is an equivalent circuit diagram of FIG. 10, and C _{PP in} the figure is a pixel capacitance parasitic between pixel electrodes. In addition,
C _DS is the capacitance between the pixel electrode and the reference bus line, C
_LC is the capacitance between the pixel electrode and the data bus line (liquid crystal capacitance), and C _GS is the capacitance between the pixel electrode and the gate bus line. The subscripts / below are pixel numbers. FIG. 12 is an example of drive waveforms for explaining the problem. VDa is the voltage of the data bus line 4a, VDb is the voltage of the data bus line 4b, VR is the voltage of the reference bus line 5, and VG is the voltage of the gate bus line 7. The voltage, VEa, is the liquid crystal voltage written in the liquid crystal portion between the pixel electrode 1a and the data bus line 4a, and V _M is the variation of the liquid crystal voltage of the pixels for which writing has already been completed.

The waveforms in the left half of FIG. 12 are VDa and VDb.
Is stable at the same potential. V in this case
Ea becomes a potential corresponding to the difference voltage between VR and VDa,
The display gradation is given without any problem by the effective value of VEa (dotted line). On the other hand, the waveform on the right half of FIG.
A case where the potential of VDb changes (e.g. decrease at time t _0), VEA in this case, reduced side following the change of VDb are undesirably changed (V _M). This is VD
The fluctuation of the liquid crystal voltage of the adjacent pixel caused by the change of b
This is because it is transmitted to VEa through the pixel capacitance. [Purpose] Therefore, an object of the present invention is to provide a liquid crystal display device in which a subtle variation in display gradation due to the influence of a pixel capacitance is suppressed, and thus display quality is improved.

[0010]

In order to achieve the above object, the present invention arranges a large number of pixel electrodes on one glass substrate and a large number of glass electrodes on the other glass substrate facing the one glass substrate. A liquid crystal display device in which data bus lines are arranged, and a voltage corresponding to a difference voltage between the voltage of the pixel electrode and the voltage of the data bus line is written in a liquid crystal layer between the pixel electrode and the data bus line, It is characterized by further comprising voltage correction means for correcting the voltage of the data bus line according to the voltage of the adjacent data bus line.

[0011]

According to the present invention, since the liquid crystal voltage written in the target pixel is corrected according to the liquid crystal voltage written in the adjacent pixel, a subtle change in the display gradation due to the influence of the pixel capacitance parasitic between the adjacent pixels is suppressed. The display quality is improved.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIGS. 1 to 5 are views showing a first embodiment of a liquid crystal display device according to the present invention. In FIG. 1, reference numeral 10 denotes a liquid crystal panel. The liquid crystal panel 10 includes a large number of data bus lines laid in the vertical direction of the screen and a large number of gate bus lines (and reference bus lines) laid in the horizontal direction. This is a publicly known structure in which a TFT and a liquid crystal electrode are connected at an intersection, and specifically, has a structure of an opposed drive type (see FIGS. 9 and 10).

Reference numeral 11 indicates the operation of the liquid crystal display device based on various control signals (clock signal CLK, horizontal / vertical synchronizing signals HSYNC / VSYNC) and display data (red data R, green data G, blue data B) from the outside. Controller that generates various necessary internal signals, 12 is HSYNC from controller
The gate drivers 13U and 13L apply display data R, G, and B from the controller 11 to each pixel on a pixel-by-pixel basis in response to a signal synchronized with A data driver 14U, 14L that takes in and converts into an analog voltage (hereinafter referred to as "display voltage") according to a display gradation and outputs it all together at the timing of HSYNC, 14U, 14L make a predetermined correction to the display voltage from the data driver 13U, 13L. This is a voltage conversion circuit that is applied and supplied to the data bus line of the liquid crystal panel 10. In addition,
Reference numerals U and L attached to 13 and 14 respectively indicate those positioned above and below the liquid crystal panel 10.

FIG. 2 shows a data driver 13U (or 13).
FIG. 13 is a configuration diagram of a main part of L; hereinafter 13U is representative; and a voltage conversion circuit 14U (or 14L; hereinafter 14U is representative). In this figure, 20a to 20c are data drivers 13U.
, 21a to 21c are voltage correcting means for correcting the input voltage of the central terminal C according to the input voltages of the both terminals R and L and outputting the voltage from the terminal O. 22a to 22c are output enable signals (HSYNC). In response to a signal synchronized with), analog switches 23a to 23c are turned on all at once, and output buffers 23a to 23c. Note that a to c represent pixel numbers.

Here, the voltage input to the central terminal C of the voltage correction means 21a to 21c is the output VDa, VDb or VDc of the amplifier 20a to 20c at the final stage of the data driver 13U, and the voltage VDa, VDb or VDc. Is
This is the data voltage of the pixel a, b, or c adjacent in the horizontal direction on the screen. Three representative voltage correction means 21a-2
Of the 1c, for example, the voltage correction means 2 located in the middle
The data voltage VDb of the pixel b is input to the central terminal C of the pixel 1b, and the pixel a is input to the left terminal L of the voltage correction unit 21b.
Data voltage is input, and the voltage correction means 21b is further input.
The data voltage of the pixel c is input to the right terminal R of the.

FIG. 3 is a functional block diagram of the voltage correction means 21a to 21c (21b as a representative example in the figure). 24
Is a difference calculation unit that calculates a difference value ΔVD between 2 × VDb and VDa + VDc, 25 is a multiplication unit that calculates ΔVD × K (where K is a predetermined multiplication coefficient), and 26 is an output of the multiplication unit 25 (Δ
VD × K) is an addition unit that adds VDb to
Execute the following arithmetic expression.

VDb ′ = VDb + K (2VDb−VDa−VDc) ... The multiplication coefficient K is determined by various parasitic capacitances of the liquid crystal panel 10 (see FIG. 1).
1 is a constant determined from C _GS , C _DS , C _LC and C _PP of the equivalent circuit, and can be calculated using the following equation in the case of the panel structure of FIG. 9, for example. K = γ / (1-β-2γ), where γ = C _PP C _LC / [(C _LC + C _GS + C _DS ) (C _LC + C _GS + C _DS + 3C _PP )] …… β = (C _GS + C _DS ) / (C _LC + C _GS + C _DS ) ...

Here, the fluctuation component V _M of the liquid crystal voltage of the pixel of interest
(See FIG. 12) was found by the analysis of the present inventor to be obtained by the following equation. V _M = (1−β) V _D −V _R + γ (V _D1 + V _D2 −2V _D ), where V _D is the voltage applied to the pixel of interest (data bus line voltage), and V _D1 and V _D2 are voltage applied to the pixels of the two neighboring pixel of interest (the voltage of the data bus lines of the two neighboring), V _R is the voltage of the reference bus line.

Now, considering the case where the pre-correction data voltages (VDa to VDc) are applied to V _D , V _D1 and V _D2 (in the case of the prior art), the third term in the above equation causes both sides to be adjacent. The larger the data voltage, the larger V _M. That is,
A value of data voltage VDb and twice the target pixel, the data voltage VDa of two neighboring, when is equal to the sum of VDc, the third term of the above equation is the V _M becomes "0" is the minimum.

[0020] Therefore, the third term of the above equation to produce a correction voltage that is set to "0", by correcting the data voltage VDb of the pixel of interest using the correction voltage is always displayed to minimize V _M The quality can be improved. When the correction voltage to x, (1-β) ( V D + x) -V R + γ _{[V D1 + V D2 -2 (V} D + x) ] _{= (1-β) V D} -V R ...... above equation The right side shows the case where the adjacent data voltages are equal, and the left side shows the case where the correction voltage x is added to the data voltage of the pixel of interest.
Solving the above equation, x = [γ / (1−β−2γ)] (2V _D −V _D1 −V _D2 ), and this x should be corrected by adding the data voltage of the pixel of interest. For example, assuming that the data voltage of the pixel of interest is VDb, the corrected data voltage VDb 'is given by VDb' = VDb + [γ / (1-β-2γ)] (2VDb-VDa-VDc).

The difference calculation unit 24 of FIG. 3 is (2V _D −
V _D1 −V _D2 ), the multiplication unit 25 calculates x, and the addition unit 26 calculates the above formula. FIG. 4 is a specific configuration diagram of the voltage correction unit 21b having the above-described arithmetic function, and the first to third operational amplifier circuits 27 are shown.
.About.29 form a difference calculating unit 24, a fourth operational amplifier circuit 30 forms a multiplying unit 25, and a fifth operational amplifier circuit 31.
Constitutes an adder 26. Reference numerals 32 to 47 are resistors, and the value (R ₄₃ ) of the input resistance 43 of the fourth operational amplifier 30.
And the value of the feedback resistor 44 (R ₄₄ ) (R ₄₄ /
R ₄₃ ) multiplication coefficient K (K = [γ / (1-β-2γ)])
Adjust. The input resistance 4 of the fourth operational amplifier 30
All resistors except 3 and the feedback resistor 44 are set to the same value.

[0022] From circuit of Figure 4 having such a _{configuration, VDb + (R 44 / R} 43) (2VDb-VDa-VDc) data voltage VDb corrected given by ... 'is output. Therefore, according to the above embodiment, the data voltage VDb of the target pixel is corrected according to the difference between the data voltage VDb of the target pixel and the data voltages VDa and VDc on both sides, and the corrected data voltage VDb ′ is obtained. Since the data is applied to the data bus line of the pixel of interest, it is possible to suppress the fluctuation (V _M ) of the effective value voltage applied to the liquid crystal and improve the display quality.

FIG. 5 is a characteristic diagram showing the improvement effect of the above-described embodiment. The vertical axis represents the luminance shift of the target pixel, and the horizontal axis represents the difference (0V) between the data voltage of the target pixel and the data voltage of the adjacent pixel. = No difference). When the correction is not performed, as shown by the broken line in the figure, the maximum luminance deviation is about 30%. However, by performing the correction, the luminance deviation can be suppressed to about ± 3% at the maximum. did it. This is a suppression effect of about 1/20.

Second Embodiment FIG. 6 is a diagram showing a second embodiment of the liquid crystal display device according to the present invention, which is an improved example of the voltage conversion circuits 14U and 14L of the first embodiment. In FIG. 6, 14U '(or 14
L ') is a voltage conversion circuit, and the voltage conversion circuit 14U'
(Or 14L ') is provided with the same voltage correction means 21a to 21c as in the first embodiment, the first analog switches 50a to 50c, and the second analog switches 51a to 5c.
1c, third analog switches 52a to 52c, fourth analog switches 53a to 53c, fifth analog switches 54a to 54c, and hold capacitors 55a to.
55c is included.

First and second analog switches 50a ...
50c and 51a to 51c are voltage correction means 21a to 21.
Central terminal C of c and data driver 13U (or 13L)
Are connected in series with the final stage amplifiers 20a to 20c, and hold capacitors 55a to 55c are connected to the first and second analog switches 50a to 50c and 51a to 51c.
Connected between the connection points Pa to Pc and the ground, and the third analog switches 52a to 52c are the voltage correction means 21a.
Of the fourth analog switches 53a to 53c, which are connected between the output terminals O of the to 21c and the connection points Pa to Pc, are adjacent to the left side of the drawing (for example, the analog switch 5).
3b is Pa) and the left side terminals L of the voltage correction means 21a to 21c, and the fifth analog switches 54a to 54c are connection points adjacent to the right side of the drawing (for example, the analog switch 53b). If so, it is connected between Pc) and the right terminal R of the voltage correction means 21a to 21c.

In such a configuration, (1) first, the first, second, fourth and fifth analog switches 5 are kept with the third analog switches 52a to 52c in the OFF state.
0a to 50c, 51a to 51c, 53a to 53c and 5
4a to 54c in the ON state (this state is shown in FIG.
The same), the voltage correction means 21a to 21c output the data voltages VDa 'to VDc' corrected according to the adjacent data voltages. (2) Then, the third
When the analog switches 52a to 52c are turned on, the corrected data voltages VDa 'to VDc' are held in the hold capacitors 55a to 55c. (3) Next,
When the second analog switches 51a to 51c, the fourth analog switches 53a to 53c, and the fifth analog switches 54a to 54c are turned on, the corrected data voltage VDa ′ held in the hold capacitors 55a to 55c. VDc 'is taken into the voltage correction means 21a to 21c, and the data voltage VDa' to VDc 'corrected according to the adjacent data voltage (however, the corrected data voltage) is output from each voltage correction means 21a to 21c. Is output. Therefore, (1) to (3) are executed immediately after the power is turned on,
After that, by repeating (2) and (3) an appropriate number of times, the data voltage of the pixel of interest can be corrected based on the corrected data voltage, and the accuracy of the correction can be improved.

Third Embodiment FIGS. 7 and 8 are views showing a third embodiment of the liquid crystal display device according to the present invention, which is digitally constructed. In this figure, 60 is A for converting each analog data voltage of R, G, B into digital data signals R, G, B
A / D converter, 61 is a delay circuit for giving a predetermined delay time to each signal, and 62 is a comparison operation circuit.

The comparison calculation circuit 62 has a calculation function similar to that of the voltage correction means of the first embodiment. Here, the data signal of the pixel of interest is converted into the data signal of the pixels on both sides thereof (for example, of the pixel of interest). When the data signal is G, it is corrected according to R and B). By the way, the input timing of the data signals R, G, and B is, for example, as shown in FIG.
80 pixels in the 0th column (hereinafter [20-80] pixels), 81 pixels in the same column (hereinafter [20-81] pixels) and 82 pixels in the same column (hereinafter [20-82] pixels) are input at the same time T _i . After that, 83 pixels in the same column (hereinafter [20-83] pixels), 84 pixels in the same column (hereinafter [20-84] pixels) and 85 pixels in the same column (hereinafter [20-85] pixels) are at the same time T _i. Enter with ₊₁ .

Now, assuming that the target pixel is the [20-82] pixel, the comparison target pixels are the [20-81] pixel and the [20-81] pixel.
Although it is a −83] pixel, it is inconvenient because the [20-83] pixel is input with a delay. Therefore, in this embodiment, [20
When comparing the −82] pixel and the [20-83] pixel,
The delay circuit 61 causes the [20-82] pixel to have T _{i + 1.}
-T _{i is} delayed.

[0030]

According to the present invention, since the voltage correcting means for correcting the voltage of the data bus line according to the voltage of the adjacent data bus line is provided, the subtle fluctuation of the display gradation due to the influence of the pixel capacitance. It is possible to provide a liquid crystal display device in which the display quality can be suppressed and display quality is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is a configuration diagram of a main part including a voltage correction unit of the first embodiment.

FIG. 3 is a functional block diagram of voltage correction means of the first embodiment.

FIG. 4 is a specific configuration diagram of the voltage correction means of the first embodiment.

FIG. 5 is a characteristic diagram showing a correction effect of the first embodiment.

FIG. 6 is a configuration diagram of a main part including a voltage correction unit according to a second embodiment.

FIG. 7 is a configuration diagram of a main part including a voltage correction unit according to a third embodiment.

FIG. 8 is a timing chart of a data signal of a third embodiment and a pixel layout diagram on a liquid crystal panel.

FIG. 9 is a plan view of a main part of a liquid crystal panel.

10 is a cross-sectional view taken along the line AA of FIG.

FIG. 11 is an equivalent circuit diagram of FIG.

FIG. 12 is a diagram illustrating a defect of a conventional example.

[Explanation of symbols]

 1a to 1c: Pixel electrodes 4a to 4c: Data bus lines 9 and 11: Glass substrate 10: Liquid crystal layer 21a to 21c: Voltage correction means 62: Comparison calculation circuit (voltage correction means)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenichi Oki 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (1)

[Claims] 1. A plurality of pixel electrodes are arranged on one glass substrate, and a plurality of data bus lines are arranged on the other glass substrate facing the one glass substrate, and the voltage of the pixel electrode and the data bus are arranged. In a liquid crystal display device that writes a voltage corresponding to a voltage difference between a line voltage and a liquid crystal layer between the pixel electrode and the data bus line, the voltage of the data bus line is set to a voltage of an adjacent data bus line. A liquid crystal display device comprising a voltage correction means for performing a correction in accordance therewith.