JPH0758323A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing an MOS transistor of LDD structure wherein processes are shortened and simplified without deteriorated performance by forming a low concentration diffusion layer and a high concentration diffusion layer by one ion implantation. CONSTITUTION:At a step part between a semiconductor substrate 1 and a gate electrode 4 formed on the semiconductor substrate 1, a side wall 18 having linear slope is formed through formation of an insulation film and etch-back (b, c, d), and after the completion of it, ion implantation is performed through the side wall 18 (e), so that an MOS semiconductor device of LDD structure is manufactured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS transistor having an LDD structure.

[0002]

2. Description of the Related Art With the increase in integration and miniaturization of semiconductor elements, it has been attempted to increase the concentration of source and drain or to reduce the diffusion depth in order to shorten the channel due to the scaling rule of MOS transistors. . However, by increasing the concentration of the source and drain and making the diffusion depth shallow, the electric field in the vicinity of the drain becomes strong, and the characteristics of the transistor deteriorate significantly due to hot carriers and the like. Since hot carriers are generated by a high electric field, miniaturized transistors have a greater effect at the same voltage. Therefore, conventionally, an LD as shown in FIG.
A MOS transistor structure called a D (Lightly, Doped, Drain) structure is used. This LDD structure has a drain with the highest electric field (see FIG.
The high-concentration diffusion layer 6) in the vicinity has a low-concentration impurity region 5
(Hereinafter referred to as a low-concentration diffusion layer), and a high-concentration diffusion layer 6 (generally formed with the same conductivity type as that of the low-concentration diffusion layer 5) is provided through the low-concentration diffusion layer 5 to form a concentration gradient. This lowers the electric field strength near the drain.

An example of a conventional method for manufacturing a MOS type semiconductor device having an LDD structure will be described with reference to FIG. First, base 1
Ions are implanted into the structure having the element isolation region 2, the gate insulating film 3, and the gate electrode 4 thereon to form the low concentration diffusion layer 5 (step a). Next, an insulating film 7 such as a silicon oxide film is deposited by the CVD method (step b). Furthermore, the insulating film 7 is removed by a combination of dry etching and wet etching, leaving only the side wall of the gate electrode 4 (step c). The remaining insulating film 7 is referred to as a side wall 8. Next, using the side wall 8 as a mask, ion implantation is performed to form the high concentration diffusion layer 6 (step d). An offset is formed between the low-concentration diffusion layer 5 and the high-concentration diffusion layer 6 by using the mask formed of the sidewalls 8 to form an LDD structure.

[0004]

However, in the conventional method of forming the LDD structure described above, two ion implantations are required to form the low-concentration diffusion layer and the high-concentration diffusion layer. It is necessary to combine dry etching and wet etching for the wall formation, which complicates the process of forming the LDD structure and prolongs the process. In addition, there is a problem that the product may be invaded by particles during the process. It also has a secondary problem that the possibility of lowering the yield of the device increases.

Therefore, the present invention has been made in view of the above circumstances, and solves the problems of the complicated process of forming the conventional LDD structure and the prolongation of the process described above. An object of the present invention is to provide a method for manufacturing a MOS transistor having an LDD structure in which a concentration diffusion layer and a high concentration diffusion layer are formed at the same time, and the process is shortened and simplified without deteriorating the performance.

[0006]

According to the present invention, a sidewall having a linear slope is formed in a step portion between a semiconductor substrate and a gate electrode formed on the semiconductor substrate by forming an insulating film and etching back. Formed by forming a sidewall, and then performing ion implantation through the sidewall to form L.
The above object is achieved by manufacturing a MOS type semiconductor device having a DD structure.

The formation and etchback of the insulating film in the formation of the side wall of the present invention can be performed by two steps of the film formation step and the etchback step, or the film formation step and the etchback step can be performed simultaneously in one step. You can also do it.

Ion implantation for forming the LDD structure of the present invention is a single step through a sidewall.

[0009]

According to the present invention, with the above structure, a linear slope is formed in the step portion between the semiconductor substrate and the gate electrode formed on the semiconductor substrate by forming and etching back the insulating film. A sidewall having a low-concentration diffusion layer and a low concentration diffusion layer on the substrate corresponding to the linearly sloped portion by ion-implanting through the linear inclination of the sidewall after forming the sidewall. An offset portion that changes from the concentration diffusion layer to the high concentration diffusion layer is formed, a high concentration diffusion layer is formed on a substrate corresponding to a flat portion without sidewalls, and a diffusion layer having a difference in concentration is formed. Form a transistor.

The sidewall having the linear inclination can be formed by two steps of an insulating film forming step and an etch back step, or by performing the insulating film forming step and an etch back step at the same time. Can be

When ion implantation for forming a diffusion layer is performed through an insulating film of a sidewall having a linear inclination according to the present invention, the inclination changes the vertical distance from the surface of the insulating film to the substrate. Therefore, the number of ions that can reach the substrate changes depending on the location. Therefore, the impurity of the substrate is low where the insulating film is thick,
On the contrary, a high-concentration impurity layer can be formed where the insulating film is thin. Therefore, a diffusion layer having a concentration gradient can be formed by one ion implantation process, and the process can be simplified.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings, but the present invention is not limited to the embodiments.

Example 1 First, Example 1 of the present invention
Will be described with reference to the drawings showing the main steps of Example 1 of the method for manufacturing a semiconductor device of FIG.

In the formation of the LDD structure according to the first embodiment of the present invention, the diffusion layer is formed by using the side wall having a constant inclination angle. As a method of forming the side wall having the constant inclination angle, The bias sputtering method is used. Then, the diffusion layer having the concentration gradient is formed by performing the ion implantation once by using the sidewall having the constant inclination angle.

In the following description, (a) through (a) in FIG.
The description will be given according to the step indicated by the symbol (f). In the following steps, the sidewalls are formed by steps a to d, and the diffusion layer is formed by ion implantation in steps e and f.

Step a: First, as shown in FIG. 1A, a gate oxide film 3 and an element isolation region 2 are formed on a semiconductor base 1 made of single crystal silicon, and the gate oxide film 3 is formed. The gate electrode 4 is formed on. The gate oxide film 3, the element isolation region 2, and the gate electrode 4 can be formed by a usual manufacturing method.

Step b: Next, as shown in FIG. 1B, the insulating film 7 is deposited by the CVD method. The thickness of the insulating film 7 is preferably about 0.3 to 0.5 μm when the thickness of the gate electrode is 0.4 μm, for example.

Step c: Next, as shown in FIG. 1C, the insulating film 7 is etched back by a bias sputtering method using Ar ⁺ ions, for example. The bias-sputtering method is one in which an RF bias is applied to a support that supports a substrate to perform sputtering, and the degree of etching of this sputter has characteristics that depend on the tilt angle having a peak near a tilt angle of 45 degrees. When ions are made to enter the substrate in a direction perpendicular to the substrate due to this bias, an inclination of about 45 degrees occurs due to sputter etching in the step portion formed by the gate electrode and the like.

Step d: At the stage where the flat portion of the insulating film 7 is almost etched back by the etching back in the step c, as shown in the figure, the sidewalls of the gate electrode 4 and the element isolation region 2 are, for example, about 45 degrees. An insulating film layer having an inclination angle of is formed. Using the insulating film layer having this inclination angle as the sidewall 18, the diffusion layer is formed by the following steps.

Step e: Ion implantation is performed on the base 1 through the sidewall 18. In the ion implantation, for example, when forming an n-type conduction type diffusion layer, As ions are subjected to 5 × 10 5 at an acceleration voltage of 100 kV.
It can be performed at a rate of ¹⁵ (cm ^-2 ). In this ion implantation, since the insulating film layer of the sidewall 18 has a tilt angle, only a small number of ions reach the base 1 in a portion where the insulating film layer has a large film thickness. Layer 21 is formed. On the other hand, many ions reach the base 1 in the thin portion of the insulating film layer of the sidewall 18 and in the flat portion where the sidewall 18 is not formed, so that the high-concentration impurity layer 22 is formed. The hatched portion in (e) of FIG. 1 indicates the implanted impurity layer 20 including the low-concentration impurity layer 21 and the high-concentration impurity layer 22, and the low-concentration impurity layer 21 is the depth of the base 1. The impurity layer 22 having a high concentration and a shallow depth is formed deep in the depth direction of the base 1.

The difference between the sidewall 18 of the present invention and the conventional sidewall 8 lies in the thickness thereof, and the thickness of the conventional sidewall 8 is about the same as that of the gate electrode 4.
Under the ion implantation conditions for forming the high-concentration diffusion layer, the ions cannot pass through the sidewall 8 and the low-concentration diffusion layer 5 cannot be formed. A step of forming the low concentration diffusion layer 5 is necessary. On the other hand, the sidewall 18 of the present invention
The ion has a sidewall 1 because the thickness of
A low-concentration diffusion layer 21 is formed by passing through a thin portion of No. 8, and at the same time, a high-concentration diffusion layer 22 is formed by passing through a flat portion where the sidewalls 18 are not formed.

Therefore, according to the method of manufacturing a semiconductor device of the present invention, a diffusion layer having a concentration gradient composed of a low concentration diffusion layer and a high concentration diffusion layer can be formed in one ion implantation step.

The concentration distribution of the diffusion layer is determined by the ion implantation conditions and the thickness of the sidewall in the incident direction of the implanted ions. The distribution of the ions in the depth direction after the ion implantation is the thickness of the sidewall. It changes according to the distribution as shown in the LSS theory with one parameter. Moreover, the thickness of the sidewall in the incident direction of the implanted ions is determined by the incident angle of the ions and the sidewall inclination angle.

Step f: After the above ion implantation step,
By performing heat treatment for activation of implanted ions and recovery of implanted defects, a MOS type semiconductor device having an LDD structure with a source / drain structure having a concentration gradient is formed. As an example of this heat treatment, the heat treatment is performed at 900 ° C in a nitrogen atmosphere at
Minute heat treatment can be employed.

(Effects peculiar to Embodiment 1) Embodiment 1 of the present invention
Then, in the bias sputtering method,
Since the incident angles of ions are substantially perpendicular to the substrate, it is possible to reproducibly obtain a linear inclined structure of the sidewall.

[Embodiment 2] Next, Embodiment 2 of the present invention will be described with reference to the drawings showing the main steps of Embodiment 2 of the method for manufacturing a semiconductor device in FIG.

In the formation of the LDD structure according to the second embodiment of the present invention, the diffusion layer is formed by using the sidewalls having the constant inclination angle as in the case of the first embodiment, and the constant inclination angle is obtained. As a method of forming the side wall, plasma CVD using bias / sputtering method or ECR plasma CVD using bias / sputtering method
Is used to form a side wall having a constant inclination angle at the same time as the formation of the insulating film, and using this side wall, a diffusion layer having a concentration gradient is formed by one-time ion implantation.

The bias sputtering method used in the second embodiment of the present invention is an ion sputtering method by applying a bias. For example, an EC using the bias sputtering method in combination is used.
In R plasma CVD, SiH ₄ and O ₂ , which are film forming components for forming an oxide film, and A for sputtering.
R gas is used as a used gas, and R is used as a support for supporting the wafer.
This can be done by applying an F bias. As a result, the film formation by CVD and the etch back by sputtering can be performed simultaneously, and the conventional etching process after film formation can be omitted.

Therefore, the difference between the second embodiment and the first embodiment lies in the sidewall forming step. In the second embodiment, the etching step of the first embodiment is omitted and the sidewalls are simultaneously formed in the film forming step. It is a thing.

In the following description, ECR plasma CVD (also referred to as bias.
FIG. 4 shows an example of a CVD method using a sputtering method).
The description will be given according to the steps indicated by reference numerals (a) to (e) in FIG.
To form a side wall, and in steps d and e, a diffusion layer is formed by ion implantation.

Step a: First, as in the first embodiment, as shown in FIG. 4A, the gate oxide film 3 and the element isolation region 2 are formed on the semiconductor base 1 made of single crystal silicon.
And a gate electrode 4 is formed on the gate oxide film 3. The gate oxide film 3, the element isolation region 2, and the gate electrode 4 can be formed by a usual manufacturing method.

Step b: Next, as shown in FIG. 4B, CVD is performed by a CVD method using both bias and sputtering.
The sidewalls are formed by simultaneously advancing the etching and the etching back. CVD with both bias and sputtering
As an example of the method, for example, as described above, there is ECR plasma CVD under the condition that SiH ₄ and O ₂ and Ar gas are used gases and an RF bias is applied to a support table that supports a wafer, As a film forming condition of the ECR plasma CVD method for applying a more specific bias, the degree of vacuum is 3 mTorr, the flow rate of SiH ₄ is 38.5 scc.
m, O ₂ flow rate 150 sccm, Ar flow rate 50 s
ccm, a microwave source of 5.45 GHz was applied with a power of 2500 W, and the plasma source was 13.26 M.
A high frequency of Hz is applied with a power of 1300 W to form an RF bias.

Step c: Sidewalls 28 are formed by the CVD method using both bias and sputtering. This side wall 28 is formed by the CVD film forming rate and Ar ⁺
It is formed by utilizing the property that the ion sputter etching rate has an ion incident angle dependency.
The dependence of the sputter etching speed on the ion incident angle has a peak at an ion incident angle of around 45 degrees, and when ions are made to enter the substrate in a vertical direction by this bias, it is formed by a gate electrode or the like. An inclination of about 45 degrees is generated in the step portion due to the sputter etching. Therefore, a side wall portion having a 45 ° inclined surface is formed in the step portion of the gate electrode 4, and the side wall 28 is formed. By utilizing the portion of the insulating film having the inclination angle of the sidewall 28, the diffusion layer can be formed by the following steps.

Further, since the ECR can form a high-density plasma in a low gas and can widely control the incident energy of ions by the bias voltage, the sputter etching rate can be easily controlled. The bias and the divergent magnetic field cause the ions to enter the substrate perpendicularly, so that submicron patterns can be dealt with.

Step d: Ion implantation is performed on the base 1 through the sidewall 28. The process of this ion implantation is the same as that shown in step e of the first embodiment, and in the structure in which the insulating film layer of the sidewall 28 has the inclination angle, a small number of ions are present in the thick insulating film layer. Only the base 1 is reached, which forms the low-concentration impurity layer 31, while the sidewall 28 is formed.
Of the thin insulating film layer and the side wall 2
Since many ions reach the base 1 in the flat portion where 8 is not formed, the high-concentration impurity layer 32 is formed. The hatched portion in (d) of FIG. 4 shows the implanted impurity layer 30 composed of the low-concentration impurity layer 31 and the high-concentration impurity layer 32, and the low-concentration impurity layer 31 is the base 1
And the high-concentration impurity layer 32 is formed deep in the depth direction of the base 1.

The state of the impurity concentration in the depth direction of the diffusion layer according to the second embodiment of the present invention is as shown in FIG. Figure 5
In A, A indicates the depth direction impurity concentration of the low concentration impurity layer 31, C indicates the high concentration impurity layer 32, and B indicates the depth direction impurity concentration of the impurity layer between A and C. Shows. The concentration distribution of the diffusion layer is determined by the ion implantation conditions and the thickness of the sidewall in the incident direction of the implanted ions as described above. The distribution of the ions in the depth direction after the ion implantation is the thickness of the sidewall. Is a parameter and changes according to the distribution as shown in the LSS theory. Further, the thickness of the sidewall in the incident direction of the implanted ions is determined by the incident angle of the ions and the sidewall inclination angle.

Since the difference between the conventional sidewall 8 and the sidewall 28 of the second embodiment of the present invention is the same as that of the first embodiment described above, the description thereof will be omitted.

Therefore, according to the method of manufacturing a semiconductor device of the present invention, a diffusion layer having a concentration gradient composed of a low concentration diffusion layer and a high concentration diffusion layer can be formed in one ion implantation step.

Step e: This step is the same as step f of the first embodiment, and therefore its description is omitted.

(Effects peculiar to the second embodiment) In the second embodiment, the etching process can be omitted when forming the sidewalls, and the process can be simplified.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention, which are not excluded from the scope of the present invention.

[0042]

As described above, according to the present invention,
In the method of manufacturing a MOS transistor of LDD structure, a low concentration diffusion layer and a high concentration diffusion layer are simultaneously formed by one-time ion implantation, and the process can be shortened and simplified without lowering the performance. .

[Brief description of drawings]

FIG. 1 is a diagram showing main steps of Example 1 of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a diagram illustrating a structure of a MOS transistor having an LDD structure.

FIG. 3 is a diagram showing main steps of a conventional method for manufacturing a semiconductor device.

FIG. 4 is a diagram showing main steps of Example 2 of the method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a diagram illustrating a state of impurity concentration in the depth direction of a diffusion layer of a semiconductor device according to the manufacturing method of the present invention.

[Explanation of symbols]

 1 Base 2 Element Isolation Area 3 Gate Oxide Film 4 Gate Electrode 7 Insulating Film 18, 28 Sidewall 20, 30 Injection Impurity Layer 21, 31 Low Concentration Diffusion Layer 22, 32 High Concentration Diffusion Layer 23, 33 Diffusion Layer

Claims (1)

[Claims] 1. A method for manufacturing a MOS type semiconductor device having an LDD structure, wherein a sidewall having a linear slope is formed in a step portion between a semiconductor substrate and a gate electrode formed on the semiconductor substrate, A method for manufacturing a semiconductor device, which is characterized in that it is formed by film formation and etch back, and ion implantation is performed after forming the side wall.