JPH0757619A - Electron emission element - Google Patents
Electron emission elementInfo
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- JPH0757619A JPH0757619A JP19575493A JP19575493A JPH0757619A JP H0757619 A JPH0757619 A JP H0757619A JP 19575493 A JP19575493 A JP 19575493A JP 19575493 A JP19575493 A JP 19575493A JP H0757619 A JPH0757619 A JP H0757619A
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は電子放出素子に関する。FIELD OF THE INVENTION The present invention relates to an electron-emitting device.
【０００２】[0002]
【従来の技術】電子の波長程度の薄い絶縁体膜（層）を
電子が透過する現象は、量子力学的トンネル効果として
知られている。そして、このトンネル効果を利用した装
置（もしくは素子）の一つとして、トンネル陰極があ
り、高輝度，低分散，低雑音の平面型陰極として注目さ
れている。なお、このトンネル陰極としては、ＭＯＳ構
造を利用したＭＯＳトンネル陰極がよく知られている
（日本電子工業振興会編，“真空マイクロエレクトロニ
クス調査報告”P.67〜76）。2. Description of the Related Art A phenomenon in which electrons pass through a thin insulator film (layer) having a wavelength of electrons is known as a quantum mechanical tunnel effect. A tunnel cathode is one of the devices (or elements) that utilizes this tunnel effect, and is attracting attention as a flat cathode with high brightness, low dispersion, and low noise. As this tunnel cathode, a MOS tunnel cathode using a MOS structure is well known (edited by Japan Electronic Industry Development Association, “Vacuum Microelectronics Research Report”, pages 67-76).
【０００３】ところで、前記ＭＯＳ構造トンネル陰極
は、一般に次のような手段で製造されている。図３ (a)
〜 (e)は、ＭＯＳ構造トンネル陰極の製造プロセスを模
式的に示したもので、先ず、たとえばｎ型Ｓｉウェハな
どの支持基板１面上に、たとえば熱酸化などにより、厚
さ 500〜1000nm程度の絶縁体層（酸化物層）２を形成す
る（図３(a))。次いで、前記形成した絶縁体層２を、た
とえばフォトリソグラフィーなどにより、電子放出部と
なる開口部３のパターニングを行ってから（図３(b))、
前記開口により露出した面を熱酸化させて厚さ10nm程度
の絶縁体層（酸化物層）４を形成する（図３(c))。By the way, the aforementioned MOS structure tunnel cathode is generally manufactured by the following means. Figure 3 (a)
~ (E) schematically shows the manufacturing process of the MOS structure tunnel cathode. First, for example, by thermal oxidation or the like, a thickness of about 500 to 1000 nm is formed on the surface of the supporting substrate 1 such as an n-type Si wafer. The insulating layer (oxide layer) 2 is formed (FIG. 3 (a)). Then, the insulating layer 2 thus formed is patterned by, for example, photolithography to form an opening 3 to be an electron emitting portion (FIG. 3 (b)),
The surface exposed by the opening is thermally oxidized to form an insulator layer (oxide layer) 4 having a thickness of about 10 nm (FIG. 3 (c)).
【０００４】その後、たとえば真空蒸着法もしくはスパ
ッタ法などを用いて、前記絶縁体層４を含む開口部３領
域の面上に、厚さ 6〜15nm程度の電子放出電極層５を形
成し（図３(d))、さらに引き出し電極層６および裏面電
極層７を形成することにより、ＭＯＳ構造トンネル陰極
が完成する（図３(e))。なお、上記製造プロセスにおい
て、電子放出電極層５の材質としては、たとえばＡｌ，
Ａｕ，Ｐｔなどが一般的に用いられ、また電子放出電極
層５および引き出し電極層６のパターニングは、シャド
ウマスクを用いて行われる。After that, an electron emission electrode layer 5 having a thickness of about 6 to 15 nm is formed on the surface of the region of the opening 3 including the insulator layer 4 by using, for example, a vacuum evaporation method or a sputtering method (see FIG. 3 (d)), and by further forming the extraction electrode layer 6 and the back surface electrode layer 7, the MOS structure tunnel cathode is completed (FIG. 3 (e)). In the above manufacturing process, the material of the electron emission electrode layer 5 is, for example, Al,
Au, Pt, etc. are generally used, and the electron emission electrode layer 5 and the extraction electrode layer 6 are patterned by using a shadow mask.
【０００５】そして、このＭＯＳ構造トンネル陰極は、
引き出し電極層６と裏面電極層７との間に、少くとも電
子放出領域の絶縁体層４が絶縁破壊を起こさないように
電圧を印加すると、電子放出電極層５表面から所望の電
子を放出する。たとえば、絶縁体層４の厚さ11nm，電子
放出電極層５の厚さ 6nm，開口部３平面積 2.5×10-3cm
2 の素子の場合、最大印加電圧（素子が破壊しない限界
の電圧）は10 Vで、そのときの放電電流密度は 6.8×10
-7／cm2 、放出効率（ダイオード電流に対する放出電流
比）は 0.7％であり、また放出電子のエネルギー分布は
半値幅 1.5eV程度の広がりをもっている。This MOS structure tunnel cathode is
When a voltage is applied between the extraction electrode layer 6 and the back electrode layer 7 so that at least the insulator layer 4 in the electron emission region does not cause dielectric breakdown, desired electrons are emitted from the surface of the electron emission electrode layer 5. . For example, the thickness of the insulator layer 4 is 11 nm, the thickness of the electron emission electrode layer 5 is 6 nm, and the plane area of the opening 3 is 2.5 × 10 −3 cm.
In the case of the element of No. 2 , the maximum applied voltage (the limit voltage at which the element does not break) is 10 V, and the discharge current density at that time is 6.8 × 10
-7 / cm 2 , emission efficiency (emission current ratio to diode current) is 0.7%, and the energy distribution of emitted electrons has a half-width of about 1.5 eV.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、従来の
ＭＯＳトンネル陰極には、実用上次のような不都合な問
題が認められる。However, the conventional MOS tunnel cathode has the following disadvantages in practical use.
【０００７】先ず、前記構成のＭＯＳトンネル陰極の構
成においては、電子放出部（領域）を成す開口部３の絶
縁体層４、たとえば熱酸化法で形成されたＳｉＯ2 層の
結晶性が非常に劣り、また、この絶縁体層４面上に形成
される電子放出電極層５も特性的に問題がある。つま
り、前記絶縁体層４は、たとえば熱酸化法やＣＶＤ法な
どによって形成し得るが、現状ではいずれの場合もアモ
ルファス状の酸化物層（絶縁体層）で、結晶性の良好な
酸化物層の形成は至難に等しい。したがって、前記アモ
ルファス状の酸化物層４面に（下地層）、積層・形成さ
れる電子放出電極層５も必然的に結晶性が劣っており、
微結晶ないしアモルファスに過ぎない。ところで、ＭＯ
Ｓトンネル陰極の放出電流密度を大きくするためには、
電子放出電極層５の下地層を成す絶縁体層４の厚みを薄
くし、印加電圧を大きく設定する必要がある。しかしな
がら、前記絶縁体層４は、アモルファス状の酸化物層で
絶縁耐圧が低いため、少くとも10nm程度の厚さを要求さ
れる一方、印加電圧も高く設定し得ない。したがって、
放出電流密度は一般的に低く、またトンネル電子が比較
的厚い絶縁体層４中や電子放出電極層５中での、トンネ
ル電子の拡散が多くなるため電子放出効率が低く、かつ
電子のエネルギー分布も広がったものとなる。こうし
た、不都合な問題は、高輝度，低分散，低雑音などの特
長が注目されながら、この種ＭＯＳトンネル陰極の実用
性に影響を及ぼしているといえる。First, in the structure of the MOS tunnel cathode having the above structure, the crystallinity of the insulator layer 4 of the opening 3 forming the electron emitting portion (region), for example, the SiO 2 layer formed by the thermal oxidation method is very high. Inferiority, and the electron emission electrode layer 5 formed on the surface of the insulator layer 4 also has a problem in characteristics. That is, the insulator layer 4 can be formed by, for example, a thermal oxidation method, a CVD method, or the like, but at present, in any case, the oxide layer is an amorphous oxide layer (insulator layer) and has an excellent crystallinity. Is very difficult to form. Therefore, the electron emission electrode layer 5 laminated / formed on the surface of the amorphous oxide layer 4 (base layer) is inevitably poor in crystallinity,
It is only microcrystalline or amorphous. By the way, MO
In order to increase the emission current density of the S tunnel cathode,
It is necessary to reduce the thickness of the insulator layer 4 forming the base layer of the electron emission electrode layer 5 and set the applied voltage to be large. However, since the insulator layer 4 is an amorphous oxide layer and has a low withstand voltage, a thickness of at least about 10 nm is required and the applied voltage cannot be set high. Therefore,
The emission current density is generally low, and the diffusion of tunnel electrons increases in the insulator layer 4 or the electron emission electrode layer 5 where tunnel electrons are relatively thick, resulting in low electron emission efficiency and electron energy distribution. Will also spread. It can be said that such an inconvenient problem affects the practicality of this type of MOS tunnel cathode while paying attention to the features such as high brightness, low dispersion, and low noise.
【０００８】本発明は上記事情に対処してなされたもの
で、良好な結晶性を有する絶縁体層および電子放出電極
層を具備し、高い電子放出効率および大放出電流密度を
得ることが可能な電子放出素子の提供を目的とする。The present invention has been made in view of the above circumstances and is provided with an insulator layer and an electron emission electrode layer having good crystallinity, and is capable of obtaining high electron emission efficiency and large emission current density. The purpose is to provide an electron-emitting device.
【０００９】[0009]
【課題を解決するための手段】本発明に係る電子放出素
子は、 IＶ族半導体およびIII-Ｖ族化合物半導体から選
ばれた素材から成る支持基板と、前記支持基板の少くと
も電子放出領域面に一体的に配置されたアルカリ土類フ
ッ化物絶縁層と、前記アルカリ土類フッ化物絶縁層上に
一体的に配置され、電子放出領域を形成する IＶ族半導
体およびIII-Ｖ族化合物半導体から選ばれた素材から成
る電子放出電極層とを具備して成ることを特徴とする。An electron-emitting device according to the present invention comprises a support substrate made of a material selected from a group IV semiconductor and a group III-V compound semiconductor, and an electron emission region surface of at least the support substrate. The alkaline earth fluoride insulating layer is integrally arranged, and is selected from the group IV semiconductor and the group III-V compound semiconductor which are integrally arranged on the alkaline earth fluoride insulating layer and form an electron emission region. And an electron emission electrode layer made of the same material.
【００１０】すなわち、本発明に係る電子放出素子は、
支持基板および電子放出電極層の構成材料として、 IＶ
族半導体およびIII-Ｖ族化合物半導体を選択し、ＳＩＳ
構造化する一方、電子放出に関与する領域の絶縁体層を
アルカリ土類フッ化物層とし、かつこの構成において始
めて、前記絶縁体層および電子放出電極層を、たとえば
ＭＢＥ法などによるエピタキシャル成長で形成し得るこ
とに着目して完成されたものである。That is, the electron-emitting device according to the present invention is
As a constituent material of the supporting substrate and the electron emission electrode layer, IV
Group III semiconductor and III-V group compound semiconductor are selected, and SIS
While structuring, the insulator layer in the region involved in electron emission is an alkaline earth fluoride layer, and for the first time in this structure, the insulator layer and the electron emission electrode layer are formed by epitaxial growth by, for example, the MBE method. It was completed with a focus on obtaining.
【００１１】そして、前記の IＶ族半導体としては、た
とえばＳｉ，Ｇｅ，Ｓｉ−Ｇｅ化合物半導体などが挙げ
られ、またIII-Ｖ族化合物半導体としては、たとえばＧ
ａＡｓ，ＧａＡｌＡｓ，ＩｎＰなどが挙げられる。ここ
で、Ｓｉなど IＶ族半導体の場合はＰ，Ａｓなどを、ま
たIII-Ｖ族化合物半導体の場合はＣ，Ｓなどをドーピン
グして電気伝導度を適宜変えてもよい。Examples of the group IV semiconductors include Si, Ge, and Si-Ge compound semiconductors, and examples of the group III-V compound semiconductors include G.
Examples include aAs, GaAlAs, InP and the like. Here, in the case of an IV group semiconductor such as Si, P, As, etc. may be doped, and in the case of a III-V group compound semiconductor, C, S, etc. may be doped to appropriately change the electric conductivity.
【００１２】さらに、絶縁層を成すアルカリ土類フッ化
物としては、たとえばＣａＦ2 ，ＢａＦ2 ，ＳｒＦ2 ，
Ｃａ0.5 Ｂａ0.5 Ｆ2 もしくはこれらの２種以上の混晶
などが挙げられる。Further, as the alkaline earth fluoride forming the insulating layer, for example, CaF 2 , BaF 2 , SrF 2 ,
Ca 0.5 Ba 0.5 F 2 or a mixed crystal of two or more of these may be used.
【００１３】[0013]
【作用】本発明に係る電子放出素子は、エピタキシャル
構造を有するＳＩＳトンネル陰極であり、従来のＭＯＳ
トンネル陰極の場合に較べて、電子放出電極層および電
子放出領域のトンネル層（下地層）を成すアルカリ土類
フッ化物絶縁層の結晶性がそれぞれ大幅に向上して、す
ぐれた耐電圧性を呈する。したがって、トンネル層を成
すアルカリ土類フッ化物絶縁層を薄くしても、高いバイ
アス電圧を印加し得ることになり、トンネル放出電流密
度を大幅に向上し得る。また前記良好な結晶性に伴なっ
て、電子散乱も軽減され、電子放出効率が向上するとと
もに、放出電子のエネルギー分散も小さく制御し得る。The electron-emitting device according to the present invention is an SIS tunnel cathode having an epitaxial structure, and has a conventional MOS structure.
Compared with the case of the tunnel cathode, the crystallinity of the alkaline earth fluoride insulating layer forming the electron emitting electrode layer and the tunnel layer (underlayer) of the electron emitting region is greatly improved, and excellent voltage resistance is exhibited. . Therefore, even if the alkaline earth fluoride insulating layer forming the tunnel layer is thinned, a high bias voltage can be applied, and the tunnel emission current density can be greatly improved. In addition to the good crystallinity, electron scattering is reduced, the electron emission efficiency is improved, and the energy dispersion of emitted electrons can be controlled to be small.
【００１４】[0014]
【実施例】以下図１および図２ (a)〜 (d)を参照して本
発明の実施例を説明する。EXAMPLES Examples of the present invention will be described below with reference to FIGS. 1 and 2A to 2D.
【００１５】実施例１ 図１は、本発明に係る電子放出素子の要部構成例を断面
的に示したもので、８は半導体系の支持基板、たとえば
ｎ型Ｓｉ単結晶基板、９は前記ｎ型Ｓｉ単結晶基板面に
設けられた絶縁体層、たとえば熱酸化法で形成されたＳ
ｉＯ2 層で開口部10を有している。また、11は前記Ｓｉ
Ｏ2 層９の開口によって露出したｎ型Ｓｉ単結晶基板８
面およびＳｉＯ2 層９面にエピタキシャル成長で形成さ
れたアルカリ土類フッ化物絶縁層、たとえばＣａＦ
2 層、12は前記開口部10領域およびその周辺部のＣａＦ
2 層11面にエピタキシャル成長で形成された半導体系の
電子放出電極層、たとえばＳｉから成る電子放出電極
層、13は前記電子放出電極層層12の引き出し電極、14は
ｎ型Ｓｉ単結晶基板８の裏面に形成された裏面電極層で
ある。Example 1 FIG. 1 is a cross-sectional view showing an example of the essential structure of an electron-emitting device according to the present invention, in which 8 is a semiconductor type supporting substrate, for example, an n-type Si single crystal substrate, and 9 is the above-mentioned substrate. An insulator layer provided on the surface of the n-type Si single crystal substrate, for example, S formed by a thermal oxidation method.
The iO 2 layer has an opening 10. Further, 11 is the Si
N-type Si single crystal substrate 8 exposed by the opening of the O 2 layer 9
Surface and SiO 2 layer 9 surface formed by epitaxial growth on an alkaline earth fluoride insulating layer such as CaF
2 layers and 12 are CaF in the opening 10 area and its peripheral area
A semiconductor type electron emission electrode layer formed by epitaxial growth on the surface of the second layer 11, for example, an electron emission electrode layer made of Si, 13 an extraction electrode of the electron emission electrode layer 12, and 14 an n-type Si single crystal substrate 8. It is a back electrode layer formed on the back surface.
【００１６】次に、前記構成の電子放出素子の製造例に
ついて説明する。図２ (a)〜 (d)は、製造プロセスの態
様を模式的に示したもので、先ずｎ型Ｓｉ単結晶基板８
を用意し、常套的な熱酸化法によって所定の面に、図２
(a)に断面的に示すごとく、厚さ 500nm程度のＳｉＯ2
層９を形成する。次いで、図２ (b)に断面的に示すよう
に、前記形成したＳｉＯ2 層９をフォトリソグラフィー
によって一部切除し、たとえば一辺が 500nmの正方形の
電子放出部を成す開口部10を設ける。その後、前記電子
放出部を成す開口部10を設けたｎ型Ｓｉ単結晶基板８に
対して、10-9Torr程度の真空中、ｎ型Ｓｉ単結晶基板８
を約 600℃に加熱した状態で、ＭＢＥ法によって、図２
(c)に断面的に示すごとく、厚さ約 8nmのＣａＦ2 層11
をエピタキシャル成長させる。Next, a manufacturing example of the electron-emitting device having the above structure will be described. 2 (a) to 2 (d) schematically show aspects of the manufacturing process. First, the n-type Si single crystal substrate 8 is formed.
2 is prepared by a conventional thermal oxidation method on a predetermined surface, as shown in FIG.
As shown in cross section in (a), SiO 2 with a thickness of about 500 nm
Form the layer 9. Next, as shown in a sectional view in FIG. 2B, the SiO 2 layer 9 thus formed is partially removed by photolithography, and an opening 10 is formed, which forms a square electron emitting portion having a side of 500 nm, for example. After that, the n-type Si single crystal substrate 8 in a vacuum of about 10 −9 Torr with respect to the n-type Si single crystal substrate 8 provided with the opening 10 forming the electron emitting portion.
2 is heated by the MBE method while being heated to about 600 ° C.
As shown in cross section in (c), CaF 2 layer with a thickness of about 8 nm 11
Are grown epitaxially.
【００１７】次いで、上記なＣａＦ2 層11を形成したｎ
型Ｓｉ単結晶基板８を約 700℃に加熱した状態下、ＭＢ
Ｅ法により図２ (d)に断面的に示すごとく、前記開口部
10を被覆するように、ＣａＦ2 層11面上に電子放出電極
層12を形成するＳｉ層を、約6nm程度の厚さに選択的に
成長させる。その後、たとえばシャドウマスクを用い
て、前記開口部10以外の領域面に引き出し電極13を形成
するＡｌ層を、約 1μm程度厚に蒸着法で選択的に形成
する一方、さらにｎ型Ｓｉ単結晶基板８の裏面にも、裏
面電極層14を成すＡｌ層を約 1μm 程度厚に蒸着法で形
成することにより、前記図１に示す構造の電子放出素子
が得られる。Then, the above-mentioned CaF 2 layer 11 was formed.
Type Si single crystal substrate 8 is heated to about 700 ° C, MB
As shown in cross section in FIG. 2 (d) by the E method, the opening is
A Si layer for forming the electron emission electrode layer 12 is selectively grown on the surface of the CaF 2 layer 11 so as to cover 10 with a thickness of about 6 nm. Thereafter, for example, by using a shadow mask, an Al layer for forming the extraction electrode 13 is selectively formed to a thickness of about 1 μm on the surface of the region other than the opening 10 by a vapor deposition method, and further, an n-type Si single crystal substrate is formed. An electron-emitting device having the structure shown in FIG. 1 can be obtained by forming an Al layer forming the back electrode layer 14 to a thickness of about 1 μm on the back surface of the electrode 8 by vapor deposition.
【００１８】この製造工程において、ＳｉＯ2 層９面上
に形成されるＣａＦ2 層11および電子放出電極層12を形
成するＳｉ層は多結晶であったが、前記開口部10の形成
で露出したｎ型Ｓｉ単結晶基板８面（電子放出領域面）
に成長されるＣａＦ2 層11および電子放出電極層12を形
成するＳｉ層は、高速反射電子線回折による観察から、
ともにエピタキシャル構造てることが確認された。In this manufacturing process, the CaF 2 layer 11 formed on the surface of the SiO 2 layer 9 and the Si layer forming the electron emission electrode layer 12 were polycrystalline, but were exposed by the formation of the opening 10. N-type Si single crystal substrate 8 surface (electron emission area surface)
The Si layer forming the CaF 2 layer 11 and the electron emission electrode layer 12 grown on the
It was confirmed that both had an epitaxial structure.
【００１９】上記構成された電子放出素子を、 1×10-6
Torrの真空下に設置する一方、この電子放出素子の電子
放出領域に対向させて陽極を配置した。この配置・構成
において、陽極電圧を電子放出素子に対し＋100Vとし、
電子放出素子の引き出し電極13と裏面電極14との間に電
圧を印加したところ、最大印加電圧は 10.5Vで、このと
きの放出電流密度は 6.0×10-6A/cm2 、電子放出効率は
0.8％であった。また、放出電子のエネルギー分布を電
子分光器で測定した結果は、半値幅 1.1eV程度の分布で
あった。The electron-emitting device configured as described above is replaced with 1 × 10 −6
The anode was placed facing the electron emission region of this electron emission device while being placed under the vacuum of Torr. In this arrangement / configuration, the anode voltage is + 100V with respect to the electron-emitting device,
When a voltage was applied between the extraction electrode 13 and the back electrode 14 of the electron-emitting device, the maximum applied voltage was 10.5 V, the emission current density at this time was 6.0 × 10 -6 A / cm 2 , and the electron emission efficiency was
It was 0.8%. In addition, the energy distribution of the emitted electrons was measured by an electron spectroscope, and the half-width was about 1.1 eV.
【００２０】この実施例の場合は、電子放出領域部の絶
縁体層（トンネル絶縁体層）の厚さを、従来の電子放出
素子の場合に較べて薄く設定しても、同等程度の電圧を
印加することができ、その結果、放出電流密度を 6.8×
10-7A/cm2 （従来例）から、6.0×10-6A/cm2 と約 9倍
と大幅向上が達成されている。また、電子放出効率も0.
7％（従来例）から 0.8％に向上し、さらにエネルギー
の分散も半値幅 1.5eV（従来例）から 1.1eVと向上して
いる。In the case of this embodiment, even if the thickness of the insulator layer (tunnel insulator layer) in the electron emission region is set to be smaller than that of the conventional electron-emitting device, an equivalent voltage is obtained. Can be applied, resulting in an emission current density of 6.8 ×
From 10 -7 A / cm 2 (conventional example) to 6.0 × 10 -6 A / cm 2 , a significant improvement of about 9 times. Also, the electron emission efficiency is 0.
It has improved from 7% (conventional example) to 0.8%, and the energy dispersion has also improved from a half-value width of 1.5eV (conventional example) to 1.1eV.
【００２１】実施例２ この実施例は、本発明に係る電子放出素子の他の構造例
を示すもので、基本的には実施例１の場合と同様であ
り、図１において８はｎ型ＧａＡｓ単結晶基板、９は前
記ｎ型ＧａＡｓ単結晶基板面に設けられた絶縁体層とし
てのＳｉ3 Ｎ4 層で開口部10を有している。また、11は
前記Ｓｉ3 Ｎ4 層９の開口によって露出したｎ型ＧａＡ
ｓ単結晶基板８面やＳｉ3 Ｎ4 層９面にエピタキシャル
成長で形成されたアルカリ土類フッ化物絶縁層、たとえ
ばＣａ0.5 Ｂａ0.5 Ｆ2 層、12は前記開口部10領域およ
びその周辺部のＣａ0.5 Ｂａ0.5 Ｆ2 層11面にエピタキ
シャル成長で形成された半導体系の電子放出電極層、た
とえばＧａＡｓから成る電子放出電極層、13は前記電子
放出電極層層12の引き出し電極、14はｎ型ＧａＡｓ単結
晶基板８の裏面に形成された裏面電極層である。Example 2 This example shows another structural example of the electron-emitting device according to the present invention, which is basically the same as the case of Example 1, and 8 in FIG. 1 is n-type GaAs. A single crystal substrate 9 is an Si 3 N 4 layer as an insulating layer provided on the surface of the n-type GaAs single crystal substrate, and has an opening 10. Further, 11 is n-type GaA exposed by the opening of the Si 3 N 4 layer 9.
s An alkaline earth fluoride insulating layer formed by epitaxial growth on the surface of the single crystal substrate 8 or the surface of the Si 3 N 4 layer, for example, a Ca 0.5 Ba 0.5 F 2 layer, and 12 are Ca in the opening 10 region and its peripheral portion. 0.5 Ba 0.5 F 2 layer A semiconductor-based electron emission electrode layer formed by epitaxial growth on the 11 surface, for example, an electron emission electrode layer made of GaAs, 13 an extraction electrode of the electron emission electrode layer 12, and 14 an n-type GaAs single layer. A back electrode layer formed on the back surface of the crystal substrate 8.
【００２２】そして、前記構成の電子放出素子は次のよ
うにして製造例できる。すなわち、前記実施例１の場合
に準じた製造プロセスで製造し得る。先ずｎ型ＧａＡｓ
単結晶基板８を用意し、約60℃に加熱保持されたＨ2 Ｓ
Ｏ4 ：Ｈ2 Ｏ2 ：Ｈ2 Ｏ＝ 8： 1： 1の混合溶液中に、
1分間浸漬してエッチング処理してから、真空中 570℃
にて加熱し表面清浄化した。この清浄化面にＣＶＤ法
で、図２ (a)に断面的に示すごとく、厚さ 500nm程度の
Ｓｉ3 Ｎ4 層９を形成する。次いで、図２ (b)に断面的
に示すように、前記形成したＳｉ3 Ｎ4 層９をフォトリ
ソグラフィーによって一部切除し、たとえば一辺が 500
nmの正方形の電子放出部を成す開口部10を設ける。その
後、前記電子放出部を成す開口部10を設けたｎ型ＧａＡ
ｓ単結晶基板８に対して、10-9Torr程度の真空中、ｎ型
ＧａＡｓ単結晶基板８を約 600℃に加熱した状態で、Ｍ
ＢＥ法によって、図２ (c)に断面的に示すごとく、厚さ
約10nmのＣａ0.5 Ｂａ0.5 Ｆ2 層11をエピタキシャル成
長させる。このＣａ0.5 Ｂａ0.5 Ｆ2 層11のエピタキシ
ャル成長は、ＣａＦ2 の分子ビームとＢａＦ2 の分子ビ
ームとのビーム圧が 1： 1となるように制御しして同時
に照射することによりなし得る。The electron-emitting device having the above structure can be manufactured as follows. That is, it can be manufactured by the manufacturing process according to the case of the first embodiment. First, n-type GaAs
A single crystal substrate 8 is prepared, and H 2 S heated and held at about 60 ° C.
In a mixed solution of O 4 : H 2 O 2 : H 2 O = 8: 1: 1,
Immerse for 1 minute and etch, then in vacuum at 570 ℃
The surface was cleaned by heating at. On the cleaned surface, a Si 3 N 4 layer 9 having a thickness of about 500 nm is formed by the CVD method as shown in a sectional view in FIG. Next, as shown in a sectional view in FIG. 2B, the formed Si 3 N 4 layer 9 is partially cut off by photolithography, and for example, one side is 500
An opening 10 that forms a square electron emission portion of nm is provided. After that, an n-type GaA having an opening 10 forming the electron emitting portion is provided.
The n-type GaAs single crystal substrate 8 is heated to about 600 ° C. in a vacuum of about 10 −9 Torr with respect to the s single crystal substrate 8.
As shown in a sectional view in FIG. 2C, a Ca 0.5 Ba 0.5 F 2 layer 11 having a thickness of about 10 nm is epitaxially grown by the BE method. The Ca 0.5 Ba 0.5 F 2 layer 11 can be epitaxially grown by controlling the beam pressures of the CaF 2 molecular beam and the BaF 2 molecular beam to be 1: 1 and performing simultaneous irradiation.
【００２３】次いで、上記なＣａ0.5 Ｂａ0.5 Ｆ2 層11
を形成したｎ型ＧａＡｓ単結晶基板８を約 700℃に加熱
した状態下、 3kVの電子線を開口部10に照射しながら、
Ａｓのビームを約10分間、ｎ型ＧａＡｓ単結晶基板８に
照射した。その後、ＭＢＥ法により、電子放出電極層12
を成すＧａＡｓ層を約 6nm程度の厚さに、前記開口部10
を被覆するように、Ｃａ0.5 Ｂａ0.5 Ｆ2 層11面上に選
択的に成長させる。その後、シャドウマスクを用いて、
前記開口部10以外の領域面に引き出し電極13を形成する
Ａｌ層を、約 1μm 程度厚に蒸着法で選択的に形成する
一方、さらにｎ型ＧａＡｓ単結晶基板８の裏面にも、裏
面電極層14を成すＡｌ層を約 1μm 程度厚に蒸着法で形
成することにより、前記図１に示す構造の電子放出素子
が得られる。Then, the above Ca 0.5 Ba 0.5 F 2 layer 11 is formed.
While the n-type GaAs single crystal substrate 8 on which is formed is heated to about 700 ° C., while irradiating the opening 10 with an electron beam of 3 kV,
The n-type GaAs single crystal substrate 8 was irradiated with the As beam for about 10 minutes. After that, the electron emission electrode layer 12 is formed by the MBE method.
The GaAs layer forming the
Is selectively grown on the surface of the Ca 0.5 Ba 0.5 F 2 layer 11 so as to cover the layer. After that, using a shadow mask,
An Al layer for forming the extraction electrode 13 is selectively formed on the surface of the region other than the opening 10 to a thickness of about 1 μm by a vapor deposition method, and a back electrode layer is also formed on the back surface of the n-type GaAs single crystal substrate 8. By forming the Al layer forming 14 to a thickness of about 1 μm by a vapor deposition method, the electron-emitting device having the structure shown in FIG. 1 can be obtained.
【００２４】この製造工程において、Ｓｉ3 Ｎ4 層９面
上に形成されるＣａ0.5 Ｂａ0.5 Ｆ2 層11および電子放
出電極層12を形成するＧａＡｓ層は多結晶であったが、
前記開口部10の形成で露出したｎ型ＧａＡｓ単結晶基板
８面（電子放出領域面）に成長されるＣａ0.5 Ｂａ0.5
Ｆ2 層11および電子放出電極層12を形成するＧａＡｓ層
は、高速反射電子線回折による観察から、ともにエピタ
キシャル構造であることが確認された。In this manufacturing process, the Ca 0.5 Ba 0.5 F 2 layer 11 formed on the surface of the Si 3 N 4 layer 9 and the GaAs layer forming the electron emission electrode layer 12 were polycrystalline,
Ca 0.5 Ba 0.5 grown on the surface (electron emission area surface) of the n-type GaAs single crystal substrate 8 exposed by the formation of the opening 10.
The GaAs layers forming the F 2 layer 11 and the electron emission electrode layer 12 were both confirmed to have an epitaxial structure by observation by high speed reflection electron beam diffraction.
【００２５】また、上記構成された電子放出素子を 1×
10-6Torrの真空下に設置する一方、この電子放出素子の
電子放出領域に対向させて陽極を配置した。この配置・
構成において、陽極電圧を電子放出素子に対し＋100Vと
し、電子放出素子の引き出し電極13と裏面電極14との間
に電圧を印加したところ、最大印加電圧は 16Vで、この
ときの放出電流密度は 4.8×10-6A/cm2 、電子放出効率
は 0.7％であった。また、放出電子のエネルギー分布を
電子分光器で測定した結果は、半値幅 1.0eV程度の分布
であった。Further, the electron-emitting device having the above structure is
While being placed under a vacuum of 10 −6 Torr, an anode was placed facing the electron emission region of this electron emission device. This arrangement
In the configuration, when the anode voltage was +100 V with respect to the electron-emitting device and a voltage was applied between the extraction electrode 13 and the back electrode 14 of the electron-emitting device, the maximum applied voltage was 16 V, and the emission current density at this time was 4.8. × 10 -6 A / cm 2 , The electron emission efficiency was 0.7%. The energy distribution of the emitted electrons was measured by an electron spectroscope, and it was a distribution with a half-value width of about 1.0 eV.
【００２６】この実施例の場合は、電子放出領域部の絶
縁体層（トンネル絶縁体層）の厚さを、従来の電子放出
素子の場合と同じく10nmに設定しても、 1.6倍程度の電
圧を印加することができ、その結果、放出電流密度を
6.8×10-7A/cm2 （従来例）から、 4.8×10-6A/cm2 と
約 7倍と大幅向上が達成されている。また、電子放出効
率も同等程度であり、さらにエネルギーの分散も半値幅
1.5eV（従来例）から 1.0eVと向上している。In the case of this embodiment, even if the thickness of the insulator layer (tunnel insulator layer) in the electron emission region is set to 10 nm as in the case of the conventional electron-emitting device, the voltage of about 1.6 times is obtained. Can be applied, and as a result, the emission current density
From 6.8 × 10 -7 A / cm 2 (conventional example), 4.8 × 10 -6 A / cm 2 was achieved, a significant improvement of about 7 times. In addition, the electron emission efficiency is about the same, and the energy dispersion is at half maximum.
It has improved from 1.5eV (conventional example) to 1.0eV.
【００２７】なお、本発明は上記実施例に限定されるも
のでなく、本発明の主旨を逸脱しない範囲でいろいろ変
形して実施し得る。たとえば、前記実施例では、前記の
IＶ族系半導体としてＳｉ単結晶を用いたが，Ｇｅ，Ｓ
ｉ−Ｇｅ系などを用いてもよいし、また、III-Ｖ族化合
物半導体としてＧａＡｓ単結晶を用いたが，，ＧａＡｌ
Ａｓ，ＩｎＰなどを用いることも可能である。ここで、
Ｓｉなど IＶ族系半導体の場合はＰ，Ａｓなどを、また
III-Ｖ族化合物半導体の場合はＣ，Ｓなどをドーピング
して電気伝導度を適宜変えてもよい。さらに、アルカリ
土類フッ化物としては、上記ではＣａＦ2 ，Ｃａ0.5 Ｂ
ａ0.5 Ｆ2 の使用例を示したが、その他ＢａＦ2 ，Ｓｒ
Ｆ2 などを用いてもよく，さらにこれらアルカリ土類フ
ッ化物は２種以上の混晶などの形でも使用し得る。The present invention is not limited to the above embodiments, and various modifications may be made without departing from the spirit of the present invention. For example, in the embodiment described above,
Although Si single crystal was used as the IV group semiconductor, Ge, S
An i-Ge system or the like may be used, and a GaAs single crystal is used as a III-V group compound semiconductor.
It is also possible to use As, InP or the like. here,
In the case of group IV semiconductors such as Si, P, As, etc.
In the case of a III-V compound semiconductor, C, S or the like may be doped to change the electric conductivity as appropriate. Further, as the alkaline earth fluoride, CaF 2 , Ca 0.5 B is used in the above.
Although an example of using a 0.5 F 2 is shown, other BaF 2 , Sr
F 2 or the like may be used, and these alkaline earth fluorides may be used in the form of a mixed crystal of two or more kinds.
【００２８】[0028]
【発明の効果】本発明に係る電子放出素子は、電子放出
基材として IＶ族系半導体やIII-Ｖ族化合物半導体を用
い、また電子放出領域の絶縁体層をアルカリ土類フッ化
物で、さらに電子放出電極層を IＶ族系半導体やIII-Ｖ
族化合物半導体で、かつ電子放出領域の絶縁体層および
電極層をエピタキシャル成長で形成した構成を特に採っ
ている。そして、このような構成の選択により、従来の
場合と同等の印加電圧でも放出電流密度の大幅な増加
（向上）を図り得るし、また電子放出領域の絶縁体層お
よび電極層は、ともに良好な結晶性を有するので、電子
の散乱が軽減され、放出効率が向上するばかりでなく、
さらに放出電子エネルギーの分散も低減される。つま
り、本発明に係る電子放出素子は、従来この種の電子放
出素子において実用上問題視されていた事項を、大幅に
解消ないし改善し、その実用化の推進に大きく寄与する
ものといえる。The electron-emitting device according to the present invention uses an IV group semiconductor or a III-V group compound semiconductor as the electron-emitting substrate, and the insulator layer in the electron-emitting region is made of alkaline earth fluoride. The electron emission electrode layer may be a group IV semiconductor or III-V
A structure in which an insulator layer and an electrode layer in the electron-emitting region are formed by epitaxial growth, which is a group compound semiconductor, is particularly adopted. By selecting such a configuration, the emission current density can be significantly increased (improved) even with an applied voltage equivalent to that in the conventional case, and the insulator layer and the electrode layer in the electron emission region are both excellent. Since it has crystallinity, the scattering of electrons is reduced, and not only the emission efficiency is improved, but
Furthermore, the dispersion of emitted electron energy is also reduced. That is, it can be said that the electron-emitting device according to the present invention largely eliminates or improves the matters which have been regarded as a practical problem in the conventional electron-emitting device of this type, and greatly contributes to the promotion of its practical use.
【図１】本発明に係る電子放出素子の構成例の要部を示
す断面図。FIG. 1 is a sectional view showing a main part of a configuration example of an electron-emitting device according to the present invention.
【図２】本発明に係る電子放出素子の製造例における実
施態様を模式的に示すもので、(a)は支持基板面に絶縁
体層を形成した状態を示す断面図、 (b)は絶縁体層の所
定領域を選択的に除去し開口した状態を示す断面図、
(c)は開口により露出した支持基板の電子放出領域面を
含む領域に絶縁層としてエピタキシャルなアルカリ土類
フッ化物層を設けた状態を示す断面図、 (d)は電子放出
領域の絶縁層面に電子放出電極層を形成した状態を示す
断面図。FIG. 2 is a schematic view showing an embodiment in a manufacturing example of an electron-emitting device according to the present invention, (a) is a sectional view showing a state in which an insulating layer is formed on the surface of a supporting substrate, and (b) is an insulating film. Sectional view showing a state in which a predetermined region of the body layer is selectively removed and opened,
(c) is a cross-sectional view showing a state in which an epitaxial alkaline earth fluoride layer is provided as an insulating layer in a region including the electron emission region surface of the supporting substrate exposed by the opening, (d) is an insulating layer surface of the electron emission region. Sectional drawing which shows the state which formed the electron emission electrode layer.
【図３】従来の電子放出素子の製造例における実施態様
を模式的に示すもので、 (a)は支持基板面に絶縁体層を
形成した状態を示す断面図、 (b)は絶縁体層の所定領域
を選択的に除去し開口した状態を示す断面図、 (c)は開
口により露出した支持基板の電子放出領域面に熱酸化に
より酸化物層を設けた状態を示す断面図、 (d)は電子放
出領域の絶縁層面に電子放出電極層を形成した状態を示
す断面図、 (e)は電子放出電極層の引き出し電極層およ
び裏面電極層をそれぞれ形成した状態を示す断面図。FIG. 3 schematically shows an embodiment in a conventional electron-emitting device manufacturing example, in which (a) is a cross-sectional view showing a state where an insulating layer is formed on the surface of a supporting substrate, and (b) is an insulating layer. A cross-sectional view showing a state in which a predetermined region is selectively removed and opened, (c) is a cross-sectional view showing a state in which an oxide layer is provided on the electron emission region surface of the supporting substrate exposed by the opening by thermal oxidation, (d) 6A is a cross-sectional view showing a state in which an electron-emission electrode layer is formed on an insulating layer surface of an electron-emission region, and FIG. 8E is a cross-sectional view showing a state in which an extraction electrode layer and a back surface electrode layer of the electron emission electrode layer are respectively formed.
１，８…支持基板 ２，９…絶縁体層 ３，10…開
口部 ４…電子放出領域の絶縁体層 ５…電子放出
電極層 ６，13…引き出し電極層 ７，14…裏面電
極層 11…アルカリ土類フッ化物絶縁層 12…エピ
タキシャルな半導体系の電子放出電極層1, 8 ... Support substrate 2, 9 ... Insulator layer 3, 10 ... Opening part 4 ... Insulator layer in electron emission region 5 ... Electron emission electrode layer 6, 13 ... Extraction electrode layer 7, 14 ... Back electrode layer 11 ... Alkaline earth fluoride insulating layer 12 ... Epitaxial semiconductor-based electron emission electrode layer
Claims (1)
体から選ばれた素材から成る支持基板と、 前記支持基板の少くとも電子放出領域面に一体的に配置
されたアルカリ土類フッ化物絶縁層と、 前記アルカリ土類フッ化物絶縁層上に一体的に配置さ
れ、電子放出領域を形成する IＶ族半導体およびIII-Ｖ
族化合物半導体から選ばれた素材から成る電子放出電極
とを具備して成ることを特徴とする電子放出素子。1. A supporting substrate made of a material selected from a group IV semiconductor and a group III-V compound semiconductor, and an alkaline earth fluoride insulating layer integrally disposed on at least an electron emission region surface of the supporting substrate. And an IV-group semiconductor and III-V which are integrally disposed on the alkaline earth fluoride insulating layer and form an electron emission region.
An electron-emitting device comprising an electron-emitting electrode made of a material selected from a group compound semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19575493A JP3260502B2 (en) | 1993-08-06 | 1993-08-06 | Electron-emitting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19575493A JP3260502B2 (en) | 1993-08-06 | 1993-08-06 | Electron-emitting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0757619A true JPH0757619A (en) | 1995-03-03 |
| JP3260502B2 JP3260502B2 (en) | 2002-02-25 |
Family
ID=16346412
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|---|---|---|---|
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| Country | Link |
|---|---|
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000074098A1 (en) * | 1999-05-28 | 2000-12-07 | Hitachi, Ltd. | Thin-film electron source, display and device |
| JP2008123743A (en) * | 2006-11-09 | 2008-05-29 | Nippon Telegr & Teleph Corp <Ntt> | Electron emission element |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006064634A1 (en) * | 2004-12-17 | 2006-06-22 | Pioneer Corporation | Electron discharge element and manufacturing method thereof |
-
1993
- 1993-08-06 JP JP19575493A patent/JP3260502B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000074098A1 (en) * | 1999-05-28 | 2000-12-07 | Hitachi, Ltd. | Thin-film electron source, display and device |
| US6818941B1 (en) | 1999-05-28 | 2004-11-16 | Hitachi, Ltd. | Thin film electron emitter, display device using the same and applied machine |
| KR100689919B1 (en) * | 1999-05-28 | 2007-03-09 | 가부시키가이샤 히타치세이사쿠쇼 | Thin-film electron source, display and device |
| JP2008123743A (en) * | 2006-11-09 | 2008-05-29 | Nippon Telegr & Teleph Corp <Ntt> | Electron emission element |
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| JP3260502B2 (en) | 2002-02-25 |
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