JPH0757499A - Test method for electrical characteristic of semiconductor memory and device therefor - Google Patents

Abstract

PURPOSE:To avoid that a test time is affected by dispersion of responsiveness of a device and to shorten a test time for verifying writing data by discriminating whether writing data is performed within an allowable time or not in plural semiconductor memories. CONSTITUTION:When aging is performed in a EEPROM, many EEPROMs 2 being an object of aging are mounted in freely attachably and detachably, these are connected in parallel each other. After these groups connected to a testing section, a power supply is turned on by a command of a CPU, and a clock signal and a reset signal are made in an 'H' level. After that, an address is cleared and counted by a retry counter 27, successively, a writing command is set by an ALPG 24 and data are simultaneously written by a driving section 21, a verify command is set, and the command is performed. Next, a response signals are inputted to each time comparator 23 any time, an allowable time from an allowable time register 22 is compared with response signals from each ROM, and it is discriminated whether this time is within an allowable time or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for inspecting electrical characteristics of a semiconductor memory device (hereinafter, sometimes referred to as a memory), and more particularly to a data write verify inspecting technique for confirming a data write operation of a memory.
EEPROM (Electrically Erasa)
ble Programmable ROM), and an aging technique for an arithmetic processing device having an EEROM as an internal memory or an external memory.

[0002]

2. Description of the Related Art Generally, an EEPROM has a different data writing time for each device. Also, EEP
In the ROM, writing to the cell of the same address may not be normally performed at one time.
Rewriting (retry) processing may be executed several times to several tens of times. Therefore, in the data write verify test of the EEPROM, the data write verify test process is required for each device. The same applies to arithmetic processing units (microcomputers, microprocessor units, central processor units, etc.) having an EEPROM as an internal memory or an external memory.

Therefore, in the conventional data write-verify test of an EEPROM or an arithmetic processing unit (hereinafter referred to as an EEPROM device) equipped with the EEPROM, each EE is checked by an expensive LSI memory tester.
The data write verify check is executed for each PROM device.

An example of a memory tester described is "Electronic Materials 1989" published by Kogyo Kenkyukai Co., Ltd.
Issue, November issue, issued on November 10, 1989, P141
There is ~ P147.

[0005]

In the conventional data write verify test of the EEPROM device,
Since an expensive LSI tester is used and tested one by one for each EEPROM device, there is a problem that a long time is consumed for testing and workability is deteriorated.

Therefore, it is conceivable that a large number of data write-verify tests of the EEPROM device are executed at the same time. In this case, however, the present inventor has clarified the following problems. (1) Since the writing time of data in the EEPROM varies greatly from device to device, the strobe signal setting time must be set to the maximum value of the fluctuation.
The testing time becomes long. (2) If the number of retries that can be performed is ignored and a large number of tests are performed at the same time, the product yield decreases. (3) When the processing speed or the processing flow is different for each device, it is not possible to perform a large number of inspections at the same time.

An object of the present invention is to provide a technique for inspecting the electrical characteristics of a semiconductor memory device, which can test a large number of devices simultaneously and shorten the testing time.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The typical ones of the inventions disclosed in the present application will be outlined below.

That is, in a method of inspecting electrical characteristics of a semiconductor memory device in which a data write verify test is performed on a semiconductor memory device, after a data write verify test is simultaneously performed on a plurality of semiconductor memory devices, respectively. , It is compared whether or not the input timing of the response signal from each semiconductor memory device is within the allowable time, and the semiconductor memory device which is not within the allowable time is designated,
The semiconductor memory device designated is controlled differently from the semiconductor memory device not designated.

[0011]

According to the above-mentioned means, when simultaneously performing the data write verify test on a plurality of semiconductor memory devices, it is determined whether the data write is performed within the allowable time among the plurality of semiconductor memory devices. By making the determination, it is possible to prevent the inspection time from being influenced by variations in the responsiveness of the semiconductor memory device, so that the data write verify inspection time of the semiconductor memory device can be shortened.

Since the data write verify test can be simultaneously performed on a plurality of semiconductor memory devices, the workability of the data write verify test can be greatly improved.

When the data write verify test is retried for a plurality of semiconductor memory devices, the data write verify test is retried under the same condition, so that it is not necessary to change the write condition or the verify condition for each retry. Therefore, it is possible to suppress an increase in testing time and testing cost.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an EEPROM which is an embodiment of the present invention.
FIG. 3 is a block diagram showing a data write verify inspection device for a device. FIG. 2 is an embodiment of the present invention EE
7 is a flowchart showing a data write verify inspection method for a PROM device. FIG. 3 is a timing waveform diagram at the time of the data write verify inspection.

In this embodiment, the electrical characteristic inspection device for a semiconductor memory device according to the present invention is configured as a data write verify device for an EEPROM device that carries out a data write verify inspection method for an EEPROM device. EEP as inspection object
ROM device (hereinafter sometimes referred to as DUT)
Is a microcomputer having an EEPROM as an internal memory and is used, for example, in a so-called IC card.

In the present embodiment, the EEPROM
A device data write verify inspection apparatus and method is used to perform an aging method for an EEPROM device that is a DUT. When performing the aging method, a large number of EEPROM devices (DUT) 2 as objects to be aged, It is removably attached to an aging board (not shown) through each socket. Each DUT2 mounted on the aging board
Are electrically connected to the testing unit in parallel with each other via a connector group.

On the other hand, the data write verify inspection device 20 according to the present embodiment is provided with an aging device (not shown).
It is configured to be detachably attached to the testing part of the device via a testing board. The testing board is electrically connected to a central processing unit (not shown), and the CPU is constructed so as to integrally control each component on the testing board. .

This data write verify inspection apparatus 20 includes a DUT drive section 21 and an allowable time register 22.
A time comparator 23 group, an expected value generator 24, a signal comparator 25 group, an allowable retry count register 26, a retry counter group 27, a count comparator 28 group, and a defective DUT information latch circuit 29 group. And a control unit 30.

The DUT drive unit 21 is electrically connected to each DUT 2 ... And is configured to drive and control each DUT 2.

The allowable time of the data write verify check is registered in advance in the allowable time register 22.
.. is configured to be inputted to one input terminal of each time comparator 23. Here, the permissible time is a time within which the testing time can be ensured most efficiently within the range where the testing time is not extended in the data write verify inspection, and for example, the data writing time of the DUT is The optimum value is obtained and determined in advance by the average value or the deviation value with respect to the variation.

The group of time comparators 23 is prepared in advance corresponding to the group of DUT2, and one input terminal of each time comparator 23 ... Is connected to each DUT2. . The time comparator 23 compares the input timing of the output signal from the DUT 2 with the permissible time signal from the permissible time register 22 to determine whether the timing of the output signal of the DUT 2 is within the permissible time. It is configured.

The expected value signal generator 24 uses an algorithmic pattern generator (ALPG), and the expected value signal generator (hereinafter sometimes referred to as ALPG) 24 is applied to the EEPROM device 2 which is a DUT. Address signals, data signals (including expected values and commands), and signals for controlling the EEPROM device 2 (out enable signals, word enable signals, etc.). These signals are selected in advance in accordance with the electrical characteristic inspection conditions and aging conditions for the EEPROM device 2,
It is stored in the memory of ALPG24.

Then, one output terminal of the ALPG 24 is DU
Each of the EEPROM devices 2 as T is electrically connected in parallel via a DUT drive unit 21, and the various signals described above are stored in the EEPROM.
It is designed to transmit to each of the devices 2 at the same time. Further, the ALPG 24 is electrically connected to each of the signal comparators 25 ... At another output terminal,
An expected value signal is transmitted to each of the signal comparators 25 ... Incidentally, the expected value signal is a signal that expects a preset predetermined action and may be considered to be equal to the data signal.

The signal comparator 25 includes the expected value signal from the ALPG 24 and the output signal of each cell to be inspected which is sent from each EEPROM device 2 ... Through each time comparator 23. Are configured to be compared with each other to determine pass / fail. That is, the signal comparator 25 determines that the output signal from each inspection target cell is good when the output signal matches the expected value signal, and determines the defect when the output signal is different from the expected value signal.

Further, each of the signal comparators 25 ... Is electrically connected to each of the retry counters 27, and the determination result is transmitted to each of the retry counters 27. The retry counter 27 is configured to count the current number of retries based on the determination result transmitted from the signal comparator 25 and hold the counted value. Each retry counter 27 ... Is configured to count the current number of retries and transmit the count value to each number comparator 28. The number of times comparator 28 is configured to compare the count value with a preset value set in the allowable retry number register 26 and send the comparison result to the defective DUT information latch circuit 29.

The value preset in the allowable retry count register 26 is a value set based on the guaranteed practical retry count for the EEPROM device 2, and is the maximum retry count value allowed for the inspection.

The time comparator 2 is connected to each input terminal of the control unit 30.
The third group, the signal comparator 25 group, and the frequency comparator 28 group are respectively connected, and the ALPG 24 and the DUT drive unit 21 are respectively connected to the two output terminals of the control unit 30. The control unit 30 controls the comparators 25, 28, 30.
The ALPG 24 and the DUT drive unit 21 are configured to be controlled respectively based on the comparison result of 1.

Next, the operation of the data write verifying apparatus for the EEPROM device according to the above configuration will be described to explain the data write verifying method for the EEPROM device according to one embodiment of the present invention with reference to FIGS. 2 and 3. .

In carrying out the aging method of the EEPROM device, a large number of EEPROM devices 2 as objects to be aged are detachably mounted on the aging board through the respective sockets. The respective EEPROM devices 2 mounted on the aging board are connected to the testing section in parallel with each other.

When the testing unit is started by a command from the CPU after the EEPROM device 2 group is connected to the testing unit, the power is turned on, the clock signal is output, and the reset signal is at the Hi level.

Next, the address is cleared and the current number of times of the retry counter 27 is incremented by one.

Subsequently, a write command is set by the ALPG 24, and data is simultaneously written by the DUT drive section 21 to each cell at a predetermined address designated by the ALPG 24 for the plurality of EEPROM devices 2. .

A preset very short time (eg 10
After the elapse of μS), a data write verify (confirmation) command for each of the cells specified in each EEPROM device 2 ... Is set by the ALPG 24, and the DUT driving unit 21 sets each DUT 2 ... Executed respectively.

When the verify command is executed, each D
Response signals are input from the UTs 2 ... to the respective time comparators 23 ... at any time. Each time comparator 23 ...
・ Compares the permissible time signal sent from the permissible time register 22 and the response signal sent from each DUT 2 ..., and determines whether the response signal is sent within the permissible time. .

For example, as shown in FIG.
It is assumed that (a) is an allowable time signal, (b) is a response signal sent from the first DUT 2, and (c) is a response signal sent from the second DUT 2. Since the response timing of the signal of (b) is within the allowable time of (a), the first
The DUT 2 is determined to be “YES” by the first time comparator 23. On the other hand, since the response timing of the signal of (c) does not fall within the allowable time of (a), the second DU
The second time comparator 23 determines T2 to be "NO".

When the second time comparator 23 determines “NO”, the second time comparator 23 sends a message to that effect to the control unit 30. The control unit 30 causes the retry count comparator 28 to determine whether the retry count is within the allowable retry count by the operation described below. When it is determined that the number of retries is within the allowable number of retries, the control unit 30 causes the ALPG 24 to set the same command as the previous command, and the DUT driving unit 21 sets the command to the second DUT 2 that is determined to be “NO”. Let it run.

On the other hand, if it is determined that the number of retries is not within the allowable number of retries, the failure D
The second DUT 2 determined to be “NO” by the UT information latch circuit 29 is determined to be defective and excluded from the retry target. Then, the defective DUT information latch circuit 29 determines whether all the DUTs 2 ...
In the case of T failure, the inspection is finished.

When the time comparator 23 determines "YES", each signal comparator 25 ...
・ A response signal is sent. Then, each signal comparator 2
5, the expected value signal sequentially sent from the ALPG 24 is compared with each output signal sent from each inspection target cell of each DUT 2.

When the output signals from the cells to be inspected of each DUT 2 match the expected value signals, each signal comparator 25 ... A determination signal indicating that the signals match is transmitted to the control unit 30. The control unit 30 executes control for suppressing the CE function for the matched inspection target cell, that is, processing for prohibiting duplicate write.

Here, when the output signal from the cell to be inspected of the EEPROM device 2 and the expected value signal match, the write operation expected for the cell currently designated in the EEPROM device 2 is normally executed. It means that it has been Therefore, it is not necessary to execute the write operation again for the inspection target cell of the EEPROM device 2 for which the write operation has been executed. Conversely, when the write operation is executed again, the EE
Since the number of writable times when the PROM device 2 is put into practical use is reduced, it is desirable to prohibit further write operations. Therefore, in the present embodiment, regarding the present inspection target cell in which the write operation is executed,
The control unit 30 executes the control for suppressing the CE function, thereby preventing the rewriting.

On the other hand, when the output signal from the current cell to be inspected in a certain EEPROM device 2 does not match the expected value signal, the signal comparator 25 determines that EEPROM.
A determination signal indicating that the signals do not match with respect to the cell currently inspected in the OM device 2 is transmitted to the retry counter 27.

The retry counter 27 is the signal comparator 2
In response to the determination signal from 5, the current count value is transmitted to the frequency comparator 28. The number of times comparator 28 compares whether or not the present count value is smaller than the maximum retry value set in the allowable retry number register 26.

When the current count value is smaller than the maximum retry count value, the count comparator 28 sends a determination signal to that effect to the control unit 30. The control unit 30 controls the retry counter 27, the ALPG 24, and the DUT drive unit 21 based on the determination signal. That is, the loop 31 at the time of retry of the data write / verify shown in FIG. 2 is executed again.

In the state where the data write command is issued again under the same condition, it is not necessary to change the write command or the verify command each time the data write verify check is retried, so that the testing time and testing cost increase. Can be suppressed.

Even in this data write verify operation again, the same E as the previous mismatch is obtained.
When the output signal from the cell to be inspected in the EPROM device 2 becomes inconsistent with the expected value signal again, the signal comparator 25 retries the determination signal indicating that the same cell is inconsistent in the previous inconsistency. -Retransmit to the counter 27.

The retry counter 27 is the signal comparator 2
In response to the rejudgment signal from 5, the present count value is transmitted to the frequency comparator 28. The number of times comparator 28 compares whether or not the current count value is smaller than the maximum retry value set in the retry register 26. At this time, the count value of the retry counter 27 is counted only once compared to the previous time.
Is up.

When the current count value is smaller than the maximum retry count value, the count comparator 28 sends a determination signal to that effect to the control unit 30. The control unit 30 controls the retry counter 27, the ALPG 23, and the DUT drive unit 21 based on the determination signal. That is, the loop 31 at the time of retry of the data write / verify shown in FIG. 2 is executed again.

When the current count value becomes larger than the maximum retry count value after the above-described retry loop 31 is repeated many times, the count comparator 28 sends a determination signal to that effect to the control unit 30. Send to. The control unit 30 determines the defective device information latch circuit 29 based on the determination signal.
By controlling the E not only the cell under test in which writing was not performed but also the E
The entire EPROM device 2 is certified as defective. Then, the EEPROM device 2 is excluded from the subsequent data write verify inspection target. Then, along with this exclusion, the count of the retry counter 27 is cleared.

When the EEPROM device 2 having cells for which the write operation has not been executed even after the maximum number of retries by the retry loop 31 is excluded from the inspection target, the control unit 30 determines whether all the devices are defective. To be judged. That is, it is determined whether or not the exclusion has been executed in all the EEPROM devices 2.

If all devices are defective,
Since this means that the EEPROM devices 2 ... Which should be inspected do not exist, the power supply 21 makes the Vpp voltage and the Vcc voltage equal by the path 34 shown in FIG. EEPROM device 2
The data write verify check for the group is completed.

On the other hand, if all the devices are not defective, the EEPROM device 2 to be inspected remains, so that the inspection previously executed by the path 35 shown in FIG. 2 is the inspection for the cell of the final address. It is determined whether or not. If it is not the cell at the final address, the data write verify test is continuously performed on the next cell in the remaining EEPROM device 2.

On the other hand, after the number of times comparator 28 determines that the output signal from the cell to be inspected coincides with the expected value signal and the control unit 30 executes the duplicate write inhibit control, the current inspected object is detected. If it is determined that the output signals of all the cells of each EEPROM device 2 ...
4, the cell at the next address in each EEPROM device 2 ... Is designated as the next inspection target.

Then, it is verified whether or not the data is written in the designated cell to be inspected next. In other words, by designating the cell of the next address, the data write verify check is performed for a plurality of Es.
This means that the EPROM devices 2 ...

Then, a plurality of EEPROM devices 2
When the data write operation is not executed for the cell of the next address in ..., The data write verify check operation is performed by the count of each retry counter 27 ... By the loop 32 shown in FIG. Returned to the point of up. Then, the above-described retry operation of the data write verify check is repeated.

On the other hand, if all the data write operations are executed for this cell group to be inspected, when the verification is judged by the above operation, the control unit 30 suppresses the CE function for all the cell groups, that is, Data write protection is released at the same time.

When the control unit 30 releases the inhibition of the CE function, it is determined whether or not the cell to be inspected at that time is the cell of the final address. When it is determined that the cell has the final address, the power supply makes the Vpp voltage equal to the Vcc voltage, and the data write verify test is completed.

When it is determined that the cell is not the cell of the final address, the maximum number of retries is saved by the retry counter 27 by the loop 33 shown in FIG. Cleared. Further, the address is incremented by the ALPG 24.

Then, by the loop 33 shown in FIG. 2, the data write verify test operation is returned to the time when the retry counter 27 counts up. Then, the above-described data write verify inspection operation is repeated.

According to the above-mentioned embodiment, the following effects can be obtained. (1) Since the data write verify test can be executed simultaneously for a plurality of EEPROM devices, the workability of the data write verify test can be significantly improved.

(2) When simultaneously performing the data write verify test on a plurality of EEPROM devices, it is determined whether or not the data write is performed within the allowable time among the plurality of EEPROM devices, and it is not performed. By retrying the data write verify test for the EEPROM, the test time can be prevented from being influenced by the variation in the response of the EEPROM device, and thus the data write verify test time of the EEPROM device can be shortened. .

(3) When the data write verify check is retried for a plurality of EEPROM devices, the data write verify check is retried under the same condition, so that the write condition and the verify condition are not changed for each retry. Therefore, it is possible to suppress an increase in testing time and testing cost.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the semiconductor memory device to be inspected is not limited to the EEPROM, but may be an EPROM (Electror).
ically Programmable ROM. ROM that can be erased by irradiating ultraviolet rays. ) Etc. Also,
An arithmetic processing unit in which these semiconductor memory devices are used as an internal memory or an external memory is also an inspection target.

The retry operation may be omitted.

In the above description, the case where the invention made by the present inventor is mainly applied to the aging technique which is the background field of application has been described, but the present invention is not limited to this and it is not limited to the wafer prober and the auto handler. It can be applied to all electrical characteristic tests such as a write verify test.

[0066]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

When the data write verify test is simultaneously performed on a plurality of semiconductor memory devices, it is determined whether or not the data write is performed within the allowable time among the plurality of semiconductor memory devices. Can be prevented from being influenced by variations in the responsiveness of the semiconductor memory device, so that the data write verify inspection time of the semiconductor memory device can be shortened.

Since the data write verify test can be simultaneously performed on a plurality of semiconductor memory devices, the workability of the data write verify test can be greatly improved.

When the data write verify test is retried for a plurality of semiconductor memory devices, the data write verify test is retried under the same condition, so that it is not necessary to change the write condition or the verify condition for each retry. Therefore, it is possible to suppress an increase in testing time and testing cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a data write verify inspection apparatus for an EEPROM device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a data write verify test method for an EEPROM device according to an embodiment of the present invention.

FIG. 3 is a timing waveform diagram at the time of a data write verify inspection.

[Explanation of sign]

2 ... EEPROM device (DUT, semiconductor memory device), 20 ... EEPROM device data write verification test device, 21 ... DUT drive section, 22 ... Allowable time register, 23 ... Time comparator, 24 ... Expected value generator, 25 ... Signal comparator, 26 ... Allowable retry count register, 27 ... Retry counter, 28 ... Count comparator, 2
9: defective DUT information latch circuit, 30 ... control unit, 31,
32 ... Flow loops, 33, 34, 35 ... Flow paths.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Keiji Tomita 3-3, Fujibashi, Ome City, Tokyo 2 Hitachi Tokyo Electronics Co., Ltd.

Claims (3)

[Claims] 1. A method for inspecting electrical characteristics of a semiconductor memory device, wherein a data write verify test is performed on the semiconductor memory device, after a data write verify test is simultaneously performed on a plurality of semiconductor memory devices. , It is compared whether the input timing of the response signal from each semiconductor memory device is within the permissible time, the semiconductor memory device which is not within the permissible time is designated, and the designated semiconductor memory device is not designated. A method for inspecting electrical characteristics of a semiconductor memory device, wherein control different from that of the semiconductor memory device is executed. 2. The method for inspecting electrical characteristics of a semiconductor memory device according to claim 1, wherein another handling is a retry of a data write verify inspection under the same condition. 3. An electrical characteristic inspection device for a semiconductor memory device, wherein a data write verify test is executed on the semiconductor memory device, wherein the input timing of response signals from each of the semiconductor memory devices and the allowable time register If the input timing of the response signal is not within the permissible time by comparing with the permissible time signal, the semiconductor memory device that specifies the semiconductor memory device and the semiconductor memory device specified by the time comparator are not specified An electrical characteristic inspection apparatus for a semiconductor memory device, comprising: a control unit that executes control different from the device.