JPH0757402A - Block identification signal processor - Google Patents

Abstract

PURPOSE:To provide a block identification signal processor simple in circuit configuration for generating a predictive signal as a reproductive block identification signal at the time of detecting the error of the block identification signal when reproduction is carried out. CONSTITUTION:This processor is provided with a first conversion means 4 for converting the identification signal of a reproductive sink block(SB) into a virtual block identification signal, a means 5 for identifying the error of the reproductive SB block identification signal, a prediction means 6 for generating the predictive signal of the block identification signal, an output means for outputting the virtual block identification signal from the first transformation means as a normal identification signal when there are no errors in the reproductive SB block identification signal and outputting the predictive signal as a normal block identification signal when there are errors in the reproductive SB block identification signal, and a second conversion means 7 for converting the virtual block identification signal from the means 8 reversely to the first conversion means 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention corresponds to each block by dividing a digital signal group into blocks of a predetermined unit and adding a block identification signal and a synchronizing signal corresponding to the arrangement of blocks to each block. The present invention relates to a block identification signal processing device provided in a reproducing device for a storage medium in which sync blocks are formed and each sync block is sequentially stored in an order different from the above-mentioned arrangement of blocks according to a certain rule.

[0002]

2. Description of the Related Art In a digital VTR that digitally encodes and records a video signal, the digital video signal is generally recorded on a magnetic tape in sync block units as shown in FIG. One sync block includes a sync signal, a block identification signal (hereinafter referred to as an address signal), a digital video signal to be recorded, and an error correction code for the digital video signal. During reproduction, the sync signal is detected to synchronize the sync blocks, and the digital video signal is processed according to the address signal.

In such a digital VTR, the position of the video signal data in one screen is determined by the address signal. Therefore, when an error occurs in the read address signal during reproduction, the image cannot be reproduced normally.

Therefore, in the case of an error in the read address signal at the time of reproduction, there is a method in which a value obtained by adding 1 to the address signal obtained from the immediately preceding sync block is assigned (special feature). JP-A-58-9908 (see International Classification H04N5 / 92)).

This conventional device will be described with reference to FIGS.

In one scan of the rotary head, that is, in one track, data of N sync blocks 0 to (N-1) is recorded, for example, as shown in FIG. 0 to (N-1) in FIGS. 8A to 8C indicate address signals corresponding to sync blocks 0 to (N-1) in one track. An error check code for each address signal is added to each address signal 0- (N-1).

FIG. 7 shows an address signal processing circuit in a digital VTR. This processing circuit protects the address signal recorded in one track.
The reproduced signal is sent to the address identification determination circuit 11, and when the sync signal is detected, the address signal is extracted and the error detection is performed based on the error check code for each address signal. Figure 8
(A) shows an address signal extracted by the address identification determination circuit 11 and a portion (hatched portion) where an error of the address signal is detected.

When the address signal extracted by the address identification determination circuit 11 has no error, the address signal is output as a normal address signal via the changeover switch 12 and is also sent to the prediction circuit 13.
FIG. 8C shows an address signal output via the switch 12.

The prediction circuit 13 creates a prediction signal for the address signal of the next sync block from the address signal sent through the changeover switch 12. In this case, the address signal to be extracted from the address identification determination circuit 11 simply increases by 1 from 0 to (N-1).
The prediction circuit 13 adds 1 to the input address signal to create a prediction signal of the address signal for the next sync block. FIG. 8B shows the prediction signal created by the prediction circuit 13.

When the address identification determination circuit 11 detects an error in the address signal, the changeover switch 12 is switched to select the output of the prediction circuit 13, and the prediction signal from the prediction circuit 13 is a normal address signal. Is output as.

That is, when an error occurs in the address signal, the prediction signal of the prediction circuit 13 is used as the address signal to protect the address signal.

[0012]

When a digital video signal of one screen is recorded on a magnetic tape, in order to prevent damage such as scratches on the tape from concentrating on the same part of one screen, Such recording methods have been developed.

That is, the sync block for one track is divided into a plurality of large blocks. For example, as shown in FIG. 3, the sync block for one track is divided into three blocks (correction blocks) MB0, MB1, and MB2 for each unit for inspecting the error of the digital video signal. The sync blocks in each of the correction blocks MB0, MB1, and MB2 are represented by using correction block numbers 0 to 3 and sync block numbers 0 to (N-1). That is, the N sync blocks in the correction block MB0 are represented by 00-0 (N
It is represented by -1). The N sync blocks in the correction block MB1 are represented by 10 to 1 (N-1). Correction block MB
The N sync blocks in 2 are represented by 20 to 2 (N-1).

The original array of these sync blocks is the sync blocks 00, 01 ... 0 in the correction block MB0.
(N-1), sync block 1 in correction block MB1
0, 11 ... 1 (N-1) and sync blocks 20, 21 ... 2 (N-1) in the correction block MB2. As shown in FIG. 4, such sync blocks for one track are shuffled between the correction blocks MB0, MB1, and MB2 and sequentially recorded on one track.

When such a recording method is adopted,
The address signal added to the reproduced digital video signal data does not simply increase. Therefore, when the prediction circuit is used to protect the address signal like the conventional address signal processing circuit shown in FIG. 7, the prediction circuit adds 1 to the address signal of the immediately preceding sync block. When a prediction signal is created by using such a predictive signal, a simple one cannot be used. Therefore, the structure of the prediction circuit becomes complicated and the circuit scale increases.

According to the present invention, a digital signal group is divided into blocks of a predetermined unit, and a block identification signal and a synchronization signal corresponding to the arrangement of blocks are added to each block to form a sync block corresponding to each block. A block identification signal processing device provided in a reproduction device for a storage medium in which each sync block is sequentially stored in a different order from the above-mentioned block arrangement according to a certain rule, and an error of the block identification signal is detected during reproduction. It is an object of the present invention to provide a block identification signal processing circuit having an extremely simple circuit configuration for creating a prediction signal to be used as a reproduction block identification signal when being processed.

[0017]

In the block identification signal processing device according to the present invention, a digital signal group is divided into blocks of a predetermined unit, and a block identification signal and a synchronization signal corresponding to the arrangement of blocks are added to each block. By doing so, a sync block corresponding to each block is formed, and a block identification signal processing device provided in a reproducing device for a storage medium in which the sync blocks are sequentially stored in an order different from the arrangement of the blocks according to a certain rule. That is, the first conversion means for converting the block identification signal of the reproduced sync block into the virtual block identification signal in which the variation amount becomes constant in the reproduction order, and the block identification signal of the reproduced sync block has an error. Discriminating means for discriminating whether or not there is, predicting means for producing a prediction signal of the block identification signal, reproduction If there is no error in the block identification signal of the generated sync block, the virtual block identification signal obtained by the first conversion means is output as a normal virtual block identification signal, and the block identification signal of the reproduced sync block has no error. If there is, the prediction signal obtained by the prediction means is output as a normal virtual block identification signal, and the virtual block identification signal output from the output means is converted in the opposite direction to the first conversion means. , A second conversion means for returning the original block identification signal, and the prediction means creates a prediction signal of the block identification signal of the sync block to be reproduced next based on the virtual block identification signal output from the output means. It is characterized by being

[0018]

The reproduced block identification signal of the sync block is converted by the first conversion means into a virtual block identification signal having a constant variation (an integer other than zero) in the reproduction order. When there is no error in the block identification signal of the reproduced sync block, the virtual block identification signal obtained by the first conversion means is output from the output means as a normal virtual block identification signal. Further, when there is an error in the block identification signal of the reproduced sync block, the prediction signal obtained by the prediction means described later is output from the output means as a normal virtual block identification signal. The virtual block identification signal output from the output means is
The second conversion means performs conversion in the opposite direction to that of the first conversion means, so that the original block identification signal is restored.

In the prediction means, a prediction signal of the block identification signal of the sync block to be reproduced next is created based on the virtual block identification signal output from the output means.
That is, in the predicting means, a value according to the amount of change in the virtual block identification signal obtained from the first converting means is added to the virtual block identification signal output from the output means, so that the sync block to be reproduced next is reproduced. A prediction signal of the block identification signal of is generated. Therefore, a simple circuit can be used as the prediction circuit.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS.
An embodiment in the case of being applied to a digital VTR that records and reproduces a digitally encoded video signal will be described.

FIG. 3 shows a sync block for one track recorded on the magnetic tape. The sync block for one track has three blocks (correction blocks) MB0 for each unit for checking an error of the digital video signal,
It is divided into MB1 and MB2.

The sync blocks in each of the correction blocks MB0, MB1 and MB2 are assigned a correction block number of 0 to 3 and 0.
To (N-1) sync block numbers. That is, the N sync blocks in the correction block MB0 are represented by 00 to 0 (N-1). The N sync blocks in the correction block MB1 are represented by 10 to 1 (N-1). 20 to 2 N sync blocks in the correction block MB2
It is represented by (N-1). The original array of these sync blocks is the sync blocks 00, 01 in the correction block MB0.
.. 0 (N-1), sync blocks 10, 11 ... 1 (N-1) in the correction block MB1, and sync blocks 20, 21 ... 2 (N-1) in the correction block MB2.

Then, as shown in FIG. 4, shuffling is performed between the correction blocks MB0, MB1 and MB2,
Sync blocks for one track are sequentially recorded on one track. Therefore, data of 3 correction blocks × N sync blocks is recorded on one track.

Each sync block is, as shown in FIG.
It is composed of a synchronization signal, a block identification signal (address signal), a digital video signal, and an error correction code for the digital video signal. An error check code for the address signal is added to the address signal.

FIG. 1 shows an address signal processing circuit used during reproduction.

The recorded data read from the magnetic tape is subjected to processing such as waveform equalization, and the demodulated digital signal is input to the reproduction signal input terminal 1. The digital signal input to the reproduction signal input terminal 1 is transferred to the sync detection circuit 2
And is sent to the address signal extraction circuit 3.

The sync detection circuit 2 detects a sync signal for each sync block. In the address signal extraction circuit 3,
An address signal to which an error check code is added is extracted from the input digital signal based on the synchronization signal detected by the synchronization detection circuit 2. The extracted address signal is sent to the reproduction address-virtual address conversion circuit 4 and the error detection circuit 5.

In the reproduction address-virtual address conversion circuit 4, an input address, that is, an address (reproduction address) whose order is changed by shuffling as shown in FIG. Figure 2
As shown in (b), the address is converted into an address (virtual address) that is simply incremented by 1 and output. Address conversion by the reproduction address-virtual address conversion circuit 4 is performed by, for example,
This is done by using a conversion table created in advance. The output of the reproduction address-virtual address conversion circuit 4 is sent to the contact a of the changeover switch 8. The output of the prediction circuit 6 is sent to the contact b of the changeover switch 8.

The error detection circuit 5 determines whether the address signal is correct or error based on the error check code of the sent address signal. When a code error in the sent address signal is detected, the changeover switch 8 is switched to the contact b side (predicted address selection contact), and when the sent address signal is correct, the changeover switch 8 is changed to the contact a side. Switch to (playback address selection contact).

Therefore, when the address signal sent to the error detection circuit 5 is correct, the virtual address output from the reproduction address-virtual address conversion circuit 4 is output from the switch 8 as a normal virtual address. On the other hand, when the address signal sent to the error detection circuit 5 is incorrect, the predicted address output from the prediction circuit 6 is output from the switch 8 as a regular virtual address.

The regular virtual address output from the changeover switch 8 is sent to the prediction circuit 6. The prediction circuit 6 outputs an address obtained by adding 1 to the input virtual address as a prediction address for the next sync block. Therefore, when the address signal sent to the error detection circuit 5 is erroneous, the value obtained by adding 1 to the regular virtual address for the immediately preceding sync block is the regular virtual address from the changeover switch 8. Is output.

The regular virtual address output from the changeover switch 8 is sent to the virtual address-reproduction address conversion circuit 7. The virtual address-reproduction address conversion circuit 7 converts the input virtual address into the original reproduction address by performing conversion in the opposite direction to the reproduction address-virtual address conversion circuit 4. The address conversion by the virtual address-reproduction address conversion circuit 7 is performed, for example, by using a conversion table created in advance. The address signal obtained by the virtual address-reproduction address conversion circuit 7 is output from the output terminal 9.

According to the above-described embodiment, when the sync blocks are recorded by shuffling the correction blocks to record the sync blocks, the addresses of the recorded sync blocks change in a complicated manner. The configuration of the circuit for creating the predicted address used as the reproduction address when the error is detected becomes extremely simple.

In the above embodiment, the virtual address is 1
The example has been described in which the virtual address is increased by N.
(N is an integer satisfying N ≧ 1) may be increased or decreased.

The present invention can also be applied to a block identification signal processing device in a digital audio signal recording / reproducing device.

[0036]

According to the present invention, a digital signal group is divided into blocks of a predetermined unit, and a block identification signal and a synchronization signal corresponding to the arrangement of blocks are added to each block so as to correspond to each block. When a sync block is formed and a sync signal is detected on the playback device side for a storage medium in which sync blocks are sequentially stored in an order different from the above-mentioned block arrangement according to a certain rule, the playback block identification is performed. The configuration of the circuit for creating the prediction signal used as the signal becomes extremely simple.

[Brief description of drawings]

FIG. 1 is a block diagram showing an address signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a relationship between a reproduction address and a virtual address.

FIG. 3 is a schematic diagram showing a sync block and a correction block for one track.

FIG. 4 is a schematic diagram showing a sync block for one track recorded on a magnetic tape.

FIG. 5 is a schematic diagram showing a format of one sync block.

FIG. 6 is a schematic diagram for explaining a conventional example and showing a sync block for one track.

FIG. 7 is a block diagram showing a conventional example.

FIG. 8 is a time chart showing signals of respective parts of FIG.

[Explanation of symbols]

 2 sync detection circuit 3 address signal extraction circuit 4 reproduction address-virtual address conversion circuit 5 error detection circuit 6 prediction circuit 7 virtual address-reproduction address conversion circuit 8 changeover switch

Claims (1)

[Claims] 1. A digital signal group is divided into blocks of a predetermined unit, and a sync block corresponding to each block is formed by adding a block identification signal and a synchronization signal corresponding to the arrangement of blocks for each block. A block identification signal processing device provided in a reproducing device for a storage medium in which respective sync blocks are sequentially stored in a different order from the arrangement of the blocks according to a certain rule, and a block identification signal of a reproduced sync block is A first conversion means for converting into a virtual block identification signal having a constant variation in the order of reproduction, a determination means for determining whether or not there is an error in the block identification signal of the reproduced sync block, a block identification signal There is no error in the prediction means for creating the prediction signal and the block identification signal of the reproduced sync block. In this case, the virtual block identification signal obtained by the first conversion means is output as a normal virtual block identification signal, and when there is an error in the block identification signal of the reproduced sync block, the prediction obtained by the prediction means. The output means for outputting the signal as a regular virtual block identification signal and the virtual block identification signal output from the output means are
Second conversion means for returning the original block identification signal by performing conversion in the opposite direction to the conversion means is provided, and the prediction means is reproduced next based on the virtual block identification signal output from the output means. A block identification signal processing device for creating a prediction signal of a block identification signal of a sync block.