JPH0756885B2 - Semiconductor memory - Google Patents

Description

The present invention relates to a semiconductor memory, and more particularly to a wiring layout of a dynamic RAM.

[Prior Art] As an example of a conventional dynamic RAM, a circuit diagram of a sense amplifier of 1M DRAM and its periphery is shown in FIG. 3 and will be described with reference to FIG. In 1M DRAM, 2048-bit cells have to be refreshed at a time, so 2048 sense amplifiers are arranged along one word line. The terminals A1 to A2048 and the terminals B1 to B2048 of the sense amplifier array arranged along one side of the memory cell array are connected to the P channel driver and the N channel driver respectively at one end of the cell array by driver wiring. After the signal appears in the sense amplifier, the sense signal φSE becomes high level and φ ▲ ▼ becomes low level, and the sense amplifier starts operating. At this time, since 2048 sense amplifiers operate simultaneously, a large amount of current flows in the driver wiring, and the potential difference between A1 and B1 far from the drive transistor becomes smaller than the potential difference between A2048 and B2048 near the drive transistor. Driver wiring width 20μ, length 16m
Assuming that the layer resistance of m and Al is 0.025Ω / □, the wiring resistance is 20Ω, and the peak current of 50mA is 1V each, and there is a difference of 2V at the far end and the near end.
It will be considerably delayed compared to S2048.

[Problems to be Solved by the Invention] In the above-described conventional dynamic RAM, the number of cells connected to one word line increases with the increase in capacity, and the distance from the driver to the far end of the sense amplifier array increases. The resistance cannot be ignored. When the sense amplifier is driven in this state, a large current flows through the driver wiring, and the potential at the drive terminal of the sense amplifier is greatly different at both ends of the sense amplifier array. The sense sensitivity deteriorates, and the sense amplifier at the far end of the driver lowers the sense speed and delays the entire access. Therefore, it is difficult to optimally design all sense amplifiers.

If you try to increase the driver wiring width in the sense amplifier and lower the resistance, the sense amplifier itself becomes larger than necessary to secure the wiring area, and the parasitic resistance of the wiring inside the sense amplifier orthogonal to the driver wiring increases. However, if the diffusion layer of the sense amplifier is enlarged, the capacitance of the diffusion layer connected to the bit line is increased and CB / CS is deteriorated. If the wiring length is shortened to increase the division of the cell array and the resistance between the sense amplifier and the driver is reduced, the chip size increases.

[Differences from the Prior Art of the Invention] In contrast to the conventional dynamic RAM described above, the present invention is
The sense amplifier is driven from the power supply and GND through multiple drivers, and its drive wiring is placed on the cell array.

[Means for Solving Problems] A semiconductor memory according to the present invention includes memory cells divided into a plurality of groups, a plurality of sense amplifiers connectable to each of the plurality of groups of the memory cells, and a plurality of sense amplifiers. In a semiconductor memory including a common drive signal line for supplying a current, a plurality of drive transistors are connected in parallel to the common drive signal line, and the drive transistors are connected to a power supply wiring.

Therefore, in the semiconductor memory of the present invention, the wiring connecting the sense amplifier from the power supply and GND via the driver is connected by a sufficiently thick wiring around the chip and a plurality of wirings from the chip periphery through the cell array to the sense amplifier. Therefore, the resistance between the power supply and GND and the sense amplifier is almost constant in the sense amplifier array, and the difference in sense speed between the sense amplifiers is extremely small.

[Embodiment] FIG. 1A is a circuit diagram of a first embodiment of the present invention. FIG. 1B is a circuit diagram of the sense amplifier used in the present invention. The terminals on the P-channel transistor side of each of the sense amplifiers S1 to Sn are connected to each other and pass through the memory cell.
It is connected to a plurality of P channel drivers P1 to Pk on the opposite side of the memory cell array via L1 to Lk. Similarly, the terminals on the N-channel transistor side of each of the sense amplifiers S1 to Sn are also connected to a plurality of N-channel drivers N1 to Nk on the opposite side of the memory cell array via wirings N1 to Nk.

After the signal in the cell appears on the bit line, the sense signal φSE becomes high level and φ ▲ ▼ becomes low level, and each driver is in the operating state. At this time, since the currents to the sense amplifiers S1 to Sn are supplied through the wirings L1 to Lk and M1 to Mk, the potentials of both terminals of the sense amplifiers S1 to Sn are set to the sense of S1 to Sn if the wiring intervals are sufficiently small. The potentials are almost equal in the amplifier, and the difference in sense speed is almost eliminated.

FIG. 2 is a circuit diagram of the second embodiment of the present invention.

S1 to Sn are the sense amplifiers shown in FIG. In a sense amplifier array sandwiched between two memory cell arrays in a dynamic RAM in which bit lines are multi-divided, a plurality of P-channel transistor side terminals connected to each other and a plurality of N-channel transistor side terminals connected to each other are provided. P channel drivers P1 to Pk and N channel drivers N1 to Nk are connected. The plurality of power supply wirings and the GND wirings pass over the plurality of cell arrays in the direction along the bit lines, and these wirings are connected to the P channel drivers P1 to Pk and the N channel drivers N1 to Nk, respectively.

[Effects of the Invention] As described above, according to the present invention, by arranging all or part of the wiring between the power supply and GND and the sense amplifier on the array, the sense between the sense amplifiers is increased without increasing the chip size. The speed difference is reduced, and the optimum sense operation design is possible for all sense amplifiers.

[Brief description of drawings]

1A is a circuit diagram of a first embodiment of the present invention, FIG. 1B is a circuit diagram of a sense amplifier used in the embodiment of the present invention, and FIG. 2 is a second embodiment of the present invention. FIG. 3 is a circuit diagram of a conventional 1M DRAM sense amplifier and its peripherals. S1 to Sn …… Sense amplifier, P1 to Pk …… P channel driver, N1 to Nk …… N channel driver, L1 to Lk, M1 to M
k …… driver wiring.

Claims (1)

[Claims] 1. A memory cell divided into a plurality of groups,
In a semiconductor memory including a plurality of sense amplifiers connectable to each of a plurality of groups of the memory cells and a common drive signal line for supplying a current to the plurality of sense amplifiers, a plurality of drive transistors are provided on the common drive signal line. Are connected in parallel, and the drive transistor is connected to a power supply wiring.