JPH0756809A - Cache prefetching device - Google Patents

Abstract

PURPOSE:To perform control to a cache memory so as to transfer data from a storage device to the cache memory by predicting the address of those data to be accessed in the future. CONSTITUTION:This device is composed of instruction address history holding means 20-2N for storing the instruction addresses of load instructions executed in the past, data address history holding means 30-3N for storing the data addresses of those instructions, address comparator circuits 40-4N for respectively comparing the respective addresses from the means 20-2N with the present instruction address, address selecting circuit 60 for selecting one of addresses in the means 30-3N based on the compared results of these circuits 40-4N, address generating circuit 70 for generating the predictive address from the address from this circuit 60 and the present address, and cache control means 80 for instructing data transfer to the cache memory by using this predictive address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control device for controlling data transfer from a storage device to a cache memory, and more particularly to a cache control for transferring data that will be needed in the future to the cache memory. The present invention relates to a prefetch device.

[0002]

2. Description of the Related Art Conventionally, in this type of cache memory control device, when an event that necessary data does not exist in the cache memory (hereinafter referred to as a cache miss) occurs, the data is required from the storage device to the cache memory. Controlled to transfer data. For example, JP-A-5
Japanese Patent Laid-Open No. 9-96585 discloses a cache memory control device which issues a data request to both the cache memory and the storage device at the time of a cache miss.

As a method of controlling the cache memory from software, data that will be needed in the future is specified by a software instruction, and the necessary data is transferred from the storage device to the cache memory in advance. Was there. For example, “February 1992, C. Dowdell and L. Thaye
r: "Scalable Graphics Enhancements for PA-RISC Wo
rkstations ", Proc. of IEEE COMPCON 92, pp.122-128,
Feb. 1992.) "describes a cache prefetch instruction (fetch32) for instructing a block transfer of 32 bytes of data to a data cache.

[0004]

However, in the former conventional cache memory control device, since the access to the storage device is started by the cache miss, it takes time until the central processing unit receives the data, There was a problem that the instruction that needed the data could not be continued. In addition, recent central processing units aim to improve throughput performance by adopting a pipeline configuration, but there are cases in which the entire pipeline must be stopped due to a cache miss. It was a hindrance to the improvement of effective performance.

Further, in the latter method by the conventional cache prefetch instruction, since the prefetch operation must be explicitly instructed on the program by this prefetch instruction, the program amount increases and the instruction supply is hindered, and the effective performance is reduced. Will have a negative effect on. Furthermore, since it is generally impossible to completely grasp the address for accessing the storage device before executing the program, it is difficult to generate the prefetch instruction at an appropriate position on the program during compilation.

[0006]

In order to solve the above-mentioned problems, the cache prefetch device of the present invention is
An address history holding unit including an instruction address history holding unit holding an instruction address and a data address history holding unit holding a data address for a load instruction for fetching data from a storage device; instruction address history holding of the address history holding unit Instruction address comparison means for comparing the instruction address from the means with the instruction address of the input load instruction to detect a match; and a data address of the address history holding means based on the comparison result by the instruction address comparison means. Prediction address generating means for generating a prediction data address from the data address from the history holding means and the data address of the input load instruction; and the instruction address and the data address of the input load instruction, respectively. Address history holding means and the data Updating means for storing the address history holding means ;; predicting a data address to be accessed when the input load instruction is executed next time, and storing the data in advance in a cache memory from a storage device. Control to transfer.

The address history holding means includes a plurality of the instruction address history holding means and a plurality of the data address history holding means corresponding to the instruction address history holding means; the instruction address comparing means, A plurality of address comparison circuits for respectively comparing the instruction addresses of the plurality of instruction address history holding means with the instruction address of the input load instruction; and, based on the comparison results of the plurality of address comparison circuits, And an entry selection circuit for determining whether they match.
The predictive address generation means selects an address selection circuit that selects at most one of the data addresses from the plurality of data address history holding means based on the address matching information from the entry selection circuit, and a data address from this address selection circuit. An address generation circuit that generates a predicted address from the data address of the input load instruction is included.

Further, the address history holding means includes a plurality of the instruction address history holding means and a plurality of the data address history holding means corresponding to the instruction address history holding means; the instruction address comparing means, A plurality of address comparison circuits for respectively comparing the instruction addresses of the plurality of instruction address history holding means with the instruction address of the input load instruction; and, based on the comparison results of the plurality of address comparison circuits, And an entry selection circuit for determining whether or not they match each other; the predictive address generating means predicts each from a data address of the load instruction input corresponding to each of the plurality of data address history holding means. Address generation circuits that generate addresses and predictions from the address generation circuits And an address selection circuit for selecting the address coincidence information of the most one of the dress from the entry selection circuit.

Further, the address history holding means includes a plurality of instruction address history holding means composed of a plurality of words and a plurality of data addresses formed of a plurality of words corresponding to the instruction address history holding means. History holding means; the instruction address comparing means,
A plurality of address comparison circuits for respectively comparing the instruction addresses of the plurality of instruction address history holding means with the instruction address of the input load instruction; and, based on the comparison results of the plurality of address comparison circuits, And an entry selection circuit for determining whether or not they match with each other; the predicted address generation means determines a predicted address from each data address of the plurality of data address history holding means and the data address of the input load instruction. And a plurality of address generating circuits for generating the address, and an address selecting circuit for selecting at most one predicted address from the plurality of address generating circuits by the address matching information from the entry selecting circuit.

The address history holding means comprises a plurality of instruction address history holding means composed of a plurality of words, and a plurality of data addresses composed of a plurality of words corresponding to the instruction address history holding means. History holding means; the instruction address comparing means,
A plurality of address comparison circuits for respectively comparing the instruction addresses of the plurality of instruction address history holding means with the instruction address of the input load instruction; and, based on the comparison results of the plurality of address comparison circuits, And an entry selection circuit for determining whether or not they match each other; in the predicted address generation means, at most one of the data addresses from the plurality of data address history holding means is selected by the address matching information from the entry selection circuit. It includes an address selection circuit and an address generation circuit that generates a predicted address from the data address from the address selection circuit and the data address of the input load instruction.

The address history holding means includes one instruction address history holding means composed of a plurality of words and one data address formed of a plurality of words corresponding to the instruction address history holding means. And history holding means.

Further, the predicted address generating means further has a coincidence detection circuit for detecting a coincidence of the data address from the data address from the address selection circuit and the data address of the input load instruction.

The predictive address generating means detects a match of data addresses from the data addresses of the input load instructions corresponding to the data addresses from the plurality of data address history holding means. And a match detection and selection circuit that selects at most one of the match detection information from the plurality of match detection circuits according to the address match information from the entry selection circuit.

Further, the predicted address generation means detects a plurality of data address coincidences from the data addresses of the input load instructions corresponding to the respective data addresses from the plurality of data address history holding means. And a match detection and selection circuit that selects at most one of the match detection information from the plurality of match detection circuits according to the address match information from the entry selection circuit.

Further, the predicted address generating means further has a coincidence detection circuit for detecting a coincidence of the data address from the data address from the address selection circuit and the data address of the input load instruction.

Further, the predicted address generating means further has a coincidence detecting circuit for detecting a coincidence of the data addresses from the data address from the data address history holding means and the data address of the input load instruction.

It has been noted that in the above-described configuration of the present invention, in a program having a repeating structure, the memory reference address often changes at equal intervals each time the memory reference instruction stored at the same instruction address is executed. It has a function of predicting a data address of data that will be needed in the future, by holding an address history in which a memory reference was made in the past.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the cache prefetch device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a cache prefetch apparatus according to an embodiment of the present invention stores a pair of an instruction address of a memory load instruction executed in the past and an operand address (data address) of the memory load instruction. The instruction address history holding means 20 to 2N that stores past instruction addresses so that the data address paired with the designated instruction address can be read associatively.
And data address history holding means 30 to 3N for storing past data addresses. Further, it has an updating means 10 for updating the data address history holding means 30 to 3N and the instruction address history holding means 20 to 2N with the current instruction address and the current data address, respectively. Further, the instruction address history holding means 2
Address comparing circuits 40 to 4N for respectively comparing the respective addresses from 0 to 2N with the current instruction address, and an entry selecting circuit for judging which of the address comparing circuits 40 to 4N is matched based on the comparison result of these address comparing circuits 40 to 4N. 50, an address selection circuit 60 for selecting one of the data address history holding means 30 to 3N in accordance with an instruction from the entry selection circuit 50, an address from the address selection circuit 60 and a current data address It has an address generation circuit 70 for generating a predicted data address to be accessed, and a cache control means 80 for instructing data transfer to a cache memory using the predicted data address from this address generation circuit 70.

The instruction address history holding means 20 to 2N and the data address history holding means 30 to 3N each hold one address, and are 20 and 30, 21 and 31, 2 respectively.
2 and 32 are paired. For example, a data address corresponding to the instruction address held by the instruction address history holding means 20 is stored in the data address history holding means 30. It is possible to provide an arbitrary number of pairs of the instruction address history holding means and the data address history holding means (in this embodiment, there are N + 1 sets).

In this embodiment, the address comparison circuits 40 to 4N
Also, N + 1 pieces are provided, and instruction address history holding means 20 to 2N
Each of the past instruction addresses is received from and the match with the current instruction address is detected. This result is used by the address selection circuit 60 via the entry selection circuit 50 to select the data address from the data address history holding means 30 to 3N. The past data address selected by the address selection circuit 60 (hereinafter, referred to as “previous data address”) is supplied to the address generation circuit 70 by the signal line 670, and the address generation circuit 70 also receives the current data. Address is signal line 17
Supplied by 0. The address generation circuit 70 generates a predicted data address from the immediately previous data address and the current data address, and transfers the predicted data address to the cache control means 80 via the signal line 780.

If none of the instruction address history holding means 20 to 2N matches the current instruction address, the address selection circuit 60 selects nothing. Therefore, the address generation circuit 70 does not generate the predicted address, and the cache control unit 80 does not instruct the cache memory to transfer the data.

The updating means 10 includes address comparing circuits 40 to 40.
If a match is detected in 4N, the current data address is stored in the data address history holding means corresponding to the matched instruction address history holding means. That is, the data address history holding means is updated in preparation for the next search. If none of the instruction address history holding means 20 to 2N matches the current instruction address, one set of the instruction address history holding means and one set of the data address history holding means are secured to set the current instruction address. The current data address is stored in the instruction address history holding means, respectively. At this time, if all the instruction address history holding means and the data address history holding means are in use, one set is invalidated by some method,
You need to make room. In order to determine which is invalidated, the LRU algorithm generally used in the cache memory can be used.

Next, the operation of the above embodiment of the present invention will be described in detail with reference to the drawings.

First, referring to FIG. 2A, the program applied to this embodiment stores in each element of the array A the value of the scalar variable C added to each element of the array B.
Assuming that this array B has double precision, for example, as shown in FIG.
As shown in (b), each element of array B has a continuous address every 8 bytes. If the address of B (1) is 5000 at the first lap of the loop, the address of 5008 of B (2) is accessed at the second lap,
On the third lap, access to address 5016 of B (3). If this property is used, when B (2) is accessed, B
The address of B (3) can be predicted by adding the increment value from the address of (1) to the address of B (2). However, there are instructions to access the storage device in various places in the program, and the instruction address of the instruction is used to uniquely identify them.

Referring to FIG. 2 (c), the object code of the program of FIG. 2 (a) is such that the instruction address of a load instruction for loading one element of the array B from the storage device is 9000, and B and C The instruction address of the floating point addition instruction for adding and storing in A is 9004, and the instruction address of the store instruction for storing A in the storage device is 90.
At address 08, the instruction address of the fixed-point addition instruction that counts up the index counter I is address 9012, and the instruction address of the branch instruction that determines whether a predetermined number of loops has been executed is address 9016.

Referring to FIG. 3, in order to predict the data address of the array B, the instruction address 9000 of the load instruction and the previous data address 50 of the array B are used.
Address 00 is paired and held in the instruction address history holding means and the data address history holding means, respectively. Here, as the current instruction, the instruction address 900
The load instruction at address 0 is to be checked, and the operand address (data address) of this load instruction is at address 5008. The address comparison circuit 40
The current instruction address and the instruction address from the instruction address history holding means 20 are compared, and both are address 9000, and it is notified to the address selection circuit 60 that they match. The address selection circuit 60 selects the data address history holding means 30 from the plurality of connected data address history holding means 30 to 3N and uses the signal line 670 to select the previously held data address 5000 address. It is transferred to the address generation circuit 70. In the address generation circuit 70, the data address 5008 of the load instruction which is the current instruction is received by the signal line 170, and the next access is made from the current data address 5008 and the previous data address 5000. A wax prediction data address is generated and transferred to the cache control means 80 by the signal line 780.

Referring to FIG. 4, the address generation circuit 70
In one embodiment, the previous data address X on signal line 670 and the current data address Y on signal line 170.
Using and, first, Y−X is generated by the subtractor 701 to obtain the increment value from the previous time, and the data address of this time is added to this by the adder 702 to predict from the signal line 780. The data address (2 × Y−X) is output.

FIG. 4B shows another embodiment of the address generation circuit 70. First, a shifter 703 is provided to obtain twice the current data address Y. This shifter 7
Reference numeral 03 actually shifts the connection between the signal line 170 and the subtractor 704 by one bit in the upper direction to compensate for zero as the least significant bit, and is simplified as compared with the configuration of FIG. In any case, output from the signal line 780 (2 × Y−
X) can be obtained.

Next, the operation timing of the above embodiment of the present invention will be described in detail with reference to the time chart.

Referring to FIG. 5, at time T1, address 8096 is input as the current instruction address.
At the next time T2, the instruction address 900 of FIG.
A load instruction at address 0 has been input. The data address of this load instruction points to the address 5000. Since this instruction is a load instruction, the load instruction decode signal indicates that. By the load instruction decode signal, the instruction address history holding means 2 is provided for each of the instruction address 9000 and the data address 5000.
0 and stored in the data address history holding means 30. The stored value is reflected from the next time T3. At time T3, the instruction at the instruction address 9004 is input, and at subsequent time T4, the instruction at the instruction address 9008 is input.

When the branch instruction at the instruction address 9016 is executed with the object code of FIG. 2C, it does not reach the predetermined number (100 times), so the instruction address 9
Branch to the load instruction at address 000. In the timing chart of FIG. 5, the instruction address 9000 at time T7
An address load instruction is input, and the data address of this load instruction points to address 5008. Since the instruction address 9000 of this load instruction and the instruction address 9000 of the instruction address history holding means 20 match,
The output of the address comparison circuit 40 indicates "match". As a result, in the address selection circuit 60, the data address history holding means 30 paired with the instruction address history holding means 20.
Select the data address 5000 of the
To the address generation circuit 70. The data address of this load instruction is transferred to the address generation circuit 70 by the signal line 170, and the predicted data address 5016 is generated by this address generation circuit 70.
It is output from the signal line 780. Further, the updating means 10 stores the data address 5008 of the load instruction in the data address history holding means 30. The stored value is reflected from the next time T8.

After that, at T12, by the same operation as at T7,
The predicted data address is generated and the data address history holding unit 30 is updated.

As can be seen from the above description, in the present invention, by providing a plurality of pairs of instruction address history holding means and data address holding means each having an address comparison circuit, a load instruction for accessing the address space at regular intervals is provided. The data address can be predicted and prefetched into the cache memory.

Next, a second embodiment of the cache prefetch device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 6, the cache prefetch device of the second embodiment of the present invention stores the instruction address of the memory load instruction executed in the past and the data address of the memory load instruction as a pair and stores them. In order to associatively read the data address paired with the designated command address, the command address history holding means 20 to 2N for storing the past command address and the data address history for storing the past data address. Holding means 30-3
N and. Further, the data address history holding means 30 to 3N and the instruction address history holding means 20 to
2N is updated with a current instruction address and a current data address, respectively. Further, address generating circuits 70 to 7N for respectively generating predicted data addresses which will be accessed next from the data address from the data address history holding means 30 to 3N and the current data address, and the instruction address history holding. Address comparing circuits 40 to 4N for respectively comparing the respective addresses from the means 20 to 2N with the current instruction address,
An entry selection circuit 50 that determines which of the address comparison circuits 40 to 4N has a match based on the comparison result, and one of the address generation circuits 70 to 7N is selected according to an instruction from the entry selection circuit 50. It has an address selection circuit 60 and a cache control means 80 for instructing the cache memory to transfer data using the predicted data address from the address selection circuit 60.

In the second embodiment of the invention of FIG. 6, storing the instruction address of the memory load instruction executed in the past and the data address of the memory load instruction as a pair is the first embodiment of the invention of the present application. However, the difference is that the instruction address history holding means 20 to 2N and the data address history holding means 30 to 3N for storing them are each composed of a plurality of words. Along with this, several bits of the input instruction address are included in the instruction address history holding means 20 to 2N and the data address history holding means 3.
It is used to select a word of 0 to 3N, and the remaining part is held in the instruction address history holding means 20 to 2N and becomes a comparison target in the address comparison circuits 40 to 4N. For example, assuming that the number of words in each of the instruction address history holding means 20 to 2N and the data address history holding means 30 to 3N is 256 words, 8 bits of the instruction address correspond to the instruction address history holding means 20 to 2N and the data address history holding. It will be used for word selection of means 30-3N.

Referring to FIG. 7, in the main part of the second embodiment of the present invention, the upper part of the instruction address is the comparison target of the address comparison circuits 40 to 43, and the lower part thereof is the instruction address history holding means 20 to. 23 and the data address history holding means 30 to 33 are used for word selection. The lower part is not used on the assumption that each instruction address is demarcated in units of 4 bytes, for example. In addition, the address generation circuits 70 to 73 make the data address history holding means 3
Although provided in each of 0 to 33, the data address of the data address history holding means 30 to 33 is selected by the address selection circuit 60, and an address is generated from the selected data address and the current data address. It can also be configured as follows.

In the second embodiment of the present invention, when an address match is detected in any of the address generation circuits, the updating means 10 causes the data address history holding means corresponding to the address generation circuit in which the address match is detected. With the current data address. If the address match is not detected despite the load instruction, one of the instruction address history holding means and the data address history holding means is paired based on some algorithm as in the first invention. select. Which word of the selected instruction address history holding means and data address history holding means is used is uniquely determined by the instruction address as described above.

According to the second embodiment of the present invention, since the instruction address held by each instruction address history holding means is only a part of the original instruction address, it is compared with the first embodiment of the present invention. And can be configured with a smaller storage capacity. According to the second embodiment of the present invention,
Since the address comparison circuit is provided for each of a plurality of instruction addresses, the number of the address comparison circuits is smaller and the bit width is narrower than that of the first embodiment of the present invention in which the address comparison circuit is provided for every instruction address. Can be configured.

Next, a third embodiment of the cache prefetch device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 8, the cache prefetch device of the third embodiment of the present invention stores the instruction address of the memory load instruction executed in the past and the data address of the memory load instruction as a pair and stores them. In order to associatively read the data address paired with the designated instruction address, the instruction address history holding means 20 for storing the past instruction address and the data address history holding means for storing the past data address. 30, an updating unit 10 for updating the data address history holding unit 30 and the instruction address history holding unit 20 with a current instruction address and a current data address, and a data address from the data address history holding unit 30. And the current data address and the predicted data address that will be accessed next. Generating each address generation circuit 7
0, an address comparison circuit 40 that compares the instruction address from the instruction address history holding unit 20 with the current instruction address, a comparison result of these address comparison circuits 40, and a predicted data address from the address generation circuit 70. The cache control means 80 is used to instruct data transfer to the cache memory.

In the third embodiment of the present invention of FIG. 8, storing the instruction address of the memory load instruction executed in the past and the data address of the memory load instruction as a pair is the same as the first embodiment of the present invention. Although not different from the second embodiment, it is different in that only one instruction address history holding means 20 and one data address history holding means 30 for storing these are provided. That is, in the second embodiment of the present invention, among the instruction addresses, the instruction addresses having the same portion used for word selection can be stored at the same time.
This cannot be done in the third embodiment of the present invention. But,
Since it is not necessary to determine which pair of instruction address history holding means and data address history holding means should be used in the updating means 10 without requiring an address selection circuit, etc. There is an advantage that it can be realized with a simple configuration and the number of words of the instruction address history holding means 20 and the data address history holding means 30 can be made large.

Next, fourth to sixth embodiments of the cache prefetch device of the present invention will be described with reference to the drawings.

Referring to FIG. 9, the cache prefetch device according to the fourth embodiment of the present invention has a configuration in which a coincidence detection circuit 90 is added to the third embodiment of the present invention shown in FIG. The coincidence detection circuit 90 can compare the data address from the data address history holding unit 30 with the current data address and detect that the data address has not changed if the two coincide. As a result, it becomes possible to control the cache prefetch to be suppressed depending on the situation for the load instruction whose address does not change in the loop. However, in such a case, it is desirable that the compiler allocates the data to the register, but if the data cannot be allocated due to the constraint of the number of registers, the above load instruction will be generated. is there.

10 and 11 show a configuration in which a coincidence detection circuit is added to the second embodiment of the present invention and the first embodiment of the present invention, respectively. It functions similarly to the embodiment.

[0047]

As described above, according to the cache prefetch device of the present invention, the data address that will be accessed next time is predicted from the current data address and the previous data address, and the cache memory is stored in the cache memory. Since it can be controlled so that the data is transferred in advance, there is an effect of improving the effective performance when the central processing unit executes the program.

[Brief description of drawings]

FIG. 1 is a first cache prefetch device according to the present invention.
It is a block diagram of one Example.

FIG. 2 is an example of a program applied to the present invention.

FIG. 3 is a conceptual diagram of a cache prefetch device of the present invention.

FIG. 4 is an address generation circuit according to the present invention.

FIG. 5 is a timing diagram according to the first embodiment of the present invention.

FIG. 6 shows a second cache prefetch device according to the present invention.
It is a block diagram of the Example of.

FIG. 7 is a configuration diagram of a main part of a second embodiment of the present invention.

FIG. 8 is a third example of the cache prefetch device of the present invention.
It is a block diagram of the Example of.

FIG. 9 is a fourth example of the cache prefetch device of the present invention.
It is a block diagram of the Example of.

FIG. 10 is a configuration diagram of a fifth embodiment of the cache prefetch device of the present invention.

FIG. 11 is a configuration diagram of a sixth embodiment of the cache prefetch device of the present invention.

[Explanation of symbols]

 10 update means 20-2N instruction address history holding means 30-3N data address history holding means 40-4N address comparison circuit 50 entry selection circuit 60 address selection circuit 70-7N address generation circuit 80 cache control means 90-9N coincidence detection circuit 100 Match detection selection circuit 170 Current data address 670 Previous data address 780 Predicted data address

Claims (11)

[Claims] 1. An address history holding unit including an instruction address history holding unit holding an instruction address and a data address history holding unit holding a data address for a load instruction for fetching data from a storage device; Instruction address comparing means for comparing the instruction address from the instruction address history holding means with the instruction address of the input load instruction to detect a match;
Prediction address generating means for generating a prediction data address from the data address from the data address history holding means of the address history holding means and the data address of the input load instruction based on the comparison result of the instruction address comparing means. And; updating means for storing the instruction address and the data address of the input load instruction in the instruction address history holding means and the data address history holding means, respectively; A cache prefetch device that predicts a data address to be accessed next time and executes control so that the data is transferred to the cache memory in advance from the storage device. 2. The address history holding means includes a plurality of the instruction address history holding means and a plurality of the data address history holding means corresponding to the instruction address history holding means; the instruction address comparing means, A plurality of address comparison circuits for respectively comparing the instruction addresses of the plurality of instruction address history holding means with the instruction address of the input load instruction; and, based on the comparison results of the plurality of address comparison circuits, And an entry selection circuit for determining whether or not they match each other; the predictive address generation means selects at most one of the data addresses from the plurality of data address history holding means according to the address matching information from the entry selection circuit. Address selection circuit, and data address and input from this address selection circuit 2. The cache prefetch device according to claim 1, further comprising an address generation circuit that generates a predicted address from the data address of the loaded load instruction. 3. The address history holding means includes a plurality of the instruction address history holding means and a plurality of the data address history holding means corresponding to the instruction address history holding means; the instruction address comparing means, A plurality of address comparison circuits for respectively comparing the instruction addresses of the plurality of instruction address history holding means with the instruction address of the input load instruction; and, based on the comparison results of the plurality of address comparison circuits, And an entry selection circuit for determining whether or not they match each other; the predictive address generating means predicts each from a data address of the load instruction input corresponding to each of the plurality of data address history holding means. A plurality of address generation circuits that generate addresses and prediction addresses from the plurality of address generation circuits. 2. The cache prefetch device according to claim 1, further comprising an address selection circuit that selects at most one of the addresses according to the address matching information from the entry selection circuit. 4. The address history holding means comprises a plurality of instruction address history holding means composed of a plurality of words, and a plurality of data addresses composed of a plurality of words corresponding to the instruction address history holding means. History holding means; the instruction address comparing means includes a plurality of address comparing circuits for respectively comparing the instruction addresses of the plurality of instruction address history holding means with the instruction address of the input load instruction. An entry selection circuit that determines which of the plurality of address comparison circuits is the same based on the comparison result of the plurality of address comparison circuits; A plurality of addresses for generating a predicted address from the data address of the input load instruction 2. The cache according to claim 1, further comprising a response generation circuit and an address selection circuit that selects at most one of the predicted addresses from the plurality of address generation circuits according to the address matching information from the entry selection circuit. Prefetch device. 5. The address history holding means comprises a plurality of instruction address history holding means composed of a plurality of words, and a plurality of data addresses composed of a plurality of words corresponding to the instruction address history holding means. History holding means; the instruction address comparing means includes a plurality of address comparing circuits for respectively comparing the instruction addresses of the plurality of instruction address history holding means with the instruction address of the input load instruction. An entry selection circuit that determines which of the plurality of address comparison circuits has a match based on the comparison result of the plurality of address comparison circuits; the predicted address generation means includes at most 1 from the data addresses from the plurality of data address history holding means. Address selection information, which is selected according to the address matching information from the entry selection circuit. 2. The cache prefetch device according to claim 1, further comprising a selection circuit and an address generation circuit that generates a predicted address from the data address from the address selection circuit and the data address of the input load instruction. 6. The address history holding means comprises one instruction address history holding means composed of a plurality of words and one data address composed of a plurality of words corresponding to the instruction address history holding means. The cache prefetch device according to claim 1, further comprising history holding means. 7. The predictive address generating means further comprises a coincidence detection circuit for detecting a coincidence of the data address from the data address from the address selection circuit and the data address of the input load instruction. The cache prefetch device according to claim 2. 8. The predictive address generating means detects a plurality of data addresses from a data address of the input load instruction corresponding to each of the data addresses from the plurality of data address history holding means. 4. The match detection circuit according to claim 3, further comprising a match detection selection circuit for selecting at most one of the match detection information from the plurality of match detection circuits according to the address match information from the entry selection circuit. The described cache prefetch device. 9. The predictive address generating means detects a match of data addresses from the data address of the input load instruction corresponding to each of the data addresses from the plurality of data address history holding means. 5. The coincidence detection circuit according to claim 4, further comprising a coincidence detection selection circuit for selecting at most one of the coincidence detection information from the plurality of coincidence detection circuits according to the address coincidence information from the entry selection circuit. The described cache prefetch device. 10. The predictive address generating means further comprises a coincidence detection circuit for detecting a coincidence of the data address from the data address from the address selection circuit and the data address of the input load instruction. The cache prefetch device according to claim 5. 11. The predictive address generating means further comprises a coincidence detecting circuit for detecting a coincidence of the data address from the data address from the data address history holding means and the data address of the input load instruction. The cache prefetch device according to claim 6.