JPH0756537A - Liquid crystal driving circuit - Google Patents

Abstract

PURPOSE:To suppress useless current consumption by forcedly cutting off an output of a driving voltage generating circuit when lighting voltage and turning off voltage for driving a common electrode and a segment electrode constituting a liquid crystal panel are selected. CONSTITUTION:A transmission gate (a third gate) 22 passes or cuts off lighting voltage Von at a prestage of transmission gates 4-1 to 4-m, a transmission gate (a fourth gate) 23 also passes or cuts off turning off voltage Voff at a prestage of transmission gates 5-1 to 5-m. Further, a cut off data generation circuit 24 generates a clock CK' in which a clock CK generated in a control circuit 1 is delayed, while generates cut off data CVon, CVoff which opens and closes the transmission gates 22, 23 respectively. And when lighting voltage and turning off voltage for driving a common electrode and a segment electrode constituting a liquid crystal panel are selected, an output of a driving voltage generation circuit 2 is cut off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive circuit.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a conventional liquid crystal drive circuit. In FIG. 4, (1) is a control circuit for controlling each part of the liquid crystal drive circuit. (2) is a drive voltage generation circuit, which generates a lighting voltage Von and a turn-off voltage Voff for driving a common electrode and a segment electrode which form the liquid crystal panel. Since the selection function of the lighting voltage Von and the extinction voltage Voff is the same for both the common electrode and the segment electrode, the case of driving the segment electrode will be described. (3-1) to (3-m) are output terminals, which are connected to m segment electrodes. (4-
1) to (4-m) are transmission gates (first gates), which output the lighting voltage Von from the output terminals (3-1) to (3-1).
It is derived or blocked from (3-m). (5-
1) to (5-m) are transmission gates (second gates), which output the turn-off voltage Voff from the output terminals (3-1) to (3-1).
It is derived or blocked from (3-m). (6) is an instruction data generation circuit, and instruction data for turning on or off any of the transmission gates (4-1) to (4-m) is set from the control circuit (1). That is, the instruction data is m-bit information that becomes "1" when any of the transmission gates (4-1) to (4-m) is made conductive and becomes "0" when it is cut off. (7) is an instruction data holding circuit, which holds the instruction data in synchronization with the clock CK generated from the control circuit (1). (8-1) to (8-m) are inverters, which correspond to the instruction data output from the instruction data holding circuit (7).
-1) to (4-m) and (5-1) to (5-m) are complementarily conducted or cut off.

FIG. 5 is a specific circuit of the drive voltage generating circuit (2) shown in FIG. 4, which is a circuit for generating a ⅓ bias voltage. In FIG. 5, (9) to (11) are resistors having the same value, which are connected in series between the power supply Vdd and the ground.
(12) is a P-channel type MOS transistor for connecting or disconnecting the power supply Vdd and the resistors (9) to (11). That is, L generated from the control circuit (1)
When CDon is "1", the power supply Vdd and the resistors (9) to (1)
1) is connected. (13) and (14) are transmission gates, one end of which is connected to both ends of the resistors (9) to (11) and the other end of which is commonly connected to derive the lighting voltage Von-seg of the segment electrodes. There is. Reference numeral (15) is an inverter for inverting the clock T output from the control circuit (1). That is, the lighting voltage Von-seg
Becomes Vdd or 0 depending on the level of the clock T. Similarly, (16) and (17) are also transmission gates, one end of which is connected to both ends of the resistors (9) to (11) and the other end of which is commonly connected to derive the lighting voltage Von-com of the common electrode. It has become. That is, the lighting voltage Von-com becomes Vdd or 0 according to the level of the clock T. Similarly,
(18) and (19) are also transmission gates,
One end is connected to both ends of the resistor (10) and the other end is commonly connected to derive the extinguishing voltage Voff-seg of the segment electrode. That is, the turn-off voltage Voff-seg becomes Vdd · 2/3 or Vdd / 3 depending on the level of the clock T.
Similarly, (20) and (21) are also transmission gates, one end of which is connected to both ends of the resistor (10), and the other end of which is commonly connected to derive the turn-off voltage Voff-com of the common electrode. . That is, the turn-off voltage Voff-com becomes Vdd · 2/3 or Vdd / 3 depending on the level of the clock T. Then, by appropriately selecting the lighting voltage or the extinction voltage according to the instruction data of FIG. 4, the common waveform C of FIG.
The OM and segment waveform SEG can be obtained.

[0004]

However, in reality, when the contents of the instruction data holding circuit (7) are transmitted to the transmission gates (4-1) to (4-m), and the instruction data holding circuit (7). When the same contents are transmitted to the transmission gates (5-1) to (5-m) through the inverters (8-1) to (8-m), different delay times are generated. Therefore, when the contents of the instruction data holding circuit (7) are changed, the transmission gates opposite to each other are opened at the same time, and the lighting voltage Von-seg and the turning-off voltage Voff-seg of the segment electrode of FIG. Lighting voltage Von-com and turn-off voltage Vof
There was a problem that f-com was short-circuited, resulting in an increase in current consumption.

Therefore, it is an object of the present invention to provide a liquid crystal drive circuit capable of suppressing current consumption when selecting a turn-on voltage and a turn-off voltage for a liquid crystal panel.

[0006]

The present invention has been made to solve the above-mentioned problems, and is characterized in that it is for driving a common electrode and a segment electrode constituting a liquid crystal panel. A drive voltage generating circuit that generates a lighting voltage and a light-off voltage, first and second gates that complementarily pass or cut off the lighting and light-off voltage, and instruction data that complementarily open and close the first and second gates. And an instruction data holding circuit for holding the instruction data in synchronism with a clock and controlling the opening and closing of the first and second gates according to the instruction data. Third and fourth gates that both pass or shut off, and a shutoff data generation circuit that shuts off both the third and fourth gates when the instruction data holding circuit updates and holds the instruction data Is that with.

[0007]

According to the present invention, the output of the drive voltage generating circuit is cut off when selecting the lighting voltage and the extinguishing voltage for driving the common electrode and the segment electrode which compose the liquid crystal panel. The current consumption can be suppressed.

[0008]

The details of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a liquid crystal drive circuit of the present invention. The same elements in FIGS. 1 and 4 are designated by the same reference numerals. In FIG. 1, reference numeral (22) is a transmission gate (third gate), which includes transmission gates (4-1) to (4-1).
In the preceding stage of (4-m), the lighting voltage Von is passed or cut off. Similarly, (23) is also a transmission gate (fourth gate), which passes or blocks the turn-off voltage Voff before the transmission gates (5-1) to (5-m). Reference numeral (24) is a cutoff data generation circuit, which generates a clock CK 'which is a delayed version of the clock CK generated from the control circuit (1) and cutoff data CVon and CVoff for opening and closing the transmission gates (22) and (23) respectively. It occurs.

FIG. 2 shows the cutoff data generation circuit (24) of FIG.
It is a specific circuit of. In FIG. 2, reference numeral (25) is a delay circuit, which delays the clock CK by the time t to generate the clock CK ′. Similarly, (26) is also a delay circuit, which delays the clock CK 'by the time t'. (27) is an inverter, and a delay circuit (2
The output of 6) is inverted to generate a clock * CK ". (28) is a NAND gate, which is a clock C
K and * CK "are logically ANDed to generate cutoff data CVon and CVoff. At times t and t '.
Is a value that allows the cutoff data CVon and CVoff to be sufficiently "0" before and after the content of the instruction data holding circuit (7) is changed at the rising edge of the clock CK '.

The operation of FIG. 1 will be described below with reference to FIG.
When the clock CK 'rises, the instruction data generation circuit (6)
The instruction data holding circuit (7) holds the m-bit instruction data generated from the transmission gates (4-1) to (4-m) and (5-1) to (5-m). It will be opened and closed according to. However, when the instruction data is changed, the cutoff data CVon and CVoff both become “0”, and the transmission gate (22)
(23) is closed. Therefore, the transmission gates (4-1) to (4-m) and (5-1) to (5-
Even if m) is opened at the same time, the lighting voltage Von and the extinction voltage Voff are not short-circuited. As a result, useless current consumption can be suppressed.

[0011]

According to the present invention, the output of the drive voltage generating circuit can be forcibly cut off when selecting the lighting voltage and the extinguishing voltage for driving the common electrodes and the segment electrodes which compose the liquid crystal panel. As a result, it is possible to obtain an advantage that wasteful current consumption can be suppressed.

[Brief description of drawings]

FIG. 1 is a diagram showing a liquid crystal drive circuit of the present invention.

FIG. 2 is a diagram showing a specific example of the cutoff data generation circuit of FIG.

FIG. 3 is a timing chart showing waveforms at various points in FIG.

FIG. 4 is a conventional liquid crystal drive circuit.

FIG. 5 is a diagram showing a specific example of a drive voltage generation circuit.

FIG. 6 is a diagram showing general common waveforms and segment waveforms.

[Explanation of symbols]

 (2) Drive voltage generation circuit (4-1) to (4-m) Transmission gate (5-1) to (5-m) Transmission gate (6) Instruction data generation circuit (7) Instruction data holding circuit (22) (23) Transmission gate (24) Interruption data generation circuit

Claims (1)

[Claims] 1. A drive voltage generating circuit for generating a lighting voltage and a non-lighting voltage for driving a common electrode and a segment electrode constituting a liquid crystal panel, and a first for complementally passing or blocking the lighting and extinguishing voltage.
And a second gate, an instruction data generating circuit for generating instruction data for opening and closing the first and second gates in a complementary manner, holding the instruction data in synchronization with a clock, and storing the instruction data according to the instruction data. An instruction data holding circuit that controls opening and closing of the first and second gates, third and fourth gates that both pass or block the lighting and extinguishing voltages, and when the instruction data holding circuit updates and holds the instruction data, A cutoff data generation circuit for cutting off both the third and fourth gates, and a liquid crystal drive circuit.